WO2022042020A1 - 静电保护器件及静电保护电路 - Google Patents

静电保护器件及静电保护电路 Download PDF

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Publication number
WO2022042020A1
WO2022042020A1 PCT/CN2021/103818 CN2021103818W WO2022042020A1 WO 2022042020 A1 WO2022042020 A1 WO 2022042020A1 CN 2021103818 W CN2021103818 W CN 2021103818W WO 2022042020 A1 WO2022042020 A1 WO 2022042020A1
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Prior art keywords
projection
electrostatic protection
protection device
terminal
transistor
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PCT/CN2021/103818
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English (en)
French (fr)
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李新
应战
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长鑫存储技术有限公司
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Priority to US17/453,210 priority Critical patent/US11854938B2/en
Publication of WO2022042020A1 publication Critical patent/WO2022042020A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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    • H01L27/0203—Particular design considerations for integrated circuits
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    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits

Definitions

  • the present disclosure relates to, but is not limited to, an electrostatic protection device and an electrostatic protection circuit.
  • Static electricity is everywhere. If there is no electrostatic protection circuit, a chip will soon be damaged by various static electricity, and this damage is usually fatal.
  • the discharge transistor In order to improve the electrostatic discharge capability of the electrostatic protection circuit, the discharge transistor usually needs to have a larger size; in addition, the pulse characteristics of the electrostatic protection circuit determine that the resistance and capacitance will occupy a larger chip area, plus a larger discharge The area of the transistor makes the effective area of the electrostatic protection circuit applied to the chip pin larger.
  • An embodiment of the present disclosure provides an electrostatic protection device, including: a discharge transistor, located on a substrate, and configured to discharge electrostatic charges; a first pad, located on a first metal layer, and a drain region of the discharge transistor electrical connection; wherein the projection of the first pad on the substrate partially overlaps the projection of the drain region on the substrate.
  • An embodiment of the present disclosure further provides an electrostatic protection circuit, including: the electrostatic protection device described above; a power terminal, electrically connected to the first pad; and a ground terminal, electrically connected to the source region of the discharge transistor .
  • An embodiment of the present disclosure further provides an electrostatic protection circuit, including: the electrostatic protection device described above; an input and output end, which is electrically connected to the first pad; wherein the discharge transistor is a P-type transistor, and the electrostatic protection circuit further includes a power supply The power supply terminal is electrically connected to the source region of the bleeder transistor; or the bleeder transistor is an N-type transistor, and the electrostatic protection circuit further includes a ground terminal, which is electrically connected to the source region of the bleeder transistor.
  • FIG. 1 is a front view of an electrostatic protection device according to an embodiment of the disclosure
  • FIG. 2 is a top view of an electrostatic protection device according to an embodiment of the disclosure.
  • FIG. 3 is a perspective view of a partial structure of an electrostatic protection device according to an embodiment of the disclosure.
  • FIG. 4 is a schematic partial cross-sectional structural diagram of an electrostatic protection device according to an embodiment of the disclosure.
  • FIG. 5 is a schematic cross-sectional structure diagram of a gate structure according to an embodiment of the disclosure.
  • FIG. 6 is a schematic structural diagram of an electrostatic protection device according to an embodiment of the disclosure.
  • FIG. 7 is a schematic structural diagram of an electrostatic protection device according to an embodiment of the disclosure.
  • FIG. 8 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the disclosure.
  • FIG. 9 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the disclosure.
  • FIG. 10 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the disclosure.
  • FIG. 11 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the disclosure.
  • FIG. 12 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the disclosure.
  • FIG. 13 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the disclosure.
  • the electrostatic protection device and the electrostatic protection circuit provided by the present disclosure reduce the effective chip area of the electrostatic protection device and improve the electrostatic discharge speed and discharge capability of the electrostatic protection device.
  • FIGS. 1 to 3 are schematic structural diagrams of an electrostatic protection device according to an embodiment of the present disclosure; wherein, FIG. 1 is a front view of the electrostatic protection device, FIG. 2 is a top view of the electrostatic protection device, and FIG. 3 It is a perspective view of the partial structure of the electrostatic protection device.
  • the electrostatic protection device includes: a discharge transistor 11, located on the substrate 10, for discharging electrostatic charges; a first pad 12, located on the first metal layer M1, electrically connected to the drain region 111 of the discharge transistor 11; wherein , the projection of the first pad 12 on the substrate 10 partially overlaps the projection of the drain region 111 on the substrate 10 .
  • the projection of the first pad 12 on the substrate 10 is denoted as the first projection
  • the projection of the drain region 111 on the substrate 10 is denoted as the second projection
  • the first projection is located in the second projection Inside.
  • the electrostatic protection device further includes: a second metal layer M2 located between the first metal layer M1 and the drain region 111 , and the second metal layer M2 and the first metal layer M1 pass through the conductive plug 131 For electrical connection, the drain region 111 and the second metal layer M2 are electrically connected through the first contact hole 132 .
  • the material of 132 is different.
  • the material of the conductive plug 131 is usually a metal, such as copper or aluminum or cobalt or nickel or an alloy composed of various metals, etc.
  • the material of the first contact hole 132 is usually a metal semiconductor material, such as cobalt silicide, Nickel Silicide, etc.
  • the projection of the conductive plug 131 on the substrate 10 is denoted as the third projection
  • the projection of the first contact hole 132 on the substrate 10 is denoted as the fourth projection
  • the third projection and the fourth projection are located in the second projection. In this way, it is beneficial to reduce the effective area of the electrostatic protection device.
  • the fourth projection also lies within the first projection.
  • the first pad 12 and the drain region 111 can be connected by vertical wiring, without increasing the conduction path length of the discharge current in the second metal layer M2 and the conductive plug 131, which is beneficial to reduce the discharge current
  • the parasitic resistance of the flow path improves the discharge capability of the electrostatic protection device.
  • a plurality of first contact holes 132 form a first contact hole array 132 a , and the first contact hole array 132 a is centrally symmetric with respect to the center of the drain region 111 . In this way, it is beneficial to ensure that the bleeder current flowing to the source electrode 112 (refer to FIG. 1 ) through the first contact hole 132 has better uniformity, thereby ensuring that the bleeder transistor 11 has a good bleeder capability.
  • a plurality of first contact holes with smaller dimensions may also be combined to form first contact holes with larger cross-sectional dimensions, thereby further reducing the parasitic resistance of the first contact holes and further improving the leakage of the electrostatic protection device. release ability.
  • the conductive plug 131 and the first contact hole 132 are both completely located under the first pad 12 , and the ESD discharge current is conducted from the first pad 12 through the conductive plug 131 .
  • the plug 131 is connected to the second metal layer M2, and then to the drain region 111 of the discharge transistor 11 through the first contact hole 132.
  • the ESD discharge current path is the shortest, thereby further improving the discharge capability of the electrostatic protection device.
  • the first contact hole 132 can even get rid of the limitation of the DRC rule.
  • the 4x4 first contact hole 132 in FIG. 2 is made into a large contact hole, so that the parasitic resistance on the current discharge path is smaller, thereby further improving the The discharge capability of the electrostatic protection device.
  • the first contact hole 132 is a recessed contact hole, that is, a part of the first contact hole 132 is located in the drain region 111 . In this way, it is beneficial to further reduce the contact resistance between the first contact hole 132 and the drain region 111 , thereby improving the electrostatic discharge capability of the electrostatic protection device.
  • the gate structure 113 of the bleeder transistor 11 (refer to FIG. 1 ) is in a ring shape, and the distances from the outer edge of the first contact hole array 132 a to the inner edge of the gate structure 113 are equal .
  • there are a first distance d1 , a second distance d2 , and a third distance between the outer edge of the first contact hole array 132a and the inner edge of the gate structure 113 d3 and the fourth pitch d4 are equal to the first pitch d1, the second pitch d2, the third pitch d3, and the fourth pitch d4.
  • the source region 112 of the bleeder transistor 11 is connected to the second contact hole 133, and the distance from the second contact hole 133 to the gate structure 113 of the bleeder transistor 11 is less than The distance from the first contact hole 132 to the gate structure 113 of the bleeder transistor 11 .
  • the drain transistor 11 has good drain capability and strong reliability.
  • the LDD structure may not be disposed between the drain region 111 and the source region 112 to further reduce the on-resistance, improve the discharge capability and reduce heat generation; A well region is added below 111 , or the drain region 111 and the source region 112 are placed in the well region as a whole, so as to reduce the leakage problem of the drain transistor 11 .
  • the gate structure 113 of the bleeder transistor 11 has a ring shape, and the drain region 111 is located in the gate structure 113 . In this way, it is beneficial to further improve the uniformity of the discharge current.
  • the annular shape includes regular polygons such as quadrilaterals, hexagons, and octagons, and the number of side bars of the regular polygons is an even number.
  • the inner corners of the annular shape are all greater than 90 degrees.
  • the inner contour of the annular shape has a first corner ⁇ 1, and the outer contour has a second corner ⁇ 2.
  • the chamfer is set at the position so that the first corner ⁇ 1 and the second corner ⁇ 2 of the annular shape are greater than 90 degrees. In this way, it is beneficial to reduce the current impact intensity at the corners of the gate structure 113 , avoid premature aging and damage of the corners due to excessive current impact, and ensure that the discharge transistor 11 has a longer service life.
  • the small sides formed by the chamfering are not included in the number of side edges of the annular shape; in addition, in other embodiments, only the first corner of the inner contour or the second corner of the outer contour may be adjusted, that is, only the first corner of the inner contour or the second corner of the outer contour may be adjusted.
  • Chamfers are set at the corners of the inner or outer contour.
  • the gate structure 213 when the gate structure 213 has a non-ring shape, the gate structure 213 is center-symmetrical with respect to the center point 211 a of the drain region 211 .
  • the center point 211a and the gate structure 213 In different directions from the center point 211a toward the gate structure 213, the center point 211a and the gate structure 213 have a first center distance d21, a second center distance d22, a third center distance d23, and a fourth center distance d24, and the first The center-to-center distance d21, the second center-to-center distance d22, the third center-to-center distance d23, and the fourth center-to-center distance d24 are equal. In this way, it is beneficial to ensure the uniformity of the discharge current of the discharge transistor.
  • the area of the drain region 111 is larger than that of the source region 112 of the bleeder transistor 11 . In this way, it is beneficial to ensure that the drain region 111 has better heat dissipation capability.
  • the electrostatic protection device further includes a third metal layer 151 and a fourth metal layer 152 , and the third metal layer 151 , the fourth metal layer 152 and the second metal layer M2 are disposed in the same layer , the third metal layer 151 is connected to the second contact hole 133 .
  • the third metal layer 151 is further connected to the ground terminal for discharging the electrostatic current of the power terminal to the ground terminal.
  • the fourth metal layer 152 is electrically connected to the second metal layer M2 to extract the voltage of the drain region 111 .
  • the second metal layer M2 is connected to the power terminal, and the fourth metal layer 152 is used to electrically connect the power terminal to other circuits.
  • the fourth metal layer 152 is connected to the corner of the second metal layer M2, thus, a larger space is reserved for the third metal layer 151; in other embodiments, referring to FIG. 7, in the gate On one side of the pole structure 213, the third metal layer 251 and the fourth metal layer 252 are arranged at intervals.
  • the second metal layer M2 , the third metal layer 151 , and the fourth metal layer 152 can be chamfered, similar to the chamfer structure in FIG. 5 .
  • the treatment can also reduce the impact of the current on the metal layer, thereby improving the lifespan of the metal layer and the reliability of the metal layer.
  • the electrostatic protection device further includes: a wire bonding pad 14 located on the redistribution metal layer M3, the wire bonding pad 14 is electrically connected to the first pad 12, and the redistribution metal layer M3 is located on the first metal layer M3. Above the layer M1 , that is, on the side of the first metal layer M1 away from the substrate 10 .
  • the space originally reserved for wire bonding on the first pad 12 can be omitted, thereby reducing the size of the first pad 12, for example, the reduced
  • the size of the first pad 12 in a direction parallel to the surface of the substrate 10 may be less than or equal to 30 ⁇ m ⁇ 30 ⁇ m, or even smaller.
  • the electrostatic protection device further includes: a redistribution via 141 for electrically connecting the first metal layer M1 and the redistribution metal layer M3.
  • the projection of the first pad 12 on the substrate 10 is denoted as the first projection
  • the projection of the drain region 111 on the substrate 10 is denoted as In the second projection
  • the projection of the wiring through hole 141 on the substrate 10 is the fifth projection
  • the projection of the wiring pad 14 on the substrate 10 is the sixth projection
  • the first projection and the fifth projection are both located in the first projection and the fifth projection.
  • the sixth projection is outside the second projection.
  • the area of the wire bonding pad 14 is larger than that of the first bonding pad 12 , for example, the area of the wire bonding pad 14 is equal to 60 ⁇ m ⁇ 60 ⁇ m. In this way, it is beneficial to reduce the difficulty of wire bonding of the electrostatic protection device.
  • the projection of the first pad 14 partially overlaps the projection of the drain region 111 , which is beneficial to reduce the effective chip area of the electrostatic protection device, and further, in the direction parallel to the surface of the substrate 10 , is Space is reserved for other electronic components; in addition, the overlapping projections are also beneficial to shorten the length of the wire between the first pad 14 and the drain region 111, thereby reducing the parasitic resistance and parasitic capacitance on the electrostatic discharge path, thereby improving the static electricity The discharge speed and discharge capacity of the protection device.
  • an embodiment of the present disclosure further provides an electrostatic protection circuit, and the electrostatic protection circuit includes any of the electrostatic protection devices described above.
  • the electrostatic protection circuit includes: the electrostatic protection device 31 according to any one of the above; a power supply terminal VDD, which is electrically connected to the first pad 14; connect.
  • the electrostatic protection circuit further includes: an electrostatic pulse sensing circuit 32, connected between the power terminal VDD and the ground terminal VSS, for sensing the electrostatic pulse of the power terminal VDD, and outputting a pulse identification signal,
  • the bleeder transistor 11 is turned on or off according to the pulse identification signal.
  • the electrostatic pulse sensing circuit 32 includes a capacitor 321 and a resistor 322.
  • the first terminal of the capacitor 321 is connected to the power supply terminal VDD, the second terminal of the capacitor 321 is connected to the first terminal of the resistor 322, and the second terminal of the resistor 322 is connected to ground.
  • the terminal VSS, the second terminal of the capacitor 321 is connected to the gate structure 113 of the bleeder transistor 11 .
  • FIG. 9 in order to illustrate a concise drawing method of the electrostatic protection circuit, a discharge transistor 11 is used to illustrate the electrostatic protection device 31 , and the same simple drawing method in other subsequent figures will not be described again.
  • the electrostatic protection circuit further includes: a drive circuit 43 connected between the power supply terminal VDD and the ground terminal VSS, and the drive circuit 43 receives the pulse identification signal output by the electrostatic pulse sensing circuit 42 and sends it to the The electrostatic protection device 41 outputs a driving signal, and the driving signal is connected to the gate structure of the discharge transistor.
  • the electrostatic pulse sensing circuit 42 (refer to FIG. 10 ) includes a resistor 421 and a capacitor 422 , the first terminal of the resistor 421 is connected to the power supply terminal VDD, the second terminal of the resistor 421 is connected to the first terminal of the capacitor 422 , and the The second terminal is connected to the ground terminal VSS;
  • the driving circuit 43 (refer to FIG. 10 ) includes an inverter 431 , the input terminal of the inverter 431 is connected to the second terminal of the resistor 421 , and the output terminal of the inverter 431 is connected to the bleeder transistor 41 . gate structure.
  • an electrostatic protection circuit applicable between a power supply terminal and a ground terminal is provided, which is beneficial to improve the electrostatic discharge capability between the power supply terminal and the ground terminal.
  • an embodiment of the present disclosure further provides an electrostatic protection circuit, and the electrostatic protection circuit includes any of the electrostatic protection devices described above.
  • the electrostatic protection circuit includes: any one of the electrostatic protection devices described above; an input and output terminal I/O, which is electrically connected to the first pad;
  • the source region of the bleeder transistor 61 is electrically connected to the gate structure of the bleeder transistor 61 , and the bleeder transistor 61 is a P-type transistor.
  • an electrostatic protection circuit applicable between the input and output terminals and the power supply terminal is provided, which is beneficial to improve the electrostatic discharge capability between the input and output terminals and the power supply terminal.
  • the electrostatic protection circuit includes: any one of the electrostatic protection devices described above; an input and output terminal I/O, which is electrically connected to the first pad;
  • the source region of the bleeder transistor 51 is electrically connected to the gate structure of the bleeder transistor 51 , and the bleeder transistor 51 is an N-type transistor.
  • an electrostatic protection circuit applicable between the input and output terminals and the ground terminal is provided, which is beneficial to improve the electrostatic discharge capability between the input and output terminals and the ground terminal.
  • the projection of the first pad overlaps with the projection of the drain region, which is beneficial to reduce the effective chip area of the electrostatic protection device.
  • the overlap of the projection part is also conducive to shortening the length of the wire between the first pad and the drain region, reducing the parasitic resistance and parasitic capacitance on the electrostatic discharge path, and improving the performance of the electrostatic protection device. Release speed and release capacity.

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Abstract

本公开提供一种静电保护器件及静电保护电路，静电保护器件包括：泄放晶体管，位于衬底上，用于泄放静电电荷；第一焊盘，位于第一金属层，与所述泄放晶体管的漏极区电连接；其中，所述第一焊盘在所述衬底上的投影与所述漏极区在所述衬底上的投影部分重叠。

Description

静电保护器件及静电保护电路
本公开要求在2020年08月26日提交中国专利局、申请号为202010872697.7、发明名称为“静电保护器件及静电保护电路”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种静电保护器件及静电保护电路。
背景技术
静电无处不在，假如没有静电保护电路，一块芯片很快会被各种各样的静电所损伤，且这种损伤通常是致命的。
为了提高静电保护电路的静电泄放能力，泄放晶体管通常需要有较大尺寸；此外，静电保护电路的脉冲特性决定了电阻和电容会占用较大的芯片面积，再加上较大的泄放晶体管的面积，使得应用于芯片管脚的静电保护电路的有效面积较大。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种静电保护器件，包括：泄放晶体管，位于衬底上，设置为泄放静电电荷；第一焊盘，位于第一金属层，与所述泄放晶体管的漏极区电连接；其中，所述第一焊盘在所述衬底上的投影与所述漏极区在所述衬底上的投影部分重叠。
本公开实施例还提供一种静电保护电路，包括：上述所述的静电保护器件；电源端，与所述第一焊盘电连接；接地端，与所述泄放晶体管的源极区电连接。
本公开实施例还提供一种静电保护电路，包括：上述所述的静电保护器件；输入输出端，与第一焊盘电连接；其中，泄放晶体管为P型晶体管，静 电保护电路还包括电源端，电源端与泄放晶体管的源极区电连接；或泄放晶体管为N型晶体管，静电保护电路还包括接地端，接地端与泄放晶体管的源极区电连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制，对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开一实施例的静电保护器件的主视图；
图2为本公开一实施例的静电保护器件的俯视图；
图3为本公开一实施例的静电保护器件的局部结构立体图；
图4为本公开一实施例的静电保护器件的局部剖面结构示意图；
图5为本公开一实施例的栅极结构的剖面结构示意图；
图6为本公开一实施例的的静电保护器件的结构示意图；
图7为本公开一实施例的的静电保护器件的结构示意图；
图8为本公开一实施例的静电保护电路的结构示意图；
图9为本公开一实施例的静电保护电路的结构示意图；
图10为本公开一实施例的静电保护电路的结构示意图；
图11为本公开一实施例的静电保护电路的结构示意图；
图12为本公开一实施例的静电保护电路的结构示意图；
图13为本公开一实施例的静电保护电路的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改， 也可以实现本申请所要求保护的技术方案。
随着芯片管脚的数量逐渐增多，减小静电保护电路的电路有效面积成为非常值得尝试的优化方向。本公开所提供的静电保护器件及静电保护电路减小了静电保护器件的有效芯片面积，提高了静电保护器件的静电泄放速度和泄放能力。
参考图1至图3，图1至图3为本公开一实施例提供的静电保护器件的结构示意图；其中，图1为静电保护器件的主视图，图2为静电保护器件的俯视图，图3为静电保护器件的局部结构立体图。
静电保护器件包括：泄放晶体管11，位于衬底10上，用于泄放静电电荷；第一焊盘12，位于第一金属层M1，与泄放晶体管11的漏极区111电连接；其中，第一焊盘12在衬底10上的投影与漏极区111在衬底10上的投影部分重叠。
本公开的一些实施例中，记第一焊盘12在衬底10上的投影为第一投影，记漏极区111在衬底10上的投影为第二投影，第一投影位于第二投影内。如此，有利于进一步减小静电保护器件的有效面积，进而在平行于衬底10表面的方向上，为其他电子元件预留更多空间；同时，第一焊盘12到达漏极区111的距离最短，有利于提高静电保护器件的静电泄放能力。
本公开的一些实施例中，静电保护器件还包括：第二金属层M2，位于第一金属层M1和漏极区111之间，第二金属层M2与第一金属层M1通过导电插塞131电连接，漏极区111与第二金属层M2通过第一接触孔132电连接。
在第一金属层M1和第二金属层M2之间，还可以具有一层或多层金属层，相邻金属层之间可通过导电插塞131电连接；导电插塞131与第一接触孔132的材料不同，导电插塞131的材料通常为金属，例如铜或铝或钴或镍或由多种金属组成的合金等，第一接触孔132的材料通常为金属半导体材料，例如硅化钴、硅化镍等等。
本公开的一些实施例中，记导电插塞131在衬底10上的投影为第三投影，记第一接触孔132在衬底10上的投影为第四投影，第三投影和第四投影均位于第二投影内。如此，有利于减小静电保护器件的有效面积。
第四投影还位于第一投影内。如此，可通过垂直连线的方式将第一焊盘 12与漏极区111连接，无需增加泄放电流在第二金属层M2和导电插塞131内的导电路径长度，有利于降低泄放电流流通路径的寄生电阻，提高静电保护器件的泄放能力。
本公开的一些实施例中，参考图4，多个第一接触孔132组成第一接触孔阵列132a，第一接触孔阵列132a相对于漏极区111的中心呈中心对称。如此，有利于保证经由第一接触孔132流向源极112(参考图1)的泄放电流具有较好的均匀性，进而保证泄放晶体管11具有良好的泄放能力。
在其他实施例中，还可以合并多个尺寸较小的第一接触孔，形成横截面尺寸较大的第一接触孔，从而进一步降低第一接触孔的寄生电阻，进一步提高静电保护器件的泄放能力。
继续参考图1、图2和图3，在一种实施例中，导电插塞131和第一接触孔132均完全位于第一焊盘12下方，ESD泄放电流从第一焊盘12经导电插塞131到第二金属层M2，再经第一接触孔132到泄放晶体管11的漏极区111，如此，ESD泄放电流路径最短，从而进一步提高静电保护器件的泄放能力。第一接触孔132甚至可以摆脱DRC rule的限制，例如，将图2中4x4的第一接触孔132做成1个大的接触孔，这样电流泄放路径上的寄生电阻更小，从而进一步提高静电保护器件的泄放能力。
本公开的一些实施例中，第一接触孔132为凹槽型接触孔，即第一接触孔132部分位于漏极区111内。如此，有利于进一步降低第一接触孔132与漏极区111之间的接触电阻，进而提高静电保护器件的静电泄放能力。
本公开的一些实施例中，参考图4，泄放晶体管11(参考图1)的栅极结构113呈环形形状，第一接触孔阵列132a的外边缘到栅极结构113的内边缘的距离相等。在第一接触孔阵列132a朝向栅极结构113的不同方向上，第一接触孔阵列132a的外边缘到栅极结构113的内边缘之间具有第一间距d1、第二间距d2、第三间距d3以及第四间距d4，第一间距d1、第二间距d2、第三间距d3以及第四间距d4相等。
如此，有利于使得泄放电流在第一接触孔阵列132a朝向栅极结构113的多个方向上均匀流动，保证泄放晶体管11具有良好的电流泄放能力。
继续参考图1和图2，本公开的一些实施例中，泄放晶体管11的源极区112接第二接触孔133，第二接触孔133到泄放晶体管11的栅极结构113的 距离小于第一接触孔132到泄放晶体管11的栅极结构113的距离。如此，有利于使得漏极区111在泄放电流流通路径上具有较大的暴露面积，从而使得漏极区111具有较好的散热能力，避免漏极区111因电流较大而发生过热损坏，进而使得泄放晶体管11具有良好的泄放能力和较强的可靠性。
本公开的一些实施例中，漏极区111与源极区112之间可以不设置LDD结构，以进一步减小导通电阻，提高泄放能力以及减小发热；此外，还可以在漏极区111下方增加阱区，或者将漏极区111和源极区112整体置于阱区内，从而减轻泄放晶体管11的漏电问题。
本公开的一些实施例中，泄放晶体管11的栅极结构113呈环形形状，漏极区111位于栅极结构113内。如此，有利于进一步提高泄放电流的均匀性。
本公开的一些实施例中，环形形状包括四边形、六边形、八边形等正多边形，且正多边形的侧边条数为偶数。
本公开的一些实施例中，环形形状的内部拐角均大于90度。参考图5，以栅极结构113的环形形状为正四边形为例，环形形状的内轮廓具有第一拐角θ1，外轮廓具有第二拐角θ2，通过在环形形状的内轮廓拐角处和外轮廓拐角处设置倒角，使得环形形状的第一拐角θ1和第二拐角θ2大于90度。如此，有利于降低栅极结构113拐角处的电流冲击强度，避免拐角因电流冲击过强而提前老化以及损坏，保证泄放晶体管11具有较长的使用寿命。
设置倒角所形成的小侧边并不算入环形形状的侧边条数；此外，在其他实施例中，也可仅对内轮廓的第一拐角或外轮廓的第二拐角进行调整，即仅在内轮廓或外轮廓的拐角处设置倒角。
本公开的一些实施例中，参考图6，当栅极结构213为非环形形状时，栅极结构213相对于漏极区211的中心点211a呈中心对称。在中心点211a朝向栅极结构213的不同方向上，中心点211a与栅极结构213具有第一中心间距d21、第二中心间距d22、第三中心间距d23以及第四中心间距d24，且第一中心间距d21、第二中心间距d22、第三中心间距d23以及第四中心间距d24相等。如此，有利于保证泄放晶体管的泄放电流均匀性。
本公开的一些实施例中，漏极区111的面积大于泄放晶体管11的源极区112的面积。如此，有利于保证漏极区111具有较好的散热能力。
继续参考图2，本公开的一些实施例中，静电保护器件还包括第三金属层151和第四金属层152，第三金属层151、第四金属层152以及第二金属层M2同层设置，第三金属层151连接第二接触孔133。在一种实施例中，例如第三金属层151进一步与接地端连接，用于将电源端的静电电流泄放到接地端。第四金属层152与第二金属层M2电连接，以引出漏极区111的电压。在一种实施例中，例如第二金属层M2连接电源端，第四金属层152用于将电源端电连接到其他电路。
本公开的一些实施例中，第四金属层152与第二金属层M2的拐角连接，如此，为第三金属层151预留较大的空间；在其他实施例中，参考图7，在栅极结构213的一侧，第三金属层251和第四金属层252间隔排列。
继续参考图2，本公开的一些实施例中，第二金属层M2、第三金属层151、第四金属层152均可做倒角处理，类似于图5的倒角结构，这样的倒角处理同样能够减小电流对金属层的冲击，进而提高金属层的寿命和金属层的可靠性。
本公开的一些实施例中，静电保护器件还包括：打线焊盘14，位于重布线金属层M3，打线焊盘14与第一焊盘12电连接，重布线金属层M3位于第一金属层M1上方，即位于第一金属层M1远离衬底10的一侧。
由于不再需要利用第一焊盘12进行打线键合，因此可省略第一焊盘12原本为打线键合预留的空间，从而缩小第一焊盘12的尺寸，例如，缩小后的第一焊盘12在平行于衬底10表面方向上的尺寸可小于等于30μm×30μm，甚至可以更小。
本公开的一些实施例中，静电保护器件还包括：重布线通孔141，用于将第一金属层M1和重布线金属层M3进行电连接。
继续参考图1、图2和图3，本公开的一些实施例中，记第一焊盘12在衬底10上的投影为第一投影，记漏极区111在衬底10上的投影为第二投影，记重布线通孔141在衬底10上的投影为第五投影，记打线焊盘14在衬底10上的投影为第六投影，第一投影、第五投影均位于第二投影内，第六投影位于第二投影外。通过片上重布线层技术(On Die RDL)重新定义用于打线键合的焊盘的位置，有利于避免打线焊盘14的打线键合的应力对泄放晶体管11的漏极区111造成影响，从而保证泄放晶体管11具有良好的泄放 能力。
本公开的一些实施例中，打线焊盘14的面积大于第一焊盘12的面积，例如，打线焊盘14的面积等于60μm×60μm。如此，有利于降低静电保护器件的打线键合的难度。
本公开的一些实施例中，第一焊盘14的投影与漏极区111的投影部分重叠，有利于减小静电保护器件的有效芯片面积，进而在平行于衬底10表面的方向上，为其他电子元件预留空间；此外，投影部分重叠，还有利于缩短第一焊盘14与漏极区111之间的导线长度，从而降低静电泄放路径上的寄生电阻和寄生电容，从而提高静电保护器件的泄放速度和泄放能力。
相应地，本公开实施例还提供一种静电保护电路，静电保护电路包括上述任一项的静电保护器件。
参考图1和图8，静电保护电路包括：上述任一项的静电保护器件31；电源端VDD，与第一焊盘14电连接；接地端VSS，与泄放晶体管11的源极区112电连接。
本公开的一些实施例中，静电保护电路还包括：静电脉冲感测电路32，连接于电源端VDD和接地端VSS之间，用于感测电源端VDD的静电脉冲，并输出脉冲标识信号，泄放晶体管11根据脉冲标识信号打开或关断。
参考图9，静电脉冲感测电路32包括电容321和电阻322，电容321的第一端接电源端VDD，电容321的第二端接电阻322的第一端，电阻322的第二端接接地端VSS，电容321的第二端接泄放晶体管11的栅极结构113。
图9为了图示静电保护电路的简洁画法，采用泄放晶体管11示意静电保护器件31，后续其他图示中的相同简洁画法不再进行说明。
在其他实施例中，参考图10，静电保护电路还包括：驱动电路43，连接于电源端VDD和接地端VSS之间，驱动电路43接收静电脉冲感测电路42输出的脉冲标识信号，并向静电保护器件41输出驱动信号，驱动信号连接于泄放晶体管的栅极结构。
参考图11，静电脉冲感测电路42(参考图10)包括电阻421和电容422，电阻421的第一端接电源端VDD，电阻421的第二端接电容422的第一端， 电容422的第二端接接地端VSS；驱动电路43(参考图10)包括反相器431，反相器431的输入端接电阻421的第二端，反相器431的输出端接泄放晶体管41的栅极结构。
本公开的一些实施例中，提供了一种可应用于电源端和接地端之间的静电保护电路，有利于提高电源端与接地端之间静电泄放能力。
相应地，本公开实施例还提供一种静电保护电路，静电保护电路包括上述任一项的静电保护器件。
参考图13，静电保护电路包括：上述任一项的静电保护器件；输入输出端I/O，与第一焊盘电连接；电源端VDD，与泄放晶体管61的源极区连接。
泄放晶体管61的源极区与泄放晶体管61的栅极结构电连接，泄放晶体管61为P型晶体管。
本实施例中，提供了一种可应用于输入输出端和电源端之间的静电保护电路，有利于提高输入输出端与电源端之间静电泄放能力。
参考图12，静电保护电路包括：上述任一项的静电保护器件；输入输出端I/O，与第一焊盘电连接；接地端VSS，与泄放晶体管51的源极区连接。
泄放晶体管51的源极区与泄放晶体管51的栅极结构电连接，泄放晶体管51为N型晶体管。
本实施例中，提供了一种可应用于输入输出端和接地端之间的静电保护电路，有利于提高输入输出端与接地端之间静电泄放能力。
本领域技术人员在考虑说明书及实践的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
工业实用性
本公开所提供的静电保护器件及静电保护电路，第一焊盘的投影与漏极区的投影部分重叠，有利于减小静电保护器件的有效芯片面积，在平行于衬底表面的方向上，为其他电子元件预留空间；此外，投影部分重叠，还有利于缩短第一焊盘与漏极区之间的导线长度，降低静电泄放路径上的寄生电阻和寄生电容，提高静电保护器件的泄放速度和泄放能力。

Claims (20)

  1. 一种静电保护器件，包括：
    泄放晶体管，位于衬底上，设置为泄放静电电荷；
    第一焊盘，位于第一金属层，与所述泄放晶体管的漏极区电连接；
    其中，所述第一焊盘在所述衬底上的投影与所述漏极区在所述衬底上的投影部分重叠。
  2. 根据权利要求1所述的静电保护器件，其中，记所述第一焊盘在所述衬底上的投影为第一投影，记所述漏极区在所述衬底上的投影为第二投影，所述第一投影位于所述第二投影内。
  3. 根据权利要求2所述的静电保护器件，所述静电保护器件还包括：
    第二金属层，位于所述第一金属层和所述漏极区之间，所述第二金属层与所述第一金属层通过导电插塞电连接，所述漏极区与所述第二金属层通过第一接触孔电连接。
  4. 根据权利要求3所述的静电保护器件，其中，记所述导电插塞在所述衬底上的投影为第三投影，记所述第一接触孔在所述衬底上的投影为第四投影，所述第三投影和所述第四投影均位于所述第二投影内。
  5. 根据权利要求4所述的静电保护器件，其中，多个所述第一接触孔组成第一接触孔阵列，所述第一接触孔阵列相对于所述漏极区的中心呈中心对称。
  6. 根据权利要求5所述的静电保护器件，其中，所述第一接触孔为凹槽型接触孔。
  7. 根据权利要求5所述的静电保护器件，其中，所述泄放晶体管的栅极结构呈环形形状，所述第一接触孔阵列的外边缘到对应的所述栅极结构的内边缘的距离相等。
  8. 根据权利要求5所述的静电保护器件，其中，所述泄放晶体管的源极区接第二接触孔，所述第二接触孔到所述泄放晶体管的栅极结构的距离小于所述第一接触孔到所述泄放晶体管的栅极结构的距离。
  9. 根据权利要求1所述的静电保护器件，其中，所述泄放晶体管的栅极结构呈环形形状，所述漏极区位于所述栅极结构内；
    其中，所述环形形状包括四边形、六边形、八边形；
    所述环形形状的内部拐角均大于90度。
  10. 根据权利要求1所述的静电保护器件，其中，所述泄放晶体管的栅极结构相对于所述漏极区的中心点呈中心对称。
  11. 根据权利要求1所述的静电保护器件，其中，所述漏极区的面积大于所述泄放晶体管的源极区的面积。
  12. 根据权利要求1所述的静电保护器件，所述静电保护器件还包括：
    打线焊盘，位于重布线金属层，所述打线焊盘与所述第一焊盘电连接，所述重布线金属层位于所述第一金属层上方；
    重布线通孔，设置为将所述第一金属层和所述重布线金属层进行电连接。
  13. 根据权利要求12所述的静电保护器件，其中，记所述第一焊盘在所述衬底上的投影为第一投影，记所述漏极区在所述衬底上的投影为第二投影，记所述重布线通孔在所述衬底上的投影为第五投影，记所述打线焊盘在所述衬底上的投影为第六投影，所述第一投影、所述第五投影均位于所述第二投影内，所述第六投影位于所述第二投影外；
    其中，所述打线焊盘的面积大于所述第一焊盘的面积。
  14. 一种静电保护电路，包括：
    如权利要求1所述的静电保护器件；
    电源端，与所述第一焊盘电连接；
    接地端，与所述泄放晶体管的源极区电连接。
  15. 根据权利要求14所述的静电保护电路，所述静电保护电路还包括：
    静电脉冲感测电路，连接于所述电源端和所述接地端之间，设置为感测所述电源端的静电脉冲，并输出脉冲标识信号，所述泄放晶体管根据所述脉冲标识信号打开或关断。
  16. 根据权利要求15所述的静电保护电路，所述静电保护电路还包括：
    驱动电路，连接于所述电源端和所述接地端之间，所述驱动电路接收所述脉冲标识信号，并输出驱动信号，所述驱动信号连接于所述泄放晶体管的 栅极结构。
  17. 根据权利要求16所述的静电保护电路，其中，所述静电脉冲感测电路包括电阻和电容，所述电阻的第一端接所述电源端，所述电阻的第二端接所述电容的第一端，所述电容的第二端接所述接地端；
    所述驱动电路包括反相器，所述反相器的输入端接所述电阻的第二端，所述反相器的输出端接所述泄放晶体管的栅极结构。
  18. 根据权利要求15所述的静电保护电路，其中，所述静电脉冲感测电路包括电阻和电容，所述电容的第一端接所述电源端，所述电容的第二端接所述电阻的第一端，所述电阻的第二端接所述接地端，所述电容的第二端接所述泄放晶体管的栅极结构。
  19. 一种静电保护电路，包括：
    如权利要求1所述的静电保护器件；
    输入输出端，与所述第一焊盘电连接；
    其中，所述泄放晶体管为P型晶体管，所述静电保护电路还包括电源端，所述电源端与所述泄放晶体管的源极区电连接；
    或所述泄放晶体管为N型晶体管，所述静电保护电路还包括接地端，所述接地端与所述泄放晶体管的源极区电连接。
  20. 根据权利要求19所述的静电保护电路，其中，所述泄放晶体管的源极区与所述泄放晶体管的栅极结构电连接。
PCT/CN2021/103818 2020-08-26 2021-06-30 静电保护器件及静电保护电路 WO2022042020A1 (zh)

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