CN108091628B - 半导体装置 - Google Patents
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Abstract
一种半导体装置,能够减少引线的连接不良,能够提高可靠性。半导体装置(1)包括半导体基板(2)、第一金属层(4)、绝缘膜层(6)、有机物层(7)以及第二金属层(8)。第一金属层(4)、绝缘膜层(6)、有机物层(7)以及第二金属层(8)在半导体基板(2)的表面(2A)上依次层叠。第一金属层(4)和第二金属层(8)通过形成于绝缘膜层(6)和有机物层(7)的过孔(6A、7A)而电连接。在第二金属层(8)的、与过孔(6A、7A)对应的位置处形成有电极垫(8A)。在半导体基板(2)的表面(2A)和第一金属层(4)之间的界面处形成有贴片部(10),该贴片部(10)位于过孔(6A、7A)的正下方且形成为截面呈梯形的形状。
Description
技术领域
本发明涉及一种在半导体基板上形成有有机物绝缘层的半导体装置。
背景技术
一般地,已知一种在半导体基板的表面形成有绝缘层的半导体装置(例如,参考专利文献1)。专利文献1所记载的半导体装置包括半导体基板和形成于半导体基板的表面的层间绝缘膜。此时,层间绝缘膜被下层配线和上层配线夹着,并且通过形成于层间绝缘膜的通孔而使下层配线和上层配线电连接。
现有技术文献
专利文献
专利文献1:日本专利特开平7-153756号公报
发明内容
发明所要解决的技术问题
但是,在堵塞通孔的位置处形成有由上层配线构成的电极垫的情况下,有时由于通孔会在电极垫的一部分产生凹陷。在对这样的电极垫进行引线接合时,有时会由于凹陷而产生连接不良,存在在引线和电极垫之间产生机械性连接强度的降低以及电阻的增加这些问题。
另一方面,专利文献1中公开了在通孔的正下方配置高度差缓冲用虚拟图案的结构。但是,虚拟图案是用于实现由无机材料构成的、膜厚较薄的层间绝缘膜的平坦化的。因此,例如没有考虑由有机材料构成的、膜厚较厚的层间绝缘膜,在堵塞深度尺寸较大的通孔来形成电极垫时,该电极垫未必能够被平坦化。
此外,专利文献1中所记载的虚拟图案形成为截面呈四边形的形状。在这种情况下,在覆盖虚拟图案来形成金属层或绝缘层时,四边形截面的拐角部分有难以形成金属层等的倾向,因而存在可靠性容易降低的问题。
本发明是鉴于上述现有技术问题而形成的,本发明的目的是提供一种能够减少引线的连接不良并且能够提高可靠性的半导体装置。
解决技术问题所采用的技术方案
为了解决上述技术问题,本发明的第一方面是:一种半导体装置,该半导体装置在半导体基板的表面层叠有第一金属层、无机物绝缘层、有机物绝缘层以及第二金属层,其中,上述有机物绝缘层形成有由通孔或有底孔构成的凹部,从上述半导体基板的表面到上述有机物绝缘层的凹部为止的厚度方向的任意部位处形成有使上述凹部的底面隆起的贴片部,上述贴片部形成为底面的面积比上表面的面积大的、截面呈梯形的形状。
本发明的第二方面是:上述贴片部的梯形截面的底边和斜边所成的倾斜角度被设定为20°以上并且70°以下。
本发明的第三方面是:上述凹部由通孔形成,上述贴片部具有面积比上述通孔的开口面积大的底面。
本发明的第四方面是:上述第二金属层具有电极垫,在与上述有机物绝缘层的凹部对应的位置处使上述电极垫的表面侧露出。
发明效果
根据本发明的第一方面,由于在从半导体基板的表面到有机物绝缘层的凹部为止的厚度方向的任意部位处形成有贴片部,因此能够通过贴片部使凹部的底面隆起。藉此,在堵塞凹部来形成第二金属层时,能够使第二金属层的表面的凹陷缓和。因此,在对第二金属层进行引线接合时,能够减少引线的连接不良。此外,由于贴片部形成为截面呈梯形的形状,因此即使在覆盖贴片部来形成金属层和绝缘层时,也能够无间断且连续地形成金属层等,并且能够抑制金属层等的缺陷,能够提高可靠性。
根据本发明的第二方面,截面呈梯形的贴片部的底边和斜边所成的倾斜角度被设定为20°以上并且70°以下。因此,由于贴片部的截面拐角部分的角度较大,因而即使在覆盖贴片部来形成金属层和绝缘层时,也能够抑制金属层和绝缘层的缺陷。
根据本发明的第三方面,由于贴片部具有面积比通孔的开口面积大的底面,因此能够使通孔的底面整体隆起。因此,能够在与通孔对应的部位整体处,使第二金属层的表面的凹陷缓和。
根据本发明的第四方面,第二金属层具有电极垫,在与有机物绝缘层的凹部对应的位置处使上述电极垫的表面侧露出。因此,能够使电极垫的表面平坦化,在对电极垫进行引线接合时,能够减少引线的连接不良。
附图说明
图1是表示第一实施方式的半导体装置的剖视图。
图2是表示第一实施方式的半导体装置的主要部分放大剖视图。
图3是表示第二实施方式的半导体装置的主要部分放大剖视图。
符号说明
1、21 半导体装置;
2 半导体基板;
2A 表面;
2B 半导体层;
3 半导体元件;
4、22、24 第一金属层;
6、23、25 绝缘膜层(无机物绝缘层);
7、26 有机物层(有机物绝缘层);
8、27 第二金属层(外部连接用);
10、29、31、32 贴片部;
10A、29A 底面;
10B、29B 上表面。
具体实施方式
以下,参照附图,对本发明的实施方式的半导体装置进行详细说明。本发明的半导体装置应用于对例如MHz频带或GHz频带这样的高频信号进行放大的功率放大器。
图1和图2中示出了第一实施方式的半导体装置1。半导体装置1包括半导体基板2、第一金属层4、绝缘膜层6、有机物层7、第二金属层8以及贴片部10。第一金属层4、绝缘膜层6、有机物层7以及第二金属层8在半导体基板2的表面2A上依次层叠。
半导体基板2采用例如砷化镓(GaAs)这样的半导体材料并呈平板状形成。并且,半导体基板2也可以通过例如磷化铟(InP)、氮化镓(GaN)等这样其它的Ⅲ-Ⅴ族的化合物半导体来形成。半导体基板2可以采用例如硒化锌(ZnSe)这样Ⅱ-Ⅵ族的化合物半导体来形成,也可以采用例如碳化硅(SiC)、硅锗(SiGe)这样Ⅳ族的化合物半导体来形成。此外,半导体基板2不限定于化合物半导体,也可以通过硅(Si)、锗(Ge)这样的Ⅳ族单个元素的半导体来形成。
半导体基板2的表面2A形成有例如由砷化镓(GaAs)、砷化铝镓(AlGaAs)等构成的半导体层2B。半导体层2B可以掺杂有杂质,也可以去除杂质。此外,半导体层2B可以是一层,也可以是多层(例如两层)。
半导体元件3配置在半导体基板2的表面2A侧。半导体元件3形成为包括例如半导体层2B。半导体元件3可以是二极管、场效应晶体管等这样的主动元件,也可以是电阻、电容器等这样的被动元件。半导体元件3通常在半导体基板2处设置有多个(仅图示一个)。上述多个半导体元件3通过例如第一金属层4和第二金属层8中的至少任意一个而彼此电连接。
第一金属层4配置在比有机物层7靠近半导体基板2的位置处。具体而言,第一金属层4形成于半导体2的表面2A上方。第一金属层4采用例如金(Au)等这样的导电性金属材料来形成。第一金属层4具有例如形成半导体元件3的电极、将多个半导体元件3间电连接等这样的各种功能。藉此,半导体基板2形成有包括半导体元件3的各种电路5(例如放大电路等)。因此,半导体基板2是形成电路5的电路基板。
绝缘膜层6覆盖半导体元件3并且形成在半导体基板2的表面2A上方。绝缘膜层6构成无机物绝缘层。因此,绝缘膜层6采用例如氮化硅膜等这样的具有绝缘性的无机材料来形成。在绝缘膜层6,在例如与第一金属层4对应的位置处形成有由通孔(贯穿孔)构成的过孔6A。绝缘膜层6构成层间绝缘层而使半导体基板2的表面2A和第二金属层8之间电绝缘。
并且,绝缘膜层6不限定于氮化硅膜(例如Si3N4,SiN等),也可以采用氧化硅膜(例如SiO2,SiO等)、氮氧化硅膜(例如SiON等)中的任意一个来形成。
有机物层7覆盖绝缘膜层6并且形成在半导体基板2上。有机物层7和绝缘膜层6一同构成层间绝缘层。有机物层7构成有机物绝缘层。因此,有机物层7采用例如聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并噁唑(PBO)等这样的具有绝缘性的有机材料来形成。有机物层7通过将各种树脂材料以旋涂的方式涂布在绝缘膜层6的表面而形成。此时,相比绝缘膜层6的膜厚,有机物层7的膜厚有变大的倾向。有机物层7例如用于使半导体装置1的表面侧整体平坦化,并且使第一金属层4和第二金属层8之间的层间电容降低。
在有机物层7,在与第一金属层4对应的位置处形成有由通孔(贯穿孔)构成的过孔7A。因此,过孔7A构成有机物层7的凹部。此时,过孔7A配置在与过孔6A对应的位置处。因此,在省略第二金属层8的状态下,在过孔7A内露出有第一金属层4的表面。并且,过孔6A、7A不需要具有相同大小(开口面积),也可以彼此是不同的大小。因此,有机物层7的过孔7A例如可以比绝缘膜层6的过孔6A大。
第二金属层8配置在比有机物层7远离半导体基板2的位置处。上述第二金属层8构成与半导体基板2不接触的其它的金属层,并且形成于有机物层7的表面上方。第二金属层8采用例如导电性金属材料来形成。第二金属层8具有通过第一金属层4将半导体元件3和外部之间电连接等这样的各种功能。因此,第二金属层8通过过孔6A、7A与第一金属层4电连接。此外,第二金属层8形成有位于与过孔6A、7A对应的部位的电极垫8A。为了使电极垫8A通过引线接合等与外部连接,因此使上述电极垫8A的表面露出。
钝化膜9覆盖第二金属层8并且设置在半导体基板2处。钝化膜9不仅覆盖第二金属层8,还覆盖有机物层7、半导体层2B等。钝化膜9采用例如氮化硅膜、氧化硅膜、氮氧化硅膜等这样的具有绝缘性的无机材料来形成。此外,钝化膜9形成有位于与电极垫8A对应的部位并且使电极垫8A露出的开口部9A。
贴片部10形成于从半导体基板2的表面2A到有机物层7的过孔7A为止的厚度方向的任意部位处。具体而言,贴片部10设置在半导体基板2和第一金属层4之间的界面处。此时,贴片部10在被半导体基板2和第一金属层4夹着的状态下与半导体基板2和第一金属层4接触。因此,贴片部10例如采用与半导体基板2和第一金属层4中的任意一方相同的材料来形成。具体而言,贴片部10采用导电性的金属材料或与半导体基板2相同的半导体材料来形成。
贴片部10的平面形状是与例如过孔7A的开口部相同的形状(例如圆形、椭圆形、多边形等)。此外,贴片部10形成为底面10A的面积比上表面10B的面积大的、截面呈梯形的形状。此时,贴片部10的底边和斜边所成的倾斜角度θ被设定为20°以下且70°以下,较为理想的是,上述倾斜角度θ被设定为30°以上且60°以下。贴片部10具有面积比过孔7A的开口面积大的底面10A。贴片部10使作为过孔7A的底面的第一金属层4在过孔7A的位置处隆起。
并且,贴片部10的底面10A的面积可以比过孔7A的开口部的面积小。若考虑贴片部10和过孔7A的位置偏差公差等,较为理想的是,贴片部10的底面10A的面积被设定为是例如过孔7A的开口部的面积的一倍以上且小于三倍。
此外,贴片部10可以被设定为与过孔7A的开口部具有相同程度的形状及大小。在这种情况下,贴片部10的底面10A的面积可以形成为比过孔7A的开口面积大,贴片部10的上表面10B的面积可以形成为比过孔7A的开口面积小。
如此,根据第一实施方式,在从半导体基板2的表面2A到有机物层7的过孔7A为止的厚度方向的任意部位处形成有贴片部10。具体而言,贴片部10设置在半导体基板2和第一金属层4之间的界面处。因此,能够通过贴片部10使作为过孔7A的底面的第一金属层4的表面隆起。藉此,在堵塞过孔7A而形成第二金属层8时,能够使第二金属层8的表面的凹陷缓和。
此时,第二金属层8具有电极垫8A,该电极垫8A在与有机物层7的过孔7A对应的位置处使其表面侧露出。因此,能够使电极垫8A的表面平坦化,在对电极垫8A进行引线接合时,能够减少引线的连接不良。
此处,在使贴片部10形成为截面呈矩形的形状(长方形状)的情况下,截面拐角部分a的角度为90°左右。在这种情况下,若形成第一金属层4来覆盖贴片部10,则在截面拐角部分a的周围有难以形成第一金属层4的倾向,因而使台阶覆盖性变差,有时第一金属层4会产生缺陷。
与此相对,本实施方式的贴片部10形成为截面呈梯形的形状。此时,截面呈梯形的形状的贴片部10被设定为底边和斜边所成的倾斜角度θ是20°以上并且70°以下。因此,贴片部10的截面拐角部分a是角度比90°大的钝角。藉此,即使在覆盖贴片部10来形成第一金属层4时,也能够无间断且连续地形成第一金属层4。其结果是,能够抑制第一金属层4的缺陷,能够提高可靠性。
此外,由于贴片部10具有面积比过孔7A的开口面积大的底面,因此能够使过孔7A的底面整体隆起。因此,能够在与过孔7A对应的部位整体处,使第二金属层8的表面的凹陷缓和。
接着,在图3中示出了本发明的第二实施方式的半导体装置21。半导体装置21的特征在于,包括多层第一金属层和绝缘膜层。并且,在对半导体装置21进行说明时,对与第一实施方式的半导体装置1相同的结构标注相同的符号并省略其说明。
半导体装置21包括半导体基板2、第一金属层22、24、绝缘膜层23、25、有机物层26、第二金属层27。半导体基板2的表面2A上形成有半导体层2B。
第一金属层22构成靠近半导体基板2的金属层,并且形成于半导体基板2的表面2A上方。第一金属层22构成为与第一实施方式的第一金属层4基本相同,采用例如导电性金属材料来形成。第一金属层22具有例如形成半导体元件3的电极、将多个半导体元件3间电连接等这样的各种功能。藉此,半导体基板2上形成有包括半导体元件3的各种电路5。
绝缘膜层23覆盖半导体元件3并且形成于半导体基板2的表面2A上方。绝缘膜层23构成无机物绝缘层。因此,绝缘膜层23构成为与第一实施方式的绝缘膜层6基本相同,采用例如氮化硅膜等这样具有绝缘性的无机材料来形成。绝缘膜层23构成层间绝缘层而使第一金属层22和其它的第一金属层24之间电绝缘。
其它的第一金属层24形成于绝缘膜层23的表面上方。第一金属层24采用例如导电性金属材料来形成。第一金属层24具有例如将第一金属层22和第二金属层27之间电连接、跨越第一金属层22而将多个半导体元件3之间电连接等这样的各种功能。
其它的绝缘膜层25覆盖半导体元件3并且形成于半导体基板2的表面2A上方。绝缘膜层25和绝缘膜层23同样地构成无机物绝缘层。因此,绝缘膜层25构成为与第一实施方式的绝缘膜层6基本相同,采用例如氮化硅膜等这样具有绝缘性的无机材料来形成。在绝缘膜层25,在例如与第一金属层24对应的位置处形成有由贯穿孔构成的过孔25A。绝缘膜层25构成层间绝缘层而使第一金属层24和第二金属层27之间电绝缘。
有机物层26覆盖绝缘膜层25并且形成于半导体基板2。有机物层26和绝缘膜层23、25一同构成层间绝缘层。有机物层26构成有机物绝缘层。因此,有机物层26与第一实施方式的有机物层7同样采用具有绝缘性的有机材料来形成。此时,相比绝缘膜层23、25的膜厚,有机物层26的膜厚有变大的倾向。有机物层26例如用于使半导体装置21的表面侧整体平坦化,并且使第一金属层22、24和第二金属层27之间的层间电容降低。在有机物层26,在与第一金属层24对应的位置处形成有由贯穿孔构成的过孔26A。此时,过孔26A配置在与过孔25A对应的位置处。因此,在省略第二金属层27的状态下,在过孔26A内露出有第一金属层24的表面。并且,过孔25A、26A不需要具有相同大小(开口面积),也可以彼此是不同的大小。因此,有机物层26的过孔26A例如可以比绝缘膜层25的过孔25A大。
第二金属层27构成与半导体基板2不接触的其它的金属层,上述第二金属层27位于有机物层26的表面上方,并且形成于半导体基板2处。第二金属层27采用例如导电性金属材料来形成。第二金属层27具有通过第一金属层22、24等将半导体元件3和外部之间电连接等这样的各种功能。第二金属层27通过过孔25A、26A与第一金属层24电连接。此外,第二金属层27形成有位于与过孔25A、26A对应的部位的电极垫27A。为了使电极垫27A通过引线接合等与外部连接,因此使上述电极垫27A的表面露出。
钝化膜28覆盖第二金属层27并且设置在半导体基板2处。钝化膜28不仅覆盖第二金属层27,还覆盖有机物层26、半导体层2B等。钝化膜28采用例如氮化硅膜、氧化硅膜、氮氧化硅膜等这样的具有绝缘性的无机材料来形成。此外,钝化膜28形成有位于与电极垫7A对应的部位并且使电极垫27A露出的开口部28A。
贴片部29形成为与第一实施方式的贴片部10基本相同。因此,贴片部29形成于从半导体基板2的表面2A到有机物层26的过孔26A为止的厚度方向的任意部位处。具体而言,贴片部29设置在半导体基板23和第一金属层24之间的界面处。此时,贴片部29在被绝缘膜层23和第一金属层24夹着的状态下与绝缘膜层23和第一金属层24接触。因此,贴片部29例如采用与半导体基板23和第一金属层24中的任意一方相同的材料来形成。具体而言,贴片部29采用导电性的金属材料或绝缘材料来形成。
贴片部29形成为底面29A的面积比上表面29B的面积大的、截面呈梯形的形状。此外,贴片部29被设定为底边和斜边所成的倾斜角度是例如20°以上并且70°以下。贴片部29具有面积比过孔26A的开口面积大的底面29A。贴片部29使作为过孔26A的底面的第一金属层24在过孔26A的位置处隆起。
如此,第二实施方式具有与第一实施方式基本相同的作用效果。
并且,在第二实施方式中,贴片部29设置在绝缘膜层23和第一金属层24之间的界面处。本发明不限于上述情况,只要贴片部29形成于从半导体基板2的表面2A到有机物层26的过孔26A为止的厚度方向的任意部位处即可。因此,如图3中双点划线所示,也可在半导体基板2和第一金属层22之间的界面处设置贴片部31,也可在第一金属层22和绝缘膜层23之间的界面处设置贴片部32。
在上述各实施方式中,相对于从半导体基板2的表面2A到有机物层7、26的过孔7A、26A为止的厚度方向设置单个贴片部10、29。本发明不限于上述情况,可以相对于厚度方向设置多个贴片部。即,在图3中,可以选择三个贴片部29、31、32中的任意两个进行设置,也可以设置全部三个。并且,在设置多个贴片部的情况下,上述贴片部的厚度尺寸和外形尺寸(底面的面积等)可以设定为彼此相同的值,也可以设定为彼此不同的值。
在上述各实施方式中,通过沿厚度方向贯穿地设置在有机物层7、26中的过孔7A、26A来形成凹部。本发明不限于上述情况,也可通过例如沿厚度方向非贯穿地设置在有机物层中的有底孔来形成凹部。
此外,在上述各种实施方式中,以半导体装置1、21应用于功率放大器的情况为例进行了说明。本发明不限于上述情况,半导体装置也可应用于太阳能电池这样的受光元件,也可应用于激光二极管(LD)、发光二极管(LED)这样的发光元件,也可以应用于具有受光元件和发光元件两者的光学传感器。
Claims (2)
1.一种半导体装置,该半导体装置在半导体基板的表面层叠有第一金属层、无机物绝缘层、有机物绝缘层以及第二金属层,其特征在于,
所述有机物绝缘层形成有由通孔构成的凹部,
从所述半导体基板的表面到所述有机物绝缘层的凹部为止的厚度方向的任意部位处形成有使所述凹部的底面隆起的贴片部,
所述第一金属层形成为覆盖所述贴片部,
所述无机物绝缘层形成为覆盖所述第一金属层,
在所述无机物绝缘层的与所述第一金属层对应的位置形成有通孔,
所述有机物绝缘层形成为:在所述凹部配置在与所述无机物绝缘层的通孔对应的位置的状态下,覆盖所述无机物绝缘层,
所述第二金属层通过所述凹部的底面与所述第一金属层接触,从而形成在所述有机物绝缘层的表面之上,所述第二金属层具有电极垫,在与所述凹部对应的位置处使所述电极垫的表面侧露出,
所述半导体装置包括钝化膜,所述钝化膜覆盖所述第二金属层而形成在所述有机物绝缘层的表面之上,且在与所述电极垫对应的部位形成有使所述电极垫露出的开口部,
所述贴片部形成为底面的面积比上表面的面积大且截面呈梯形的形状,
所述贴片部的上表面的面积形成为比所述有机物绝缘层的所述通孔的开口面积小,
所述贴片部的梯形截面的底边和斜边所成的倾斜角度被设定为20°以上并且70°以下。
2.如权利要求1所述的半导体装置,其特征在于,
所述贴片部具有面积比所述有机物绝缘层的所述通孔的开口面积大的底面。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101383303A (zh) * | 2007-07-23 | 2009-03-11 | 株式会社瑞萨科技 | 半导体装置及其制造方法 |
JP6204277B2 (ja) * | 2014-06-23 | 2017-09-27 | 京セラドキュメントソリューションズ株式会社 | 画像形成システム、及びボックス機能を用いた印刷出力方法 |
JP6342144B2 (ja) * | 2013-12-03 | 2018-06-13 | クラリオン株式会社 | 車両用放送受信装置、及び車両用放送受信装置の制御方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6342144A (ja) * | 1986-08-08 | 1988-02-23 | Hitachi Ltd | 多層配線構造体 |
JPS6352444A (ja) * | 1986-08-22 | 1988-03-05 | Toshiba Corp | 半導体集積回路装置とその製造方法 |
JPH04127452A (ja) * | 1989-06-30 | 1992-04-28 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
KR100335591B1 (ko) * | 1992-09-10 | 2002-08-24 | 텍사스 인스트루먼츠 인코포레이티드 | 집적회로디바이스의액티브회로영역상의와이어본딩방법및집적회로디바이스 |
JPH07153756A (ja) | 1993-11-29 | 1995-06-16 | Hitachi Ltd | 半導体集積回路装置 |
JPH08139094A (ja) * | 1994-11-14 | 1996-05-31 | Citizen Watch Co Ltd | 半導体装置の製造方法 |
JP2985692B2 (ja) * | 1994-11-16 | 1999-12-06 | 日本電気株式会社 | 半導体装置の配線構造及びその製造方法 |
JPH08255833A (ja) * | 1995-03-15 | 1996-10-01 | Sony Corp | 半導体装置の製造方法 |
JP3641111B2 (ja) * | 1997-08-28 | 2005-04-20 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4001115B2 (ja) * | 2003-02-28 | 2007-10-31 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
JP4599834B2 (ja) * | 2003-12-12 | 2010-12-15 | ソニー株式会社 | 半導体装置およびその製造方法 |
US7915737B2 (en) * | 2006-12-15 | 2011-03-29 | Sanyo Electric Co., Ltd. | Packing board for electronic device, packing board manufacturing method, semiconductor module, semiconductor module manufacturing method, and mobile device |
JP2014022502A (ja) * | 2012-07-17 | 2014-02-03 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2015002234A (ja) * | 2013-06-14 | 2015-01-05 | サンケン電気株式会社 | 半導体装置及びその製造方法 |
US9991200B2 (en) * | 2014-09-25 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Air gap structure and method |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101383303A (zh) * | 2007-07-23 | 2009-03-11 | 株式会社瑞萨科技 | 半导体装置及其制造方法 |
JP6342144B2 (ja) * | 2013-12-03 | 2018-06-13 | クラリオン株式会社 | 車両用放送受信装置、及び車両用放送受信装置の制御方法 |
JP6204277B2 (ja) * | 2014-06-23 | 2017-09-27 | 京セラドキュメントソリューションズ株式会社 | 画像形成システム、及びボックス機能を用いた印刷出力方法 |
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