CN107833913A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN107833913A
CN107833913A CN201710383196.0A CN201710383196A CN107833913A CN 107833913 A CN107833913 A CN 107833913A CN 201710383196 A CN201710383196 A CN 201710383196A CN 107833913 A CN107833913 A CN 107833913A
Authority
CN
China
Prior art keywords
electrode
terminal
semiconductor device
protuberance
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710383196.0A
Other languages
English (en)
Other versions
CN107833913B (zh
Inventor
桑原芳光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN107833913A publication Critical patent/CN107833913A/zh
Application granted granted Critical
Publication of CN107833913B publication Critical patent/CN107833913B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

本发明的实施方式提供一种能够抑制半导体芯片破裂时的损伤的半导体装置。实施方式的半导体装置具有半导体芯片、壳体、第1电极、第2电极及金属板。所述半导体芯片具有第1端子及设置在所述第1端子的相反侧的第2端子。所述壳体包围所述半导体芯片的外周。所述第1电极设置在所述第1端子侧，且与所述第1端子电连接。所述第2电极设置在所述第2端子侧，且与所述第2端子电连接。所述金属板设置在所述第1端子与所述第1电极之间。所述金属板在外周具有朝向侧方突出的突出部。所述突出部与所述第1电极隔开。

Description

半导体装置
[相关申请]
本申请享有以日本专利申请2016-180689号(申请日：2016年9月15日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
在工业用反相器或风扇、泵驱动装置等被通入大电流的系统中，使用压接型半导体装置。在该半导体装置中，当设置在内部的半导体芯片产生不良状况时，有半导体芯片破裂的情况。此时，有可能会因飞散的半导体芯片的碎片，而导致收纳有半导体芯片的半导体装置破损，且碎片飞散至外部而使其它装置受损。
发明内容
本发明提供一种能够抑制破损的半导体装置。
实施方式的半导体装置具有半导体芯片、壳体、第1电极、第2电极及金属板。所述半导体芯片具有第1端子及设置在所述第1端子的相反侧的第2端子。所述壳体包围所述半导体芯片的外周。所述第1电极设置在所述第1端子侧，且与所述第1端子电连接。所述第2电极设置在所述第2端子侧，且与所述第2端子电连接。所述金属板设置在所述第1端子与所述第1电极之间。所述金属板在外周具有朝向侧方突出的突出部。所述突出部与所述第1电极隔开。
附图说明
图1(a)及(b)是实施方式的半导体装置的剖视图。
图2是表示实施方式的半导体装置的一部分的剖视图。
图3是实施方式的半导体装置所具有的金属板的俯视图。
图4是实施方式的变化例的半导体装置的剖视图。
具体实施方式
以下，一边参照附图一边对本发明的各实施方式进行说明。
另外，附图为示意性或概念性图，各部分的厚度与宽度的关系、部分间的大小的比率等未必限定为与实物相同。而且，即便在表示相同部分的情况下，也有彼此的尺寸或比率根据附图而不同地表示的情况。
而且，在本案说明书及各图中，对与已说明过的要素相同的要素标注相同的符号，并适当省略详细的说明。
在各实施方式的说明中使用XYZ正交坐标系。将从下部电极20朝向上部电极24的方向设为Z方向(第1方向)，将与Z方向垂直并且相互正交的两个方向设为X方向及Y方向。
图1是实施方式的半导体装置100的剖视图。
图1(a)中示出整个半导体装置100，图1(b)中示出半导体装置100所具有的半导体芯片10。
半导体装置100例如为具有多个半导体芯片的压接型Press-Pack IEGT(Injection Enhanced IGBT，注入式增强型IGBT)。
如图1(a)所示，半导体装置100具有半导体芯片10、外壳12(壳体)、树脂架14、热补偿板16及18、下部电极20(第2电极)、金属板22以及上部电极24(第1电极)。
如图1(b)所示，半导体芯片10具有上部端子10a(第1端子)、设置在上部端子10a的相反侧的下部端子10b(第2端子)及设置在上部端子10a与下部端子10b之间的半导体部10c。
半导体芯片10例如为使用硅的IEGT。IEGT为具备电子注入促进效果的IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)。在半导体芯片10为IEGT的情况下，上部端子10a作为发射电极发挥功能，下部端子10b作为集电极发挥功能。而且，在此情况下，半导体芯片10还具备未图示的栅极电极。
另外，半导体芯片10只要为上下具备电极的器件，那么也可以为IEGT以外的器件。半导体芯片10例如也可以为FRD(Fast Recovery Diode，快恢复二极管)等二极管或MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)。或者，也可以是，半导体装置100所具有的多个半导体芯片10的一部分为IEGT，另外一部分为二极管。而且，半导体芯片10也可以是除硅以外使用碳化硅等的器件。
外壳12为环状，包围半导体芯片10的外周。外壳12由氧化铝等绝缘性陶瓷形成。在外壳12的外周设置有多个环状突起部12a。通过设置突起部12a，而能够提高上部电极24与下部电极20之间的绝缘性(沿面距离)。
树脂架14设置在外壳12的内侧，支撑多个半导体芯片10。
热补偿板16设置在半导体芯片10的上部端子10a侧。热补偿板18设置在半导体芯片10的下部端子10b侧。热补偿板16及18使用热膨胀系数与半导体芯片10接近的材料。当半导体芯片10使用硅时，热补偿板16及18可使用钼。
下部电极20具有电极块20a及缘边(fringe)20b。缘边20b设置在电极块20a的外周。缘边20b的厚度比电极块20a的厚度薄。也就是说，设置有缘边20b的下部电极20的外周部分的厚度(Z方向上的尺寸)比设置有电极块20a的下部电极20的中心部分的厚度薄。电极块20a的上表面具有多个突起，热补偿板16及半导体芯片10设置在各突起之上。下部电极20经由热补偿板16与多个半导体芯片10的下部端子10b电连接。
金属板22设置在热补偿板18之上。在金属板22的外周设置有朝向侧方突出的突出部22a。而且，金属板22的下表面具有多个突起，各突起位于半导体芯片10之上，且连接于热补偿板18。
上部电极24设置在金属板22之上，具有电极块24a及缘边24b。缘边24b设置在电极块24a的外周。缘边24b的厚度比电极块24a的厚度薄。也就是说，设置有缘边24b的上部电极24的外周部分的厚度比设置有电极块24a的上部电极24的中心部分的厚度薄。上部电极24经由热补偿板18及金属板22而与多个半导体芯片10的上部端子10a电连接。
电极块20a及24a、金属板22例如由铜形成。
缘边20b及24b例如由铁镍合金形成。
电极块20a与缘边20b以及电极块24a与缘边24b是通过焊接等而连接。
缘边20b及24b分别通过钎焊而连接于外壳12的上下。
多个半导体芯片10被外壳12、下部电极20及上部电极24包围。它们的内部空间内被填充惰性气体，多个半导体芯片10被气密地密封。
缘边20b及24b为板状，具有适当强度的弹簧特性。如果从半导体装置的上下方向对上部电极24及下部电极20施加按压力，那么半导体芯片10、热补偿板16、热补偿板18、下部电极20、金属板22及上部电极24相互密接，而获得良好的电接触。
接下来，一边参照图2及图3，一边对金属板22具体地进行说明。
图2是表示实施方式的半导体装置100的一部分的剖视图。
图3是实施方式的半导体装置100所具有的金属板22的俯视图。
如上所述，金属板22在其外周具有朝向侧方突出的突出部22a。如图2所示，该突出部22a在Z方向上与上部电极24隔开。而且，突出部22a与外壳12的内壁面隔开而设置。
突出部22a与缘边24b的至少一部分在Z方向上对向，并且从下方覆盖电极块24a的外周及缘边24b。也就是说，突出部22a从下方覆盖上部电极24的厚度较薄的外周部分的至少一部分。
在突出部22a的下部电极20侧的面(下表面)上形成有凹部R1。如图3所示，凹部R1沿着金属板22的外周形成为环状。
此处，对本实施方式的效果进行说明。
在半导体装置100中，如果多个半导体芯片10的一部分产生不良状况，且对产生有不良状况的半导体芯片10通入大电流，那么半导体芯片10的温度上升而引起热失控。而且，如果因热失控而导致半导体芯片10的温度进一步上升，那么半导体芯片10开始熔化。此时，有半导体芯片10破裂并且半导体装置100的内压大幅度上升的情况。如果半导体芯片10破裂，且因其碎片而导致外壳12或下部电极20、上部电极24破损，并且碎片飞散至半导体装置100之外，那么有可能使半导体装置100以外的装置受损。因此，理想的是，即便在半导体芯片10已破裂的情况下，也不会使半导体装置100破损，碎片不会飞散至半导体装置100之外。
因半导体芯片10破裂而导致半导体装置100破损尤其容易在下部电极20或上部电极24的外周产生。原因在于，下部电极20及上部电极24的中央部分(电极块20a及24a)形成为较厚，外壳12也能够通过使厚度增加而提高强度，相对于此，下部电极20及上部电极24的外周的缘边20b及24b必须具备适度的弹簧特性。
本实施方式的半导体装置100中，在半导体芯片10与上部电极24之间的金属板22上设置突出部22a，该突出部22a与上部电极24隔开。在这种构造中，当半导体芯片10的碎片朝向上部电极24的外周飞散时，碎片首先碰撞到突出部22a。突出部22a与上部电极24在Z方向上隔开，因此能够抑制碎片碰撞到突出部22a时的冲击传递给上部电极24。而且，即便在因碎片碰撞而导致突出部22a折断的情况下，也能够在通过突出部22a朝向上方弯曲，利用突出部22a及金属板22使碎片的动能缓和之后，使碎片碰撞到上部电极24。因此，根据本实施方式，即便在半导体芯片10已破裂的情况下，也能够降低上部电极24产生破损的可能性。
而且，通过在突出部22a形成凹部R1，而提高突出部22a的弹簧特性，在碎片碰撞到突出部22a时，更容易缓和碎片的动能。因此，在半导体芯片10已破裂的情况下，能够进一步降低上部电极24产生破损的可能性。
另外，凹部R1也可以形成在突出部22a的上表面，但理想的是形成在下表面。原因在于，通过将凹部R1形成在突出部22a的下表面，能够提高从下方受力时的弹簧特性。
而且，并不限定于图3所示的例子，凹部R1也可以在突出部22a形成多个。
(变化例)
图4是实施方式的变化例的半导体装置110的剖视图。
半导体装置110与半导体装置100的不同点是在多个半导体芯片10与下部电极20之间设置有金属板26。
金属板26的上表面具有多个突起，热补偿板16及半导体芯片10设置在各突起之上。下部电极20经由热补偿板16及金属板26而与多个半导体芯片10的下部端子10b电连接。
金属板26与金属板22同样地，在外周具有朝向侧方突出的突出部26a(第2突出部)。突出部26a与下部电极20在Z方向上隔开。而且，突出部26a与下部电极20的缘边20b在Z方向上对向，并且从上方覆盖电极块20a的外周及缘边20b。也就是说，突出部26a从上方覆盖下部电极20的厚度较薄的外周部分的至少一部分。
与突出部22a同样地，在突出部26a的上部电极24侧的面(上表面)上形成凹部R2，该凹部R2沿着金属板26的外周设置成环状。
这样一来，通过在半导体芯片10与下部电极20之间的金属板26上设置突出部26a，而与设置有突出部22a时同样地，即便在半导体芯片10已破裂的情况下，也能够降低下部电极20产生破损的可能性。
而且，凹部R2理想为形成在上表面。原因在于，通过将凹部R2形成在突出部26a的上表面，而能够提高从上方受力时的弹簧特性。
以上，对本发明的若干实施方式进行了说明，但这些实施方式是作为示例而提出，并不意图限定发明的范围。这些新颖的实施方式能够以其它各种方式加以实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。关于实施方式中所包含的例如半导体芯片10、外壳12、下部电极20、金属板22、上部电极24、金属板26等各要素的具体构成，本领域技术人员能够从公知的技术中适当选择。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。而且，所述各实施方式能够相互组合而实施。

Claims (5)

1.一种半导体装置，其特征在于具备：
半导体芯片，具有第1端子及设置在所述第1端子的相反侧的第2端子；
壳体，包围所述半导体芯片的外周；
第1电极，设置在所述第1端子侧，且与所述第1端子电连接；
第2电极，设置在所述第2端子侧，且与所述第2端子电连接；以及
金属板，设置在所述第1端子与所述第1电极之间，且在外周具有朝向侧方突出的突出部，所述突出部与所述第1电极隔开。
2.根据权利要求1所述的半导体装置，其特征在于：
在所述突出部的所述第2电极侧的面上形成有凹部。
3.根据权利要求2所述的半导体装置，其特征在于：
所述凹部沿着所述金属板的外周形成为环状。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于：
具备多个所述半导体芯片，
所述第1电极与所述多个所述第1端子电连接，
所述第2电极与所述多个所述第2端子电连接。
5.根据权利要求1至3中任一项所述的半导体装置，其特征在于：
所述第1电极的外周部分的厚度比所述第1电极的中心部分的厚度薄，
所述突出部在从所述第2电极朝向所述第1电极的第1方向上，与所述第1电极的所述外周部分的至少一部分对向。
CN201710383196.0A 2016-09-15 2017-05-26 半导体装置 Active CN107833913B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-180689 2016-09-15
JP2016180689A JP6585569B2 (ja) 2016-09-15 2016-09-15 半導体装置

Publications (2)

Publication Number Publication Date
CN107833913A true CN107833913A (zh) 2018-03-23
CN107833913B CN107833913B (zh) 2021-11-19

Family

ID=60255658

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710383196.0A Active CN107833913B (zh) 2016-09-15 2017-05-26 半导体装置

Country Status (3)

Country Link
US (1) US9818705B1 (zh)
JP (1) JP6585569B2 (zh)
CN (1) CN107833913B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7395452B2 (ja) 2020-09-23 2023-12-11 株式会社東芝 半導体装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112652612B (zh) * 2019-10-12 2022-07-05 深圳第三代半导体研究院 一种堆叠型压接式功率模块及其制造方法
CN112466856B (zh) * 2020-11-17 2023-04-14 深圳宝铭微电子有限公司 一种igbt器件及其制备方法
CN112597678B (zh) * 2020-12-15 2023-03-24 重庆大学 一种压接型igbt器件微动磨损失效演化的数值模拟方法
CN115836391A (zh) * 2021-05-28 2023-03-21 丹尼克斯半导体有限公司 半导体装置
EP4162524A1 (en) * 2021-08-27 2023-04-12 Dynex Semiconductor Limited Semiconductor device with failure-protection structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5121189A (en) * 1989-11-06 1992-06-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US5371386A (en) * 1992-04-28 1994-12-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of assembling the same
CN105914152A (zh) * 2015-02-24 2016-08-31 株式会社东芝 半导体装置及半导体模块

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850425B2 (ja) * 1977-11-07 1983-11-10 三菱電機株式会社 半導体装置
JPH081914B2 (ja) * 1987-03-31 1996-01-10 株式会社東芝 圧接型半導体装置
JP2918389B2 (ja) * 1992-04-28 1999-07-12 三菱電機株式会社 半導体装置およびその組立方法
US5598036A (en) 1995-06-15 1997-01-28 Industrial Technology Research Institute Ball grid array having reduced mechanical stress
JP5040234B2 (ja) 2006-09-26 2012-10-03 三菱電機株式会社 圧接型半導体装置
JP5899952B2 (ja) 2012-01-19 2016-04-06 株式会社明電舎 半導体モジュール
JP2015056487A (ja) * 2013-09-11 2015-03-23 株式会社東芝 半導体装置
JP2016082105A (ja) 2014-10-17 2016-05-16 株式会社東芝 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5121189A (en) * 1989-11-06 1992-06-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US5371386A (en) * 1992-04-28 1994-12-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of assembling the same
CN105914152A (zh) * 2015-02-24 2016-08-31 株式会社东芝 半导体装置及半导体模块

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7395452B2 (ja) 2020-09-23 2023-12-11 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
JP2018046190A (ja) 2018-03-22
US9818705B1 (en) 2017-11-14
CN107833913B (zh) 2021-11-19
JP6585569B2 (ja) 2019-10-02

Similar Documents

Publication Publication Date Title
CN107833913A (zh) 半导体装置
JP6326280B2 (ja) パワーエレクトロニクス開閉装置及びパワーエレクトロニクス開閉装置を有する装置
CN105914152A (zh) 半导体装置及半导体模块
US10658284B2 (en) Shaped lead terminals for packaging a semiconductor device for electric power
CN103824844A (zh) 功率半导体模块及其制造方法
JP5414644B2 (ja) 半導体装置
CN107093587B (zh) 半导体装置及其制造方法
US20170338176A1 (en) Semiconductor module and method of manufacturing semiconductor module
CN110021565B (zh) 具有芯片载体的至少部分暴露的内侧壁的包封式无引线封装
US20160111554A1 (en) Semiconductor device
US20180068918A1 (en) Power module
CN104992934B (zh) 功率半导体器件子模组
US9024430B2 (en) Semiconductor device
CN106981460B (zh) 半导体装置
WO2020241472A1 (ja) 半導体装置、および半導体装置の製造方法
CN103794594A (zh) 半导体封装件
JP6101507B2 (ja) 半導体装置の製造方法
US7969278B2 (en) Thermistor
CN104795370A (zh) 半导体装置
US3027502A (en) Semiconductor device
JP2018046099A (ja) 半導体装置
CN107204292B (zh) 半导体装置及半导体装置的制造方法
JPH1084009A (ja) 半導体装置
US20220336300A1 (en) Power Semiconductor Device
JP2019046839A (ja) パワー半導体モジュール

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant