JP6585569B2 - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 103
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- 239000012634 fragment Substances 0.000 description 8
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- Computer Hardware Design (AREA)
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Description
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
また、本願明細書と各図において、既に説明したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
各実施形態の説明には、XYZ直交座標系を用いる。下部電極20から上部電極24に向かう方向をZ方向(第1方向)とし、Z方向に対して垂直であり、相互に直交する2方向をX方向およびY方向とする。
図1(a)では、半導体装置100の全体が表され、図1(b)では、半導体装置100が有する半導体チップ10が表されている。
図1(a)に表すように、半導体装置100は、半導体チップ10、ハウジング12(枠体)、樹脂フレーム14、熱補償板16および18、下部電極20(第2電極)、金属板22、および上部電極24(第1電極)を有する。
熱補償板16は、半導体チップ10の上部端子10a側に設けられている。熱補償板18は、半導体チップ10の下部端子10b側に設けられている。熱補償板16および18には、半導体チップ10と熱膨張係数の近い材料が用いられる。半導体チップ10にシリコンが用いられる場合、熱補償板16および18には、モリブデンを用いることができる。
フリンジ20bおよび24bは、例えば、鉄ニッケル合金で形成されている。
電極ブロック20aとフリンジ20b、および電極ブロック24aとフリンジ24bは、溶接などで接続されている。
フリンジ20bおよび24bは、それぞれ、ハウジング12の上下にろう付けによって接続されている。
図2は、実施形態に係る半導体装置100の一部を表す断面図である。
図3は、実施形態に係る半導体装置100が有する金属板22の平面図である。
半導体装置100において、複数の半導体チップ10の一部に不具合が生じ、不具合が生じた半導体チップ10に大きな電流が流れると、半導体チップ10の温度が上昇し、熱暴走が起こる。そして、熱暴走によって半導体チップ10の温度がさらに上昇していくと、半導体チップ10が溶け始める。このとき、半導体チップ10が破裂するとともに、半導体装置100の内圧が大きく上昇する場合がある。半導体チップ10が破裂し、その破片によってハウジング12や下部電極20、上部電極24が破損し、半導体装置100の外にまで破片が飛散すると、半導体装置100以外の装置を損傷させる可能性がある。このため、半導体チップ10が破裂した場合でも、半導体装置100が破損せず、半導体装置100の外に破片が飛散しないことが望ましい。
また、図3に表す例に限らず、凹部R1は、突出部22aに複数形成されていてもよい。
図4は、実施形態の変形例に係る半導体装置110の断面図である。
半導体装置110は、複数の半導体チップ10と下部電極20との間に、金属板26が設けられている点で、半導体装置100と異なる。
Claims (6)
- 第1端子と、前記第1端子の反対側に設けられた第2端子と、を有する半導体チップと、
前記半導体チップの前記第1端子側に設けられたブロック部と、前記ブロック部よりも薄いフランジ部と、を含み、前記第1端子と電気的に接続される第1電極と、
前記半導体チップの前記第2端子側に設けられ、前記第2端子と電気的に接続される第2電極と、
前記半導体チップと前記第1電極の前記ブロック部との間に配置された金属板と、
前記半導体チップおよび前記金属板を囲む枠体と、
を備え、
前記第1電極の前記フランジ部は、前記枠体と前記金属板との間の隙間を跨ぐように前記枠体に係合され、
前記金属板は、その外周に沿って、前記枠体と前記金属板との間の前記隙間中に突出した突出部であって、前記枠体および前記フランジ部から離間した突出部を有し、
前記突出部は、前記金属板の外周において、前記半導体チップよりも前記第1電極に近い位置から突出した半導体装置。 - 前記突出部の前記第2電極側の面に、凹部が形成されている請求項1記載の半導体装置。
- 前記凹部は、前記金属板の外周に沿って環状に形成されている請求項2記載の半導体装置。
- 複数の前記半導体チップを備え、
前記第1電極は、前記複数の前記第1端子と電気的に接続され、
前記第2電極は、前記複数の前記第2端子と電気的に接続された請求項1〜3のいずれか1つに記載の半導体装置。 - 前記第1電極の前記ブロック部は、前記金属板に接する中心部分と、前記中心部分の厚さよりも薄い外縁と、を有し、前記フランジ部は、前記外縁に係合され、
前記突出部は、前記ブロック部の前記外縁よりも外側に突出し、前記第2電極から前記第1電極に向かう方向において、前記フランジ部と対向している請求項1〜4のいずれか1つに記載の半導体装置。 - 前記半導体チップを支持する絶縁性のフレームをさらに備え、
前記第2電極は、前記フレームの開口を介して、前記第2端子に電気的に接続され、
前記枠体は、前記フレームを囲むように配置され、
前記フレームの外周は、前記金属板の前記外周よりも前記枠体に近接し、
前記金属板の前記突出部は、前記第1電極のフランジ部と、前記枠体と、前記フレームと、前記金属板と、に囲まれた前記隙間に突出した請求項1〜5のいずれか1つに記載の半導体装置。
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JP2016180689A JP6585569B2 (ja) | 2016-09-15 | 2016-09-15 | 半導体装置 |
US15/447,121 US9818705B1 (en) | 2016-09-15 | 2017-03-02 | Semiconductor device |
CN201710383196.0A CN107833913B (zh) | 2016-09-15 | 2017-05-26 | 半导体装置 |
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CN112652612B (zh) * | 2019-10-12 | 2022-07-05 | 深圳第三代半导体研究院 | 一种堆叠型压接式功率模块及其制造方法 |
JP7395452B2 (ja) | 2020-09-23 | 2023-12-11 | 株式会社東芝 | 半導体装置 |
CN112466856B (zh) * | 2020-11-17 | 2023-04-14 | 深圳宝铭微电子有限公司 | 一种igbt器件及其制备方法 |
CN112597678B (zh) * | 2020-12-15 | 2023-03-24 | 重庆大学 | 一种压接型igbt器件微动磨损失效演化的数值模拟方法 |
EP4128334A1 (en) * | 2021-05-28 | 2023-02-08 | Dynex Semiconductor Limited | Semiconductor device |
EP4162524A1 (en) * | 2021-08-27 | 2023-04-12 | Dynex Semiconductor Limited | Semiconductor device with failure-protection structure |
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JPS5850425B2 (ja) * | 1977-11-07 | 1983-11-10 | 三菱電機株式会社 | 半導体装置 |
JPH081914B2 (ja) * | 1987-03-31 | 1996-01-10 | 株式会社東芝 | 圧接型半導体装置 |
JPH0760893B2 (ja) * | 1989-11-06 | 1995-06-28 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US5371386A (en) * | 1992-04-28 | 1994-12-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of assembling the same |
JP2918389B2 (ja) * | 1992-04-28 | 1999-07-12 | 三菱電機株式会社 | 半導体装置およびその組立方法 |
US5598036A (en) | 1995-06-15 | 1997-01-28 | Industrial Technology Research Institute | Ball grid array having reduced mechanical stress |
JP5040234B2 (ja) | 2006-09-26 | 2012-10-03 | 三菱電機株式会社 | 圧接型半導体装置 |
JP5899952B2 (ja) | 2012-01-19 | 2016-04-06 | 株式会社明電舎 | 半導体モジュール |
JP2015056487A (ja) * | 2013-09-11 | 2015-03-23 | 株式会社東芝 | 半導体装置 |
JP2016082105A (ja) | 2014-10-17 | 2016-05-16 | 株式会社東芝 | 半導体装置 |
JP6301857B2 (ja) * | 2015-02-24 | 2018-03-28 | 株式会社東芝 | 半導体モジュール |
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CN107833913B (zh) | 2021-11-19 |
CN107833913A (zh) | 2018-03-23 |
US9818705B1 (en) | 2017-11-14 |
JP2018046190A (ja) | 2018-03-22 |
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