CN107818947A - 一种半导体器件及其制造方法 - Google Patents
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- 238000002955 isolation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
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- 241000416536 Euproctis pseudoconspersa Species 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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Abstract
本发明公开了一种半导体器件及其制造方法,在衬底上形成多晶硅,并在多晶硅的侧面形成侧墙;在衬底上淀积氧化物阻挡层;通过N+和P+的两次光刻,分别刻蚀相应位置的氧化物阻挡层并注入形成N+和P+区域;在N+和P+区域上方生长形成金属硅化物层。本发明减少了光刻次数,节约了成本。
Description
技术领域
本发明涉及一种半导体器件技术领域,特别涉及一种半导体器件及其制造方法。
背景技术
为了减小MOS(Metal-Oxide-Silicon,金属-氧化物-半导体)器件源/漏区的接触电阻,会引入金属硅化物(Silicide)工艺,即在源漏区之间的衬底上设置金属硅化物层;为了减小多晶硅(Poly)的接触电阻,会引入多晶硅化物(Polycide)工艺;在自对准的CMOS(Complementary Metal-Oxide-Silicon,互补型金属-氧化物-半导体)工艺中,将Silicide过程和Polycide过程同时完成而引入Salicide(Self-Aligned Silicide,自对准金属硅化物)工艺。
然而,在基于自对准的CMOS工艺中,由于在制作多晶硅Poly高阻时,需要额外用金属硅化物阻挡层(Salicide Block)光刻板来选择性生长金属硅化物,以增加了工序和成本。具体如图1-6所示,示意了现有技术的半导体器件的制造方法的步骤。现有技术中在多晶硅栅(Poly)和侧墙(Spacer)形成后,需要三次光刻和两次注入形成N+注入,P+注入和金属硅化物Salicide,具体步骤如图1,2,3,4,5,6所示,分别通过N+,P+两次光刻注入形成N+和P+区域,再通过淀积氧化物阻挡层并光刻形成生长Salicide的区域,然后去胶,利用标准的淀积、退火、刻蚀、退火工艺形成Salicide。
发明内容
有鉴于此,本发明的目的是提供一种减少光刻次数的半导体器件及其制造方法,用于解决现有技术存在的增加工序和成本的技术问题。
为实现上述目的,本发明提供了一种半导体器件的制造方法,包括以下步骤:
在衬底上形成多晶硅,并在多晶硅的侧面形成侧墙;
在衬底上淀积氧化物阻挡层;
通过N+和P+的两次光刻,分别刻蚀相应位置的氧化物阻挡层并注入形成N+和P+区域;
在N+和P+区域上方生长形成金属硅化物层。
可选的,在形成N+和P+区域后,先去掉胶层,衬底表面淀积金属层,并经第一温度退火,再刻蚀掉不需要的金属层,然后经第二温度退火,上述过程中,所述金属层与衬底表面的硅反应,从而在N+和P+区域上方形成金属硅化物层。
可选的,所述的第一温度为450~600摄氏度,所述的第二温度为750~900摄氏度。
可选的,在衬底中使用浅沟槽隔离结构、场氧或小场氧进行隔离。
本发明还提供一种半导体器件,由以下方法制成:
在衬底上形成多晶硅,并在多晶硅的侧面形成侧墙;
在衬底上淀积氧化物阻挡层;
通过N+和P+的两次光刻,分别刻蚀相应位置的氧化物阻挡层并注入形成N+和P+区域;
在N+和P+区域上方生长形成金属硅化物层。
可选的,在形成N+和P+区域后,先去掉胶层,衬底表面淀积金属层,并经第一温度退火,再刻蚀掉不需要的金属层,然后经第二温度退火,上述过程中,所述金属层与衬底表面的硅反应,从而在N+和P+区域上方形成金属硅化物层。
与现有技术相比,本发明之技术方案具有以下优点:本发明在N+和P+两次光刻前,在衬底上淀积氧化物阻挡层,再分别通过N+,P+的两次光刻,分别刻蚀氧化物阻挡层并注入形成N+和P+区域,此时有N+,P+的区域也形成了可以生长金属硅化物层的区域,然后去胶,再利用淀积、退火、刻蚀、退火工艺形成金属硅化物层,从而减少了光刻次数,节约了成本。
附图说明
图1为现有技术形成多晶硅和侧墙的结构示意图;
图2为现有技术N+光刻注入形成N+区域的结构示意图;
图3为现有技术P+光刻注入形成P+区域的结构示意图;
图4为现有技术淀积氧化物阻挡层的结构示意图;
图5为现有技术刻蚀形成用于生长金属硅化物层的结构示意图;
图6为现有技术在N+和P+区域形成金属硅化物层结构示意图;
图7为本发明N+光刻注入形成N+区域的结构示意图;
图8为本发明P+光刻注入形成P+区域的结构示意图;
图9为本发明在N+和P+区域形成金属硅化物层结构示意图。
具体实施方式
以下结合附图对本发明的优选实施例进行详细描述,但本发明并不仅仅限于这些实施例。本发明涵盖任何在本发明的精神和范围上做的替代、修改、等效方法以及方案。
为了使公众对本发明有彻底的了解,在以下本发明优选实施例中详细说明了具体的细节,而对本领域技术人员来说没有这些细节的描述也可以完全理解本发明。
在下列段落中参照附图以举例方式更具体地描述本发明。需说明的是,附图均采用较为简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明之半导体器件的制造方法使用了与现有技术不同的工序,调整了氧化物阻挡层的淀积顺序,从而省去了一次光刻。在本发明工艺下,对于NMOS或PMOS而言,由于N+或P+注入的区域均有金属硅化物层,对其NMOS或PMOS的特性没有影响。对于高阻而言,在P+注入的区域有金属硅化物层,方便两端电极的引出,以降低接触电阻,而没有P+注入的区域没有金属硅化物层,从而使整个多晶硅Poly有高阻特性。为了示意清楚,本发明的附图以NMOS、PMOS和Poly高阻作为半导体器件为例,以浅沟槽隔离结构(STI)进行隔离,但实际工艺的实现不限于上述器件,只要基于本发明之构思所实现的,均可认为是由本发明方法制造出的半导体器件。NMOS和PMOS中所形成的多晶硅Poly通过电极引出后形成栅极。以下将通过图7、8和9详细说明本发明之实施步骤。
首先,浅沟槽隔离结构(STI)将衬底隔离成多个器件区域,以P型衬底为例,在衬底P-sub内形成P型阱,用以在P型阱区域制作NMOS;在衬底P-sub内形成N型阱,用以在N型阱区域制作PMOS;并在衬底表面设置高压电阻。然后,通过在衬底P-sub表面上形成多晶硅Poly,并在多晶硅Poly的侧面形成侧墙Spacer,并进而在衬底上淀积氧化物阻挡层Oxide。
如图7所示,示意了N+光刻注入形成N+区域的状态结构,其中在无需注入的位置设置胶层Photoresist进行遮挡。本步骤中,实现了N+注入,形成N+注入的区域,N+光刻注入时需要刻掉N+注入区域的氧化物阻挡层Oxide。与现有技术不同的是,氧化物阻挡层Oxide形成于光刻之前。
如图8所示,示意了P+光刻注入形成N+区域的状态结构,其中在无需注入的位置设置胶层Photoresist进行遮挡。本步骤中,实现了P+注入,形成P+注入的区域,P+光刻注入时需要刻掉P+注入区域的氧化物阻挡层Oxide。与现有技术不同的是,氧化物阻挡层Oxide形成于光刻之前。此外N+注入和P+注入并没有严格的顺序,既然先后顺序可以互换,不构成对本申请技术方案的限制。所述氧化物阻挡层可以使用SRO,TEOS,SION等各种氧化物材料。
如图9所示,示意了N+和P+区域形成金属硅化物层的状态结构。通过图7和8的N+和P+的两次光刻,分别刻蚀相应位置的氧化物阻挡层并注入形成N+注入和P+注入区域。在N+注入和P+注入区域上方生长形成金属硅化物层Salicide。具体地,在形成N+和P+区域后,先去掉胶层,衬底表面淀积金属层,并经第一温度退火,再刻蚀掉不需要的金属层,然后经第二温度退火,上述过程中,所述金属层与衬底表面的硅反应,从而在N+和P+区域上方形成金属硅化物层。这里的金属层可以采用钴,第一温度退火主要作用是使有硅裸露的区域,硅和钴反应生成第一种金属硅化物,而被氧化物覆盖的区域,并不会发生反应。从而在第二温度退火前,可以通过选择性刻蚀,将未发生反应的钴去除掉,但保留了发生反应后的第一种金属硅化物。第二温度退火主要实现钴与衬底上硅进一步反应,形成第二种金属硅化物层。所述的第一温度为450~600摄氏度,如采用500摄氏度,所述的第二温度为750~900摄氏度,如采用800摄氏度。
基于同一发明构思,可形成另一实施例,即改变了侧墙的形成步骤,在两次光刻注入的同时形成侧墙,具体如下:
在衬底上形成多晶硅;
在衬底上淀积氧化物阻挡层;
通过N+和P+的两次光刻,分别刻蚀相应位置的氧化物阻挡层并在多晶硅的侧面形成侧墙,然后再分别注入形成N+和P+区域;
在N+和P+区域上方生长形成金属硅化物层。
除了采用浅沟槽隔离结构(STI)隔离外,还可以采用场氧(locos)或小场氧(mini-locos)进行隔离。
虽然以上将实施例分开说明和阐述,但涉及部分共通之技术,在本领域普通技术人员看来,可以在实施例之间进行替换和整合,涉及其中一个实施例未明确记载的内容,则可参考有记载的另一个实施例。
以上所述的实施方式,并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等,均应包含在该技术方案的保护范围之内。
Claims (6)
1.一种半导体器件的制造方法,包括以下步骤:
在衬底上形成多晶硅,并在多晶硅的侧面形成侧墙;
在衬底上淀积氧化物阻挡层;
通过N+和P+的两次光刻,分别刻蚀相应位置的氧化物阻挡层并注入形成N+和P+区域;
在N+和P+区域上方生长形成金属硅化物层。
2.根据权利要求1所述的半导体器件的制造方法,其特征在于:在形成N+和P+区域后,先去掉胶层,衬底表面淀积金属层,并经第一温度退火,再刻蚀掉不需要的金属层,然后经第二温度退火,上述过程中,所述金属层与衬底表面的硅反应,从而在N+和P+区域上方形成金属硅化物层。
3.根据权利要求2所述的半导体器件的制造方法,其特征在于:所述的第一温度为450~600摄氏度,所述的第二温度为750~900摄氏度。
4.一种半导体器件的制造方法,其特征在于:
在衬底上形成多晶硅;
在衬底上淀积氧化物阻挡层;
通过N+和P+的两次光刻,分别刻蚀相应位置的氧化物阻挡层并在多晶硅的侧面形成侧墙,然后再分别注入形成N+和P+区域;
在N+和P+区域上方生长形成金属硅化物层。
5.一种半导体器件,其特征在于:由以下方法制成:
在衬底上形成多晶硅,并在多晶硅的侧面形成侧墙;
在衬底上淀积氧化物阻挡层;
通过N+和P+的两次光刻,分别刻蚀相应位置的氧化物阻挡层并注入形成N+和P+区域;
在N+和P+区域上方生长形成金属硅化物层。
6.根据权利要求5所述的半导体器件,其特征在于:在形成N+和P+区域后,先去掉胶层,衬底表面淀积金属层,并经第一温度退火,再刻蚀掉不需要的金属层,然后经第二温度退火,上述过程中,所述金属层与衬底表面的硅反应,从而在N+和P+区域上方形成金属硅化物层。
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