CN1905138B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1905138B CN1905138B CN2006101075829A CN200610107582A CN1905138B CN 1905138 B CN1905138 B CN 1905138B CN 2006101075829 A CN2006101075829 A CN 2006101075829A CN 200610107582 A CN200610107582 A CN 200610107582A CN 1905138 B CN1905138 B CN 1905138B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- gate electrode
- silicon
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 36
- 239000010703 silicon Substances 0.000 claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 84
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 41
- 229910052759 nickel Inorganic materials 0.000 claims description 17
- 239000010936 titanium Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 239000011135 tin Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 238000003780 insertion Methods 0.000 claims 1
- 230000037431 insertion Effects 0.000 claims 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 18
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 18
- 239000012535 impurity Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- -1 silicon ion Chemical class 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910005881 NiSi 2 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910001453 nickel ion Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
一种用于制造半导体器件的方法，包括：在衬底上形成栅电极，具有在其间插入的栅绝缘层；在栅电极的两侧形成绝缘层侧壁；在分别位于栅电极两侧的衬底的表面部分中形成源区/漏区；在包括栅电极的衬底的整个表面上形成硅层；在包括硅层的衬底的整个表面上形成导电层；通过热处理该衬底，以便导电层与硅层起反应，在衬底的整个表面上形成硅化物层；以及有选择地除去不对应于栅电极和衬底的源区/漏区的硅化物层。
Description
技术领域
本发明涉及一种半导体器件，具体涉及一种通过补偿硅的损耗形成具有稳定的阻抗性能的金属硅化物层的半导体器件及其制造方法。
背景技术
通常，随着半导体器件几何尺寸变得越来越小，栅极、源区和漏区的尺寸被减小，要求源区和漏区之间的结点更浅。但是，由于这些原因，不希望地产生高阻区。
由此，为了减小源区和漏区以及多晶硅区之间的电阻，在那些区之间的接触上使用高熔点金属硅化物。
在处理过程中只要在源区和漏区以及露出的硅之间发生接触，高熔点金属的薄膜被淀积，并被加热形成硅化物。在该工序中，使用包括铂、锰、钴、钛等的各种硅化物化合物。
现在将参考附图描述相关技术的半导体器件的制造方法。
图1A至1F是说明相关技术的半导体器件的制造方法的剖面图。
如图1A所示，半导体衬底21包括有源区和器件隔离区，以及通过硅的局部氧化(LOCOS)或浅沟槽隔离(STI)工艺，在器件隔离区中形成器件隔离层22。
然后，在高温下热氧化该半导体衬底，以在半导体衬底21上形成栅氧化层23。
如图1B所示，在半导体衬底21的有源区中有选择地注入用于形成晶体管的沟道的n-型或p-型杂质离子，以形成n-阱或p-阱(未示出)，以及在约1050～1200℃的高温下，在其上执行热处理。
然后，在栅氧化层23上淀积多晶硅层，并通过光刻工艺有选择地刻蚀该多晶硅层和栅氧化层23，以形成栅电极24。
使用栅电极24作为掩模，将n-型杂质离子或p-型杂质离子注入半导体衬底21的整个表面，以在分别位于栅电极24的两侧半导体衬底21的表面部分中形成轻掺杂漏(LDD)区25。
如图1C所示，通过低压化学气相淀积(LPCVP)方法，在半导体衬底21的整个表面上淀积绝缘层，然后在其整个表面上执行深刻蚀工艺，以在栅电极24的两侧形成绝缘层侧壁26。
然后，使用栅电极24和绝缘层侧壁26作为掩模，将n-型或p-型高浓度杂质离子注入到半导体衬底21的整个表面，以在分别位于栅电极24两侧的半导体衬底21的表面部分中形成源-漏杂质区27，然后在约1000～1050℃的温度下在其上执行热处理。
如图1D所示，执行清洗工序，以从半导体衬底21除去各种目标材料如金属杂质、有机污染物、自然氧化层。
然后，经过清洗工序的半导体衬底21被传送到溅射设备的溅射室(未示出)，通过溅射在半导体衬底21的整个表面上形成镍层28。
如图1E所示，半导体衬底21被提供到快速热处理(RTP)设备或电炉中，并在400～600℃的温度下被热处理，以在包括栅电极24以及源和漏杂质区27的半导体衬底21的表面上形成镍硅化物层29。
具体地，在热处理过程中，栅电极24和半导体衬底21的硅离子与镍层28的镍离子起反应，由此形成镍硅化物层29。但是，在绝缘层侧壁26和器件隔离层22中未发生这种反应，因此在其上仍然剩下镍层28。
如图1F所示，未参与镍硅化物层29的形成的剩余镍层被除去，然后在预定温度下退火该半导体衬底21，以稳定镍硅化物层29的相位，由此完成低阻镍硅化物层29。
但是，制造半导体器件的相关技术的方法具有以下问题。
因为在这种窄的温度范围内形成镍硅化物(NiSi)，从该温度范围偏差仅仅约10℃的温度致使将产生具有高电阻的材料如Ni2Si或NiSi2。
因此，镍硅化物(NiSi)需要在低温下形成。
发明内容
由此，本发明涉及一种半导体器件及其制造方法，基本上避免由于相关技术的限制和缺点的一个或多个问题。
本发明的目的是提供一种半导体器件及其制造方法，通过扩大形成镍硅化物(NiSi)的温度范围可以提高器件的可靠性，因此形成优质的镍硅化物层。
本发明的附加优点、目的以及特点部分将在下面的描述中阐述和部分对于本领域的技术人员来说在检查以下的描述时将变得明显，或可以从本发明的实践学到。通过撰写的说明书和权利要求以及附图中特别指出的结构可以实现和获得本发明的这些及其他优点。
为了实现这些目的和其他优点以及根据本发明的目的，如在此体现和广泛地描述，提供一种半导体器件的制造方法，包括：在衬底上形成栅电极，具有在其间插入的栅绝缘层；在栅电极的两侧形成绝缘层侧壁；在分别位于栅电极两侧的衬底表面部分中形成源区/漏区；在包括栅电极的衬底的整个表面上形成硅层；在包括硅层的衬底的整个表面上形成导电层；通过热处理该衬底，以便导电层与硅层起反应，在衬底的整个表面上形成硅化物层；以及有选择地除去不对应于栅电极和衬底的源区/漏区的硅化物层。
在本发明的另一方面中，这样提供一种半导体器件，包括：被限定为有源区和器件隔离区的衬底；在衬底的有源区上形成的栅电极；通过在位于栅电极两侧的有源区上执行杂质离子注入工序而形成的源区和漏区；以及包括在源区和漏区以及栅电极上形成的硅单层和导电层的硅化物层。
应当理解本发明的上述概述及随后的详细描述是示例性的和说明性的，目的是用来提供所要求的发明的进一步说明。
附图说明
所包括的附图提供本发明的进一步理解并被引入和构成本申请的一部分，说明本发明的实施例以及与该描述一起用来解释本发明的原理。在图中：
图1A至1F是说明相关技术的半导体器件的制造方法的剖面图；
图2A至2F是说明根据本发明的半导体器件的制造方法的剖面图。
具体实施方式
现在详细介绍本发明的优选实施例，在附图中图示了其例子。
图2A至2F是说明根据本发明的半导体器件的制造方法的剖面图。
如图2A所示，半导体衬底201包括有源区和器件隔离区，以及通过硅的局部氧化(LOCOS)或浅沟槽隔离(STI)工艺，在器件隔离区中形成器件隔离层202。
然后，在高温下热氧化该半导体衬底201，以在半导体衬底201上形成栅氧化层203。
如图2B所示，在半导体衬底201的有源区中有选择地注入用于形成晶体管沟道的n-型或p-型杂质离子，以形成n-阱或p-阱(未示出)，在约1050～1200℃的高温下在其上执行热处理。
然后，在栅氧化层203上淀积多晶硅层，以及通过光刻工艺有选择地刻蚀该多晶硅层和栅氧化层203，以形成栅电极204。
使用栅电极204作为掩模，将n-型杂质离子或p-型杂质离子注入半导体衬底201的整个表面，以在分别位于栅电极204的两侧半导体衬底201的表面部分中形成轻掺杂漏(LDD)区25。
如图2C所示，通过低压化学气相淀积(LPCVP)方法在半导体衬底201的整个表面上淀积绝缘层，然后在其整个表面上执行深刻蚀工艺，以在栅电极204的两侧形成绝缘层侧壁206。
然后，使用栅电极204和绝缘层侧壁206作为掩模，将n-型或p-型高浓度杂质离子注入到半导体衬底201的整个表面，以在分别位于栅电极204两侧的半导体衬底201的表面部分中形成源-漏杂质区207，然后在约1000～1050℃的温度下在其上执行热处理。
如图2D所示，执行清洗工序，以从半导体衬底201除去各种目标材料如金属杂质、有机污染物、自然氧化层。
该清洗工序是使用SC1溶液(标准清洗：通过以1:4:20的比率混合NH4OH、H2O2、H2O获得的有机材料)，HF或DHF(稀释的HF)溶液的化学清洗工序。
然后，完全经过清洗工序的半导体衬底201被加热到约250～400℃，例如，约350℃。在加热的半导体衬底201上注入SiH4气体，由此形成硅(Si)层208，硅(Si)层是单层。
形成硅单层的气体不局限于SiH4，而是可以使用包括未过度地稳定的Si的任意类型的气体(因为过度地稳定的Si不与Ni(镍))起反应。
如图2E所示，通过物理汽相淀积(PVD)或化学气相淀积(CVD)在硅层208上形成镍层209。
在镍层209上可以形成帽盖层Ti、TiN或Ti/TiN。
镍层209具有50～300
的厚度。用于在镍层209上形成帽盖层的Ti或TiN被淀积到100～400
的厚度，在100～300℃的淀积温度下。
尽管在本发明中描述了镍层209，但是可以使用选自由钴、钛、钨、钽、钼等等构成的组的一种材料。
如图2F所示，在300～500℃的温度下，在半导体衬底201上执行热处理10秒至2分钟，由此在包括栅电极204和源/漏杂质区207的半导体衬底201上形成镍硅化物(NiSi)层210。
在相关技术中，通过热处理，金属层的金属离子与栅电极和半导体衬底的硅离子起反应，以形成镍硅化物层。但是，在本发明中，在栅电极204和半导体衬底201上形成的硅层208的硅离子与镍层209的金属离子起反应，以形成镍硅化物层210。
亦即，在相关技术中，因为温度余量的不足，在400℃±10℃的温度范围周围制成Ni2Si或NiSi2。这里，400℃是形成NiSi时的基准温度。
在相关技术中，Ni和栅电极24和源/漏区的Si互相起反应，以在栅电极24的表面和源/漏区的表面中形成镍硅化物。但是，在本发明中，在栅电极204的表面上和在源/漏区的表面上形成独立的镍硅化物层，以及部分镍硅化物是形成在栅电极204的表面和源/漏区的表面中。
因此，重要的是在低温范围中制成NiSi，不是Ni2Si。为此，以1:1的比率结合Ni和Si。
根据本发明，使用SiH4在半导体衬底201上形成硅层208，即使在低温下，也可以获得NiSi。因此，在其中制成NiSi的温度范围可以被大大地增加。
然后，通过湿法刻蚀，有选择地除去不对应于栅电极和半导体衬底的源/漏区的镍硅化物层(209)。
如至此描述，根据本发明的半导体器件的制造方法具有以下效果。
在本发明中，使用SiH4在半导体层上形成硅层，SiH4与镍层起反应，以便即使在低温下也可以获得优质的镍硅化物。因此，形成镍硅化物的温度范围可以被大大地增加。
所属领域的技术人员应当明白在本发明中可以进行各种改进和改变。因此，希望本发明覆盖在附加权利要求及它们的等效范围内提供的本发明的改进和改变。
Claims (21)
1.一种用于制造半导体器件的方法，该方法包括：
在衬底上形成栅电极，具有在这两者间插入的栅绝缘层；
在栅电极的两侧形成绝缘层侧壁；
在分别位于栅电极两侧的衬底表面部分中形成源区/漏区；
在包括栅电极的衬底的整个表面上形成硅层；
在包括硅层的衬底的整个表面上形成导电层；
通过热处理该衬底，以便导电层与硅层起反应，在衬底的整个表面上形成硅化物层；以及
有选择地除去不对应于栅电极和衬底的源区/漏区的硅化物层。
2.根据权利要求1的方法，其中通过将包括Si(硅)的气体注入到衬底形成硅层。
3.根据权利要求2的方法，其中用来形成硅层的气体是SiH4。
4.根据权利要求1的方法，还包括，在形成硅层之前，将衬底加热到250～400℃的温度。
5.根据权利要求4的方法，其中在350°的淀积温度下形成硅层。
6.根据权利要求1的方法，其中导电层具有50～300
的厚度。
7.根据权利要求1的方法，还包括，在形成硅层之前，将半导体层加热到350℃。
8.根据权利要求1的方法，其中在300～500℃的温度下执行热处理。
9.根据权利要求8的方法，其中热处理被执行10秒～2分钟。
10.根据权利要求1的方法，其中在100～300℃的温度下形成导电层。
11.根据权利要求1的方法，还包括，在导电层上形成由Ti、TiN和Ti/TiN的一种形成的帽盖层。
12.根据权利要求1的方法，其中在导电层上由Ti、TiN和Ti/TiN的一种形成的帽盖层具有100～400的厚度。
13.根据权利要求1的方法，其中导电层由选自由镍、钴、钛、钨、钽和钼构成的组的一种材料形成。
14.根据权利要求13的方法，其中形成以1∶1的比率结合镍(Ni)和硅(Si)的硅化物层。
15.一种半导体器件，包括：
被限定为有源区和器件隔离区的衬底；
形成在衬底的有源区上的栅电极；
通过在位于栅电极两侧的有源区上执行杂质离子注入工序形成的源区和漏区；以及
包括硅单层和导电层的硅化物层，在源区、漏区、和栅电极上形成所述硅单层和导电层，所述导电层形成在所述硅单层上。
16.根据权利要求15的半导体器件，其中使用SiH4气体形成硅单层。
17.根据权利要求15的半导体器件，其中导电层具有50～300
的厚度。
18.根据权利要求15的半导体器件，其中硅化物层还包括在导电层上由Ti、TiN和Ti/Tin的一种形成的帽盖层。
19.根据权利要求18的半导体器件，其中在导电层上由Ti、TiN和Ti/TiN的一种形成的帽盖层具有100～400的厚度。
20.根据权利要求15的半导体器件，其中导电层由选自由镍、钴、钛、钨、钽和钼构成的组的一种材料形成。
21.根据权利要求20的半导体器件，其中形成以1∶1的比率结合镍(Ni)和硅(Si)的硅化物层。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050068323 | 2005-07-27 | ||
| KR1020050068323A KR100685898B1 (ko) | 2005-07-27 | 2005-07-27 | 반도체 소자의 제조방법 |
| KR10-2005-0068323 | 2005-07-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1905138A CN1905138A (zh) | 2007-01-31 |
| CN1905138B true CN1905138B (zh) | 2010-08-11 |
Family
ID=37674356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101075829A Expired - Fee Related CN1905138B (zh) | 2005-07-27 | 2006-07-27 | 半导体器件及其制造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7767580B2 (zh) |
| KR (1) | KR100685898B1 (zh) |
| CN (1) | CN1905138B (zh) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100821082B1 (ko) * | 2006-12-15 | 2008-04-08 | 동부일렉트로닉스 주식회사 | 반도체 소자 제조 방법 |
| US20080160706A1 (en) * | 2006-12-27 | 2008-07-03 | Jin Hyo Jung | Method for fabricating semiconductor device |
| CN105097472A (zh) * | 2015-07-30 | 2015-11-25 | 上海华力微电子有限公司 | 一种降低镍侵蚀的方法 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6524952B1 (en) * | 1999-06-25 | 2003-02-25 | Applied Materials, Inc. | Method of forming a titanium silicide layer on a substrate |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6323130B1 (en) * | 2000-03-06 | 2001-11-27 | International Business Machines Corporation | Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging |
| US20020111021A1 (en) * | 2001-02-13 | 2002-08-15 | Advanced Micro Devices, Inc. | Ozone oxide as a mediating layer in nickel silicide formation |
| US6787864B2 (en) | 2002-09-30 | 2004-09-07 | Advanced Micro Devices, Inc. | Mosfets incorporating nickel germanosilicided gate and methods for their formation |
| US6787425B1 (en) * | 2003-06-16 | 2004-09-07 | Texas Instruments Incorporated | Methods for fabricating transistor gate structures |
| KR100738066B1 (ko) * | 2003-12-01 | 2007-07-12 | 삼성전자주식회사 | 열적 안정성이 우수한 실리사이드막 형성방법, 이방법으로 형성된 실리사이드막이 구비된 반도체 소자와반도체 메모리 소자 및 이들 소자의 제조 방법 |
| KR20050064663A (ko) * | 2003-12-24 | 2005-06-29 | 매그나칩 반도체 유한회사 | 반도체 소자의 실리사이드층 형성 방법 |
| KR100591157B1 (ko) * | 2004-06-07 | 2006-06-19 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조방법 |
| KR100654340B1 (ko) * | 2004-12-08 | 2006-12-08 | 삼성전자주식회사 | 카본이 포함된 금속 실리사이드 층을 갖는 반도체 소자 및그 제조 방법 |
| US7109116B1 (en) * | 2005-07-21 | 2006-09-19 | International Business Machines Corporation | Method for reducing dendrite formation in nickel silicon salicide processes |
-
2005
- 2005-07-27 KR KR1020050068323A patent/KR100685898B1/ko active IP Right Grant
-
2006
- 2006-07-27 US US11/495,387 patent/US7767580B2/en active Active
- 2006-07-27 CN CN2006101075829A patent/CN1905138B/zh not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6524952B1 (en) * | 1999-06-25 | 2003-02-25 | Applied Materials, Inc. | Method of forming a titanium silicide layer on a substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| US20070032057A1 (en) | 2007-02-08 |
| KR100685898B1 (ko) | 2007-02-26 |
| US7767580B2 (en) | 2010-08-03 |
| KR20070013743A (ko) | 2007-01-31 |
| CN1905138A (zh) | 2007-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6087234A (en) | Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction | |
| KR20070080836A (ko) | 금속 실리사이드 형성 방법 및 반도체 장치의 제조 방법 | |
| CN1905138B (zh) | 半导体器件及其制造方法 | |
| US7427561B2 (en) | Method for manufacturing semiconductor device | |
| CN102983104B (zh) | Cmos晶体管的制作方法 | |
| JPH09190983A (ja) | 半導体装置の製造方法 | |
| TW411507B (en) | Double sidewall raised silicided source/drain CMOS transistor | |
| KR100600380B1 (ko) | 반도체 소자의 제조 방법 | |
| JP2000101075A (ja) | 電界効果型トランジスタの製造方法 | |
| CN100463223C (zh) | 半导体器件及其制造方法 | |
| TWI493602B (zh) | 半導體元件及其製法 | |
| KR20030002867A (ko) | 반도체 소자의 제조 방법 | |
| KR100432789B1 (ko) | 반도체 소자의 제조 방법 | |
| KR20090067966A (ko) | 반도체 소자 및 그 제조방법 | |
| JP2001203346A (ja) | 半導体装置の製造方法 | |
| TW535237B (en) | Manufacturing method of metal oxide semiconductor transistor | |
| TW561585B (en) | Method for producing salicide with improved junction electrical properties | |
| KR100779400B1 (ko) | 반도체 소자 및 그 제조방법 | |
| KR100607782B1 (ko) | 반도체 소자의 금속 실리사이드막 제조 방법 | |
| KR100565755B1 (ko) | 반도체 소자의 제조방법 | |
| JP2008071914A (ja) | 半導体装置及びその製造方法 | |
| CN1490853A (zh) | 可改善接面电性特性的自行对准金属硅化物的制造方法 | |
| KR20040072790A (ko) | 반도체 소자의 트랜지스터 제조 방법 | |
| JP2002217193A (ja) | 半導体装置の製造方法 | |
| JP2001110748A (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100811 Termination date: 20130727 |