CN107785331A - 封装结构及其制作方法 - Google Patents

封装结构及其制作方法 Download PDF

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Publication number
CN107785331A
CN107785331A CN201610903318.XA CN201610903318A CN107785331A CN 107785331 A CN107785331 A CN 107785331A CN 201610903318 A CN201610903318 A CN 201610903318A CN 107785331 A CN107785331 A CN 107785331A
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CN
China
Prior art keywords
solder mask
encapsulating structure
patterning
opening
substrate
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Pending
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CN201610903318.XA
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English (en)
Inventor
郑有为
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Kinpo Electronics Inc
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Kinpo Electronics Inc
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Publication of CN107785331A publication Critical patent/CN107785331A/zh
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Abstract

本发明提供一种封装结构及其制作方法，其封装结构，包括衬底、图案化阻焊层、多个焊料、芯片以及高分子胶体。衬底包括多个焊垫。图案化阻焊层设置于衬底上并包括多个阶梯状开口。阶梯状开口分别暴露焊垫。焊料设置于焊垫上并位于阶梯状开口内。芯片设置于衬底上并包括有源表面以及多个接垫。接垫设置于有源表面并通过焊料而与焊垫连接。高分子胶体填充于图案化阻焊层的顶面与有源表面之间，其中高分子胶体至少环绕焊料的设置区域并填充于两相邻焊料之间。本发明提供的封装结构及其制作方法可简化工艺并可提升封装结构的电性表现。

Description

封装结构及其制作方法
技术领域
本发明涉及一种半导体结构及其制作方法，尤其涉及一种半导体封装结构及其制作方法。
背景技术
随着科技进步，各种电子装置朝向小型化及多功能化的方向发展。因此为了使电子装置中的芯片能传输或接收更多的信号，电性连接于芯片与线路板之间的接点也朝向高密度化的方向发展。于需要技术中，电性连接芯片与衬底的方法多为先在芯片的接点与衬底的导电结构之间配置异方性导电膜(Anisotropic Conductive Film,ACF)，且芯片的接点与衬底的导电结构皆面向异方性导电膜。然后，压合芯片的接点、异方性导电膜与衬底的导电结构，以藉由异方性导电膜中的导电颗粒电性连接芯片的每一接点与玻璃衬底上与前述接点对应的导电结构。
此外，在此种封装工艺中，须先对异方性导电膜进行热压，以将异方性导电膜贴附于衬底的压合区域上，接着再高温压合芯片于异方性导电膜上，使芯片上的接垫与衬底上的焊垫能够藉由异方性导电膜中的导电粒子而导通。上述两个步骤须分开进行，因而增加工艺的复杂度，且有应用领域的限制，使得工艺时间增加，进而导致产能下降。并且，异方性导电膜在经过多次按压及环境的变化后会造成异方性导电膜的阻抗不稳定，进而导致封装结构的电性表现下降。再者，异方性导电膜的价格昂贵，故使用异方性导电膜也会使封装结构的成本增加。
发明内容
本发明提供一种封装结构及其制作方法，其可简化工艺并可提升封装结构的电性表现。
本发明的封装结构的制作方法包括下列步骤。提供衬底，衬底包括多个焊垫。形成图案化阻焊层于衬底上，图案化阻焊层包括多个阶梯状开口，阶梯状开口分别暴露焊垫。设置高分子胶体于图案化阻焊层的顶面，其中热熔胶体至少环绕焊垫的设置区域并设置于两相邻焊垫之间。分别设置多个焊料于焊垫上，其中焊料分别位于阶梯状开口内。设置芯片于衬底上，其中芯片包括有源表面以及多个接垫，接垫位于有源表面，并通过焊料而与焊垫连接。对焊料进行回焊工艺，并使高分子胶体填充于图案化阻焊层的顶面与有源表面之间。
本发明的封装结构包括衬底、图案化阻焊层、多个焊料、芯片以及高分子胶体。衬底包括多个焊垫。图案化阻焊层设置于衬底上并包括多个阶梯状开口。阶梯状开口分别暴露焊垫。焊料设置于焊垫上并位于阶梯状开口内。芯片设置于衬底上并包括有源表面以及多个接垫。接垫设置于有源表面并通过焊料而与焊垫连接。高分子胶体填充于图案化阻焊层的顶面与有源表面之间，其中热熔胶体至少环绕焊料的设置区域并填充于两相邻焊料之间。
在本发明的一实施例中，上述的形成图案化阻焊层于衬底上的步骤还包括：形成第一阻焊层于衬底上，其中第一阻焊层覆盖焊垫。对第一阻焊层进行第一图案化工艺以形成包括多个第一开口的第一图案化阻焊层，第一开口分别暴露焊垫。形成第二阻焊层于第一阻焊层上。对第二阻焊层进行第二图案化工艺以形成包括多个第二开口的第二图案化阻焊层，其中第二开口分别暴露第一开口及环绕第一开口的部分第一图案化阻焊层，各第一开口及对应的第二开口共同定义出各阶梯状开口。
在本发明的一实施例中，上述的高分子胶体设置于第二图案化阻焊层上。
在本发明的一实施例中，上述的第一图案化工艺以及第二图案化工艺包括曝光显影工艺。
在本发明的一实施例中，上述的高分子胶体环绕各阶梯状开口。
在本发明的一实施例中，上述的高分子胶体的材料包括合成聚酯树脂。
在本发明的一实施例中，上述的封装结构的制作方法还包括：在分别设置焊料于焊垫上之前，对高分子胶体进行预固化工艺，以使高分子胶体呈现半固化状态。
在本发明的一实施例中，上述的预固化工艺包括对高分子胶体进行加热。
在本发明的一实施例中，上述的对高分子胶体进行加热的加热温度实质上介于摄氏50度至80度之间。
在本发明的一实施例中，上述的分别设置焊料于焊垫上的方法包括网板印刷。
在本发明的一实施例中，上述的设置高分子胶体于图案化阻焊层的顶面的方法包括网板印刷。
在本发明的一实施例中，上述的衬底包括软性电路板。
在本发明的一实施例中，上述的图案化阻焊层包括第一图案化阻焊层以及第二图案化阻焊层。第一图案化阻焊层设置于衬底上并包括多个第一开口，第一开口分别暴露焊垫。第二图案化阻焊层设置于第一图案化阻焊层上并包括多个第二开口，第二开口分别暴露第一开口及环绕第一开口的部分第一图案化阻焊层，其中各第一开口及对应的第二开口共同定义出各阶梯状开口。
在本发明的一实施例中，上述的高分子胶体填充于第二图案化阻焊层与芯片之间。
在本发明的一实施例中，上述的焊料分别填充阶梯状开口。
在本发明的一实施例中，上述的各接垫的尺寸实质上大于各焊垫的尺寸。
基于上述，本发明将高分子胶体设置于具有阶梯状开口的图案化阻焊层的顶面上，其中，阶梯状开口暴露衬底的焊垫，并且，高分子胶体环绕焊垫的设置区域并设置于两相邻焊垫之间。之后，在将芯片通过焊料而设置于衬底上，如此，由于焊料在回焊固化后会收缩，进而压缩高分子胶体，使高分子胶体可填满图案化阻焊层的顶面与芯片的有源表面之间的间隙，因而可达到密封的效果，防止外界的水气渗入封装结构内。因此，本发明可通过一次打件作业即同时完成封装结构的防水结构的制作，因而可取代现有的异方性导电膜的工艺，进而简化封装结构的工艺步骤及降低生产成本。此外，由于本发明是利用表面粘着技术(surface-mount technology SMT)而将芯片设置于衬底上，故相对于异方性导电膜来说，其阻抗较为稳定，因此，本发明也可提升封装结构的电性表现。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1K是依照本发明的一实施例的一种封装结构的制作方法的流程剖面示意图；
图2是依照本发明的一实施例的高分子胶体于图案化阻焊层上的配置的俯视示意图；
图3是依照本发明的另一实施例的高分子胶体于图案化阻焊层上的配置的俯视示意图。
附图标记：
100：封装结构；
110：衬底；
112：焊垫；
120：图案化阻焊层；
122：阶梯状开口；
122a：第一开口；
122b：第二开口；
124：第一图案化阻焊层；
124a：第一阻焊层；
125、127：图案化光阻层；
126：第二图案化阻焊层；
126a：第二阻焊层；
130：高分子胶体；
140：焊料；
150：芯片；
152：有源表面；
154：接垫。
具体实施方式
有关本发明的前述及其他技术内容、特点与功效，在以下配合参考附图的各实施例的详细说明中，将可清楚的呈现。以下实施例中所提到的方向用语，例如：“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附加附图的方向。因此，使用的方向用语是用来说明，而并非用来限制本发明。并且，在下列各实施例中，相同或相似的元件将采用相同或相似的标号。
图1A至图1K是依照本发明的一实施例的一种封装结构的制作方法的流程剖面示意图。本实施例的封装结构的制作方法可包括下列步骤。首先，提供如图1A所示的衬底110，其中，衬底110包括多个焊垫112。接着，形成如图1H所示的图案化阻焊层120于衬底110上，其中，图案化阻焊层120如图1H所示的包括多个阶梯状开口122，且阶梯状开口122分别暴露衬底110上的焊垫112。在本实施例中，衬底110可为软性电路板，当然，本发明并不以此为限。在其他实施例中，衬底110也可为印刷线路板或其他适合的衬底。
举例而言，上述的图案化阻焊层120的制作方法可包括下列步骤：首先如图1B所示的形成第一阻焊层124a于衬底110上。在本实施中，第一阻焊层124a可例如全面性覆盖衬底110上表面并覆盖焊垫112。接着，再对第一阻焊层124a进行第一图案化工艺，此第一图案化工艺可例如为曝光显影工艺。详细而言，上述的图案化工艺可如图1C所示的设置具有多个开口的图案化光阻层125于第一阻焊层124a上，上述开口暴露部分的第一阻焊层124a，接着再对暴露的第一阻焊层124a进行曝光工艺，以移除被暴露的第一阻焊层124a而形成如图1D所示的第一图案化阻焊层124，其中，第一图案化阻焊层124包括多个第一开口122a，且第一开口122a分别暴露焊垫112。须说明的是，上述的图案化工艺是以正型光阻为例，当然，在其他实施例中，图案化工艺也可采用负型光阻并对应改变图案化光阻层的图案来形成第一图案化阻焊层124，本发明并不以此为限。
接着，形成如图1E所示的第二阻焊层126a于第一图案化阻焊层124上，再对第二阻焊层126a进行第二图案化工艺，此第二图案化工艺也可为曝光显影工艺。详细而言，上述的图案化工艺可如图1F所示的设置具有多个开口的图案化光阻层127于第二阻焊层126a上，上述开口暴露部分的第二阻焊层126a，接着，再对暴露的第二阻焊层126a进行曝光工艺，以移除被暴露的第二阻焊层126a而形成如图1G所示的第二图案化阻焊层126，其中，第二图案化阻焊层126包括多个第二开口122b，且第二开口122b分别暴露第一开口122a及环绕第一开口122a的部分第一图案化阻焊层124。也就是说，如图1H所示之图案化阻焊层120可由第一图案化阻焊层124及第二图案化阻焊层126所堆叠而成，且第一图案化阻焊层124的第一开口122a及第二图案化阻焊层126的第二开口122b共同定义出图案化阻焊层120的阶梯状开口122。相似地，第二图案化工艺也可采用负型光阻并对应改变图案化光阻层的图案来形成第二图案化阻焊层126，本发明并不以此为限。
图2是依照本发明的一实施例的高分子胶体于图案化阻焊层上的配置的俯视示意图。图3是依照本发明的另一实施例的高分子胶体于图案化阻焊层上的配置的俯视示意图。请先参照图1H及图2，接着，设置高分子胶体130于图案化阻焊层120的顶面，详细而言，高分子胶体130设置于第二图案化阻焊层126的上表面。高分子胶体130通常可由许多相同的、简单的结构单元通过共价键重复连接而成的高分子量(通常可达10至106)化合物。在本实施例中，高分子胶体的材料可包括合成聚酯树脂(synthetic polyester resin)或其他适合的高分子防水绝缘材料，并且，设置高分子胶体130于图案化阻焊层120上的方法可包括网板印刷。当然，本实施例仅用以举例说明，本发明并不以此为限。在本实施例中，高分子胶体130可至少环绕多个焊垫112的设置区域，并可设置于两相邻焊垫112之间。换句话说，高分子胶体130可沿着多个焊垫112的外围设置，以环绕所述的多个焊垫112，并可至少设置于两相邻焊垫112之间。举例来说，高分子胶体130可如图2所示的环绕多个焊垫112的外围，并横跨于上下两列焊垫112之间。此外，在另一实施例中，高分子胶体130也可如图3所示的环绕各阶梯状开口122，也就是环绕于各个焊垫112的周围。
接着，在一实施例中，可例如对高分子胶体130进行预固化工艺，以使高分子胶体130呈现半固化状态。具体而言，上述的预固化工艺可例如是对高分子胶体130进行加热，其加热温度约介于摄氏50度至80度之间。当然，本实施例仅用以举例说明，本发明并不以此为限。
请接续参照图1I，分别设置多个焊料140于焊垫112上，其中焊料140分别位于阶梯状开口122内。在本实施例中，设置焊料140于焊垫112上的方法可包括网板印刷，当然，本发明并不以此为限。接着，再如图1J所示的设置芯片150于衬底110上，其中，芯片150包括有源表面152以及多个接垫154。接垫154位于有源表面152上，并通过焊料140而与焊垫112连接。换句话说，本实施例是利用表面粘着技术(surface-mount technology SMT)而将芯片150设置于衬底110上。在本实施例中，各接垫154的尺寸可如图1J所示的略大于各焊垫112的尺寸，当然，本发明并不以此为限。高分子胶体130则位于图案化阻焊层120的顶面与芯片150的有源表面152之间。
接着，对焊料140进行回焊工艺，以将芯片150固设于衬底110上，回焊后的焊料140可完全填充图案化阻焊层120的阶梯状开口122。同时，由于焊料140在回焊固化后会收缩，进而压缩高分子胶体130，使高分子胶体130可完全填充于图案化阻焊层120的顶面与有源表面之间的间隙，因而可达到密封的效果，防止外界的水气渗入封装结构100内。如此，即可大致完成如图1K所示的封装结构100。
就结构上而言，依上述制作方法所形成的封装结构100可包括衬底110、图案化阻焊层120、多个焊料140、芯片150以及高分子胶体130。衬底110包括多个焊垫112。图案化阻焊层120设置于衬底110上并包括多个阶梯状开口112。阶梯状开口122分别暴露焊垫112。详细而言，图案化阻焊层120包括如图1H所示的第一图案化阻焊层124以及第二图案化阻焊层126。第一图案化阻焊层124设置于衬底110上并包括多个第一开口122a，且第一开口122a分别暴露焊垫112。第二图案化阻焊层126则设置于第一图案化阻焊层124上并包括多个第二开口122b，且第二开口122b分别暴露第一开口122a及环绕第一开口122a的部分第一图案化阻焊层124，其中，第一开口122a及第二开口122b共同定义出图案化阻焊层120的阶梯状开口122。
并且，焊料140设置于焊垫112上并位于阶梯状开口122内。芯片150设置于衬底110上并包括有源表面152以及多个接垫154。接垫154设置于有源表面152并通过焊料140而与焊垫112连接。高分子胶体130则填充于图案化阻焊层120的顶面与芯片150的有源表面152之间，其中，高分子胶体130至少环绕焊料140的设置区域并填充于两相邻焊料140之间。
综上所述，本发明将高分子胶体设置于具有阶梯状开口的图案化阻焊层的顶面上，其中，阶梯状开口暴露衬底的焊垫，并且，高分子胶体环绕焊垫的设置区域并设置于两相邻焊垫之间。之后，在将芯片通过焊料而设置于衬底上，如此，由于焊料在回焊固化后会收缩，进而压缩高分子胶体，使高分子胶体可填满图案化阻焊层的顶面与芯片的有源表面之间的间隙，因而可达到密封的效果，防止外界的水气渗入封装结构内。
因此，本发明可通过一次打件作业即同时完成封装结构的防水结构的制作，因而可取代已知的异方性导电膜的工艺，进而简化封装结构的工艺步骤及降低生产成本。此外，由于本发明是利用表面粘着技术(surface-mount technology SMT)而将芯片设置于衬底上，故相对于异方性导电膜来说，其阻抗较为稳定，因此，本发明也可提升封装结构的电性表现。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，均在本发明范围内。

Claims (20)

1.一种封装结构的制作方法，其特征在于，包括：
提供衬底，所述衬底包括多个焊垫；
形成图案化阻焊层于所述衬底上，所述图案化阻焊层包括多个阶梯状开口，所述多个阶梯状开口分别暴露所述多个焊垫；
设置高分子胶体于所述图案化阻焊层的顶面，其中所述高分子胶体至少环绕所述多个焊垫的设置区域并设置于两相邻焊垫之间；
分别设置多个焊料于所述多个焊垫上，其中所述多个焊料分别位于所述多个阶梯状开口内；
设置芯片于所述衬底上，其中所述芯片包括有源表面以及多个接垫，所述多个接垫位于所述有源表面，并通过所述多个焊料而与所述多个焊垫连接；以及
对所述多个焊料进行回焊工艺，并使热熔胶体填充于所述图案化阻焊层的顶面与所述有源表面之间。
2.根据权利要求1所述的封装结构的制作方法，形成所述图案化阻焊层于所述衬底上的步骤还包括：
形成第一阻焊层于所述衬底上，其中所述第一阻焊层覆盖所述多个焊垫；
对所述第一阻焊层进行第一图案化工艺以形成包括多个第一开口的第一图案化阻焊层，所述多个第一开口分别暴露所述多个焊垫；
形成第二阻焊层于所述第一图案化阻焊层上；以及
对所述第二阻焊层进行第二图案化工艺以形成包括多个第二开口的第二图案化阻焊层，其中所述多个第二开口分别暴露所述多个第一开口及环绕所述多个第一开口的部分所述第一图案化阻焊层，各所述第一开口及对应的第二开口共同定义出各所述阶梯状开口。
3.根据权利要求2所述的封装结构的制作方法，所述高分子胶体设置于所述第二图案化阻焊层上。
4.根据权利要求2所述的封装结构的制作方法，所述第一图案化工艺以及所述第二图案化工艺包括曝光显影工艺。
5.根据权利要求1所述的封装结构的制作方法，所述高分子胶体环绕各所述阶梯状开口。
6.根据权利要求1所述的封装结构的制作方法，所述高分子胶体的材料包括合成聚酯树脂。
7.根据权利要求1所述的封装结构的制作方法，所述的封装结构的制作方法还包括：
在分别设置所述多个焊料于所述多个焊垫上之前，对所述高分子胶体进行预固化工艺，以使所述高分子胶体呈现半固化状态。
8.根据权利要求7所述的封装结构的制作方法，所述预固化工艺包括对所述高分子胶体进行加热。
9.根据权利要求8所述的封装结构的制作方法，对所述高分子胶体进行加热的加热温度实质上介于摄氏50度至80度之间。
10.根据权利要求1所述的封装结构的制作方法，分别设置所述多个焊料于所述多个焊垫上的方法包括网板印刷。
11.根据权利要求1所述的封装结构的制作方法，设置所述高分子胶体于所述图案化阻焊层的所述顶面的方法包括网板印刷。
12.根据权利要求1所述的封装结构的制作方法，所述衬底包括软性电路板。
13.一种封装结构，其特征在于，包括：
衬底，包括多个焊垫；
图案化阻焊层，设置于所述衬底上并包括多个阶梯状开口，所述多个阶梯状开口分别暴露所述多个焊垫；
多个焊料，设置于所述多个焊垫上并位于所述多个阶梯状开口内；
芯片，设置于所述衬底上并包括有源表面以及多个接垫，所述多个接垫设置于所述有源表面并通过所述多个焊料而与所述多个焊垫连接；以及
高分子胶体，填充于所述图案化阻焊层的顶面与所述有源表面之间，其中所述高分子胶体至少环绕所述多个焊料的设置区域并填充于两相邻焊料之间。
14.根据权利要求13所述的封装结构，所述图案化阻焊层包括：
第一图案化阻焊层，设置于所述衬底上并包括多个第一开口，所述多个第一开口分别暴露所述多个焊垫；以及
第二图案化阻焊层，设置于所述第一图案化阻焊层上并包括多个第二开口，所述多个第二开口分别暴露所述多个第一开口及环绕所述多个第一开口的部分所述第一图案化阻焊层，其中各所述第一开口及对应的第二开口共同定义出各所述阶梯状开口。
15.根据权利要求14所述的封装结构，所述高分子胶体填充于所述第二图案化阻焊层与所述芯片之间。
16.根据权利要求13所述的封装结构，所述高分子胶体环绕各所述阶梯状开口。
17.根据权利要求13所述的封装结构，所述多个焊料分别填充所述多个阶梯状开口。
18.根据权利要求13所述的封装结构，所述高分子胶体的材料包括合成聚酯树脂。
19.根据权利要求13所述的封装结构，所述衬底包括软性电路板。
20.根据权利要求13所述的封装结构，各所述接垫的尺寸实质上大于各所述焊垫的尺寸。
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