JP2018037632A - パッケージ構造およびその製造方法 - Google Patents
パッケージ構造およびその製造方法 Download PDFInfo
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- JP2018037632A JP2018037632A JP2017029757A JP2017029757A JP2018037632A JP 2018037632 A JP2018037632 A JP 2018037632A JP 2017029757 A JP2017029757 A JP 2017029757A JP 2017029757 A JP2017029757 A JP 2017029757A JP 2018037632 A JP2018037632 A JP 2018037632A
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- resist layer
- solder
- solder resist
- package structure
- patterned
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract
【解決手段】パッケージは、基板110と、パターン化ソルダレジスト層120と、複数のソルダ140と、チップ150と、高分子ゲル130とを含む。基板110は、複数のソルダパッド112を含む。基板110の上のパターン化ソルダレジスト層120は、複数の階段状開口を形成し、ソルダパッド112を露出する。ソルダ140は、ソルダパッド112の上に配置される。作用面152と複数の接合パッド154を含むチップ150は基板110上に配置され、ソルダ140を介してソルダパッド112に接続される。高分子ゲル130は、2つの隣接するソルダ140の間のパターン化ソルダレジスト層120の上表面と作用面152の間の空間を充填する。
【選択図】図1−3
Description
110 基板
112 ソルダパッド
120 パターン化ソルダレジスト層
122 階段状構造
122a 第1開口
122b 第2開口
124 第1パターン化ソルダレジスト層
124a 第1ソルダレジスト層
125、127 パターン化フォトレジスト層
126 第2パターン化ソルダレジスト層
126a 第2ソルダレジスト層
130 高分子ゲル
140 ソルダ
150 チップ
152 作用面
154 接合パッド
Claims (20)
- 複数のソルダパッドを含む基板を提供するステップと、
前記基板の上に、前記ソルダパッドをそれぞれ露出する複数の階段状開口を含むパターン化ソルダレジスト層を形成するステップと、
前記パターン化ソルダレジスト層の上表面に、少なくとも前記ソルダパッドの配置領域を取り囲み、且つ隣接する2つの前記ソルダパッドの間に配置された高分子ゲルを配置するステップと、
前記ソルダパッドの上に、それぞれ前記階段状開口の中に設置された複数のソルダを配置するステップと、
前記基板の上に、作用面と、前記作用面の上に設置され、前記ソルダを介して前記ソルダパッドに接続された複数の接合パッドとを含むチップを配置するステップと、
前記ソルダに対してリフロー処理を行い、前記パターン化ソルダレジスト層の上表面と前記作用面の間に前記高分子ゲルを充填するステップと、
を含むパッケージ構造の製造方法。 - 前記基板の上に前記パターン化ソルダレジスト層を形成する前記ステップが、
前記基板の上に、前記ソルダパッドを覆う第1ソルダレジスト層を形成するステップと、
前記第1ソルダレジスト層に対して第1パターニングプロセスを行い、それぞれ前記ソルダパッドを露出する複数の第1開口を含む第1パターン化ソルダレジスト層を形成するステップと、
前記第1パターン化ソルダレジスト層の上に第2ソルダレジスト層を形成するステップと、
前記第2ソルダレジスト層に対して第2パターニングプロセスを行い、複数の第2開口を含む第2パターン化ソルダレジスト層を形成するステップと、
を含み、前記第2開口が、前記第1開口および前記第1開口を取り囲む前記第1パターン化ソルダレジスト層の一部を露出し、各前記第1開口および対応する前記第2開口が、共同で各前記階段状開口を定義する請求項1に記載のパッケージ構造の製造方法。 - 前記高分子ゲルが、前記第2パターン化ソルダレジスト層の上に配置された請求項2に記載のパッケージ構造の製造方法。
- 前記第1パターニングプロセスおよび前記第2パターニングプロセスが、フォトリソグラフィプロセスを含む請求項2に記載のパッケージ構造の製造方法。
- 前記高分子ゲルが、各前記階段状開口を取り囲む請求項2に記載のパッケージ構造の製造方法。
- 前記高分子ゲルの材料が、合成ポリエステル樹脂を含む請求項2に記載のパッケージ構造の製造方法。
- 前記ソルダパッドの上にそれぞれ前記ソルダを配置するステップの前に、前記高分子ゲルに対して予備硬化プロセスを行って、前記高分子ゲルを半硬化状態にするステップ
をさらに含む請求項1に記載のパッケージ構造の製造方法。 - 前記予備硬化プロセスが、前記高分子ゲルに対して加熱処理を行うことを含む請求項7に記載のパッケージ構造の製造方法。
- 前記高分子ゲルに対して行う前記加熱処理の加熱温度が、実質的に、50℃〜80℃の範囲である請求項8に記載のパッケージ構造の製造方法。
- 前記ソルダパッドの上にそれぞれ前記ソルダを配置する方法が、スクリーン印刷を含む請求項1に記載のパッケージ構造の製造方法。
- 前記パターン化ソルダレジスト層の前記上表面に前記高分子ゲルを配置する方法が、スクリーン印刷を含む請求項1に記載のパッケージ構造の製造方法。
- 前記基板が、フレキシブルプリント回路基板を含む請求項1に記載のパッケージ構造の製造方法。
- 複数のソルダパッドを含む基板と、
前記基板の上に配置され、且つそれぞれ前記ソルダパッドを露出する複数の階段状開口を含むパターン化ソルダレジスト層と、
前記ソルダパッドの上に配置され、且つそれぞれ前記階段状開口の中に設置された複数のソルダと、
前記基板の上に配置され、且つ作用面と、前記作用面の上に設置され、前記ソルダを介して前記ソルダパッドに接続された複数の接合パッドとを含むチップと、
前記パターン化ソルダレジスト層の上表面と前記作用面の間を充填し、少なくとも前記ソルダの配置領域を取り囲み、且つ隣接する2つの前記ソルダの間を充填する高分子ゲルと、
を含むパッケージ構造。 - 前記パターン化ソルダレジスト層が、
前記基板の上に配置され、且つそれぞれ前記ソルダパッドを露出する複数の第1開口を含む第1パターン化ソルダレジスト層と、
前記第1パターン化ソルダレジスト層の上に配置され、且つ複数の第2開口を含む第2パターン化ソルダレジスト層と、
を含み、前記第2開口が、前記第1開口および前記第1開口を取り囲む前記第1パターン化ソルダレジスト層の一部を露出し、各前記第1開口および前記対応する第2開口が、共同で各前記階段状開口を定義する請求項13に記載のパッケージ構造。 - 前記高分子ゲルが、前記第2パターン化ソルダレジスト層と前記チップの間を充填する請求項14に記載のパッケージ構造。
- 前記高分子ゲルが、各前記階段状開口を取り囲む請求項13に記載のパッケージ構造。
- 前記ソルダが、それぞれ前記階段状開口を充填する請求項13に記載のパッケージ構造。
- 前記高分子ゲルの材料が、合成ポリエステル樹脂を含む請求項13に記載のパッケージ構造。
- 前記基板が、フレキシブルプリント回路基板を含む請求項13に記載のパッケージ構造。
- 各前記接合パッドのサイズが、各前記ソルダパッドのサイズよりも実質的に大きい請求項13に記載のパッケージ構造。
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TWI606565B (zh) | 2017-11-21 |
TW201807797A (zh) | 2018-03-01 |
CN107785331A (zh) | 2018-03-09 |
JP6764355B2 (ja) | 2020-09-30 |
EP3291285A1 (en) | 2018-03-07 |
US20180061793A1 (en) | 2018-03-01 |
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