CN107690692B - 形成浅沟槽隔离(sti)结构的方法 - Google Patents

形成浅沟槽隔离(sti)结构的方法 Download PDF

Info

Publication number
CN107690692B
CN107690692B CN201680032734.5A CN201680032734A CN107690692B CN 107690692 B CN107690692 B CN 107690692B CN 201680032734 A CN201680032734 A CN 201680032734A CN 107690692 B CN107690692 B CN 107690692B
Authority
CN
China
Prior art keywords
trench
layer
oxide
etch
planarization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201680032734.5A
Other languages
English (en)
Chinese (zh)
Other versions
CN107690692A (zh
Inventor
贾斯丁·希罗奇·萨托
格雷戈里·艾伦·斯托姆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of CN107690692A publication Critical patent/CN107690692A/zh
Application granted granted Critical
Publication of CN107690692B publication Critical patent/CN107690692B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
    • H10P95/066—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions

Landscapes

  • Element Separation (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
CN201680032734.5A 2015-06-10 2016-06-03 形成浅沟槽隔离(sti)结构的方法 Active CN107690692B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/735,359 US9627246B2 (en) 2015-06-10 2015-06-10 Method of forming shallow trench isolation (STI) structures
US14/735,359 2015-06-10
PCT/US2016/035785 WO2016200693A1 (en) 2015-06-10 2016-06-03 Method of forming shallow trench isolation (sti) structures

Publications (2)

Publication Number Publication Date
CN107690692A CN107690692A (zh) 2018-02-13
CN107690692B true CN107690692B (zh) 2022-01-25

Family

ID=56131655

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680032734.5A Active CN107690692B (zh) 2015-06-10 2016-06-03 形成浅沟槽隔离(sti)结构的方法

Country Status (7)

Country Link
US (2) US9627246B2 (https=)
EP (1) EP3308394B1 (https=)
JP (1) JP2018517300A (https=)
KR (1) KR20180015628A (https=)
CN (1) CN107690692B (https=)
TW (1) TW201703194A (https=)
WO (1) WO2016200693A1 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107017161B (zh) * 2017-05-31 2020-01-24 上海华力微电子有限公司 一种减小sti-cmp过程中碟型凹陷的方法
JP2019169581A (ja) * 2018-03-23 2019-10-03 株式会社東芝 半導体装置の製造方法
CN110707045B (zh) * 2018-10-09 2023-05-12 联华电子股份有限公司 一种制作半导体元件的方法
CN110148579A (zh) * 2019-04-15 2019-08-20 上海华力集成电路制造有限公司 浅沟槽隔离层的制造方法
GB2583348A (en) * 2019-04-24 2020-10-28 Univ Southampton Photonic chip and method of manufacture
CN110660839B (zh) * 2019-11-13 2022-04-29 京东方科技集团股份有限公司 一种显示面板及其制备方法
US11227926B2 (en) * 2020-06-01 2022-01-18 Nanya Technology Corporation Semiconductor device and method for fabricating the same
CN114038744B (zh) * 2021-10-26 2024-12-13 上海华力集成电路制造有限公司 一种mos晶体管制作方法及mos晶体管
CN115346912B (zh) * 2022-10-19 2023-01-03 广州粤芯半导体技术有限公司 浅沟槽隔离结构的制备方法
CN115763358B (zh) * 2022-11-15 2026-02-13 上海华力微电子有限公司 半导体器件的制作方法
US20250113558A1 (en) * 2023-09-28 2025-04-03 Texas Instruments Incorporated Semiconductor device with self-aligned nitride for power isolation
WO2025212375A1 (en) * 2024-04-05 2025-10-09 Applied Materials, Inc. High-density plasma (hdp) topography improvement with partial gapfill carbon
CN121035051B (zh) * 2025-10-22 2026-04-10 荣芯半导体(宁波)有限公司 一种半导体器件及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391781B1 (en) * 2000-01-06 2002-05-21 Oki Electric Industry Co., Ltd. Method of making a semiconductor device
CN103208453A (zh) * 2012-01-11 2013-07-17 国际商业机器公司 用于超薄绝缘体上半导体器件的电隔离结构及其制作方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5026666A (en) * 1989-12-28 1991-06-25 At&T Bell Laboratories Method of making integrated circuits having a planarized dielectric
JPH05235184A (ja) * 1992-02-26 1993-09-10 Nec Corp 半導体装置の多層配線構造体の製造方法
JP3311044B2 (ja) * 1992-10-27 2002-08-05 株式会社東芝 半導体装置の製造方法
US5741740A (en) * 1997-06-12 1998-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer
US6020621A (en) * 1998-01-28 2000-02-01 Texas Instruments - Acer Incorporated Stress-free shallow trench isolation
US6197658B1 (en) * 1998-10-30 2001-03-06 Taiwan Semiconductor Manufacturing Company Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity
US6300219B1 (en) * 1999-08-30 2001-10-09 Micron Technology, Inc. Method of forming trench isolation regions
US20010053583A1 (en) 1999-12-22 2001-12-20 Simon Fang Shallow trench isolation formation process using a sacrificial layer
TW492143B (en) 2001-05-11 2002-06-21 Macronix Int Co Ltd Manufacturing method of shallow trench isolation structure
US6664190B2 (en) 2001-09-14 2003-12-16 Chartered Semiconductor Manufacturing Ltd. Pre STI-CMP planarization scheme
KR100406179B1 (ko) * 2001-12-22 2003-11-17 주식회사 하이닉스반도체 플래쉬 메모리 셀의 자기 정렬 플로팅 게이트 형성 방법
KR20030053958A (ko) * 2001-12-24 2003-07-02 동부전자 주식회사 반도체 소자의 트랜지스터 제조방법
JP4018596B2 (ja) * 2002-10-02 2007-12-05 株式会社東芝 半導体装置の製造方法
US7265014B1 (en) * 2004-03-12 2007-09-04 Spansion Llc Avoiding field oxide gouging in shallow trench isolation (STI) regions
US8017493B2 (en) 2008-05-12 2011-09-13 Texas Instruments Incorporated Method of planarizing a semiconductor device
CN102386084B (zh) * 2010-09-01 2014-01-08 中芯国际集成电路制造(上海)有限公司 平坦化晶圆表面的方法
US8629514B2 (en) * 2011-01-18 2014-01-14 Wafertech, Llc Methods and structures for customized STI structures in semiconductor devices
CN105280545A (zh) * 2014-07-24 2016-01-27 联华电子股份有限公司 半导体装置的浅沟槽隔离结构与其制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391781B1 (en) * 2000-01-06 2002-05-21 Oki Electric Industry Co., Ltd. Method of making a semiconductor device
CN103208453A (zh) * 2012-01-11 2013-07-17 国际商业机器公司 用于超薄绝缘体上半导体器件的电隔离结构及其制作方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
超大规模集成电路制造中硅片平坦化技术的未来发展;郭东明等;《机械工程学报》;20031120(第10期);全文 *

Also Published As

Publication number Publication date
US20160365272A1 (en) 2016-12-15
KR20180015628A (ko) 2018-02-13
JP2018517300A (ja) 2018-06-28
TW201703194A (zh) 2017-01-16
US9627246B2 (en) 2017-04-18
EP3308394A1 (en) 2018-04-18
WO2016200693A1 (en) 2016-12-15
US20170229340A1 (en) 2017-08-10
CN107690692A (zh) 2018-02-13
EP3308394B1 (en) 2022-07-27

Similar Documents

Publication Publication Date Title
CN107690692B (zh) 形成浅沟槽隔离(sti)结构的方法
US8936995B2 (en) Methods of fabricating isolation regions of semiconductor devices and structures thereof
JP2018517300A5 (https=)
US7238586B2 (en) Seamless trench fill method utilizing sub-atmospheric pressure chemical vapor deposition technique
CN111354675B (zh) 浅沟槽隔离结构的形成方法及浅沟槽隔离结构
CN102810471A (zh) 利用含硅掩模形成沟渠的方法
KR100620707B1 (ko) 반도체 소자의 ｓｔｉ 형성 방법
US7968418B1 (en) Apparatus and method for isolating integrated circuit components using deep trench isolation and shallow trench isolation
US9490141B2 (en) Method for planarizing semiconductor device
KR100650902B1 (ko) 반도체 금속 배선 및 그 제조방법
JP4756926B2 (ja) 素子分離構造部の製造方法
WO2016058174A1 (en) Barrier layer removal method and semiconductor structure forming method
KR100605909B1 (ko) 금속배선의 절연막 평탄화 방법
KR100800667B1 (ko) 반도체 소자 제조 방법
KR100500926B1 (ko) 반도체 소자의 소자분리막 형성방법
KR100561524B1 (ko) 소자 분리막 형성 방법
WO2007081089A1 (en) Method of isolating dual-trench element and method of fabricating flash memory by etching active region
CN105632917A (zh) 一种半导体器件及其制造方法
KR100596279B1 (ko) 반도체 소자의 엠아이엠 형성 방법
KR100945871B1 (ko) 듀얼 다마신 공정을 이용한 금속 배선 형성 방법
KR100835420B1 (ko) 반도체장치의 제조방법
KR20060068232A (ko) 반도체 소자 및 그 제조방법
JP2011124427A (ja) 半導体装置の製造方法
KR20090071804A (ko) 고전압 반도체 소자 제조 방법
KR20060075104A (ko) 반도체 소자의 소자 분리막 형성 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant