CN107492557A - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

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CN107492557A
CN107492557A CN201710426030.2A CN201710426030A CN107492557A CN 107492557 A CN107492557 A CN 107492557A CN 201710426030 A CN201710426030 A CN 201710426030A CN 107492557 A CN107492557 A CN 107492557A
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layer
contact hole
semiconductor layer
insulating barrier
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CN107492557B (zh
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花田明纮
渊正芳
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Japan Display Central Inc
Japan Display Inc
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Abstract

一种半导体装置，具备：绝缘基板；第1半导体层，位于绝缘基板的上方；第2半导体层，位于绝缘基板的上方，由与第1半导体层不同的物质形成；绝缘层，位于绝缘基板的上方，覆盖第1半导体层与第2半导体层，并形成有贯通至第1半导体层的第1接触孔与贯通至第2半导体层的第2接触孔；阻挡层，覆盖第1接触孔内的第1半导体层与上述第2接触孔内的第2半导体层中的某一方，并具有导电性；以及第1导电层，与阻挡层接触。

Description

半导体装置以及半导体装置的制造方法
相关申请的交叉引用
本申请基于并主张2016年6月10日提交的日本在先专利申请No.2016-116131号的优先权的利益，这里通过参照将其全部内容引用于此。
技术领域
本发明的实施方式涉及一种半导体装置以及半导体装置的制造方法。
背景技术
薄膜晶体管根据半导体层中使用的材料的不同而显示出各种特性。例如，在将低温多晶硅半导体使用于半导体层的情况下，能够得到可靠性良好的薄膜晶体管。另外，在将氧化物半导体使用于半导体层的情况下，能够得到截止电流小的薄膜晶体管。在将具备多晶硅(polysilicon)半导体层的薄膜晶体管、以及具备氧化物半导体层的薄膜晶体管制作在同一基板上而得到的显示装置中，已知氧化物半导体层位于比多晶硅半导体层靠上层的技术。在这样的显示装置中，在形成贯通至多晶硅半导体层的接触孔之后，为了去除形成于多晶硅半导体层的表面的自然氧化膜而实施清洗。此时，担心清洗所使用的氢氟酸(HF)等清洗液导致氧化物半导体层被蚀刻。
发明内容
根据本实施方式，提供一种半导体装置，具备：绝缘基板；第1半导体层，位于上述绝缘基板的上方；第2半导体层，位于上述绝缘基板的上方，由与上述第1半导体层不同的物质形成；绝缘层，位于上述绝缘基板的上方，覆盖上述第1半导体层和上述第2半导体层，并形成有贯通至上述第1半导体层的第1接触孔和贯通至上述第2半导体层的第2接触孔；阻挡层，将上述第1接触孔内的上述第1半导体层和上述第2接触孔内的上述第2半导体层中的某一方覆盖，并具有导电性；以及第1导电层，与上述阻挡层接触。
根据本实施方式，提供一种半导体装置的制造方法，该半导体装置具备绝缘基板、第1绝缘层、位于上述第1绝缘层的上方的第2绝缘层、位于上述绝缘基板与上述第1绝缘层之间的第1半导体层、以及位于上述第1绝缘层与上述第2绝缘层之间并由与上述第1半导体层不同的物质形成的第2半导体层，其中，该半导体装置的制造方法具备如下工序：形成将上述第2绝缘层贯通至上述第2半导体层的第1接触孔，在上述第2绝缘层和上述第1接触孔内的上述第2半导体层上将导电性的阻挡层成膜，形成将上述阻挡层、上述第1绝缘层以及上述第2绝缘层贯通至上述第1半导体层的第2接触孔，形成在上述第1接触孔内与上述阻挡层接触且在上述第2接触孔内与上述第2半导体层接触的第1导电层。
根据本实施方式，提供一种半导体装置的制造方法，该半导体装置具备绝缘基板、第1绝缘层、位于上述第1绝缘层的上方的第2绝缘层、位于上述绝缘基板与上述第1绝缘层之间的第1半导体层、以及位于上述第1绝缘层与上述第2绝缘层之间并由与上述第1半导体层不同的物质形成的第2半导体层，其中，该半导体装置的制造方法具备如下工序：形成将上述第1绝缘层以及上述第2绝缘层贯通至上述第1半导体层的第1接触孔，在上述2绝缘层和上述第1接触孔内的上述第1半导体层上将导电性的阻挡层成膜，形成将上述阻挡层以及上述第2绝缘层贯通至上述第2半导体层的第2接触孔，形成在上述第1接触孔内与上述阻挡层接触且在上述第2接触孔内与上述第2半导体层接触的上述第1导电层。
根据本实施方式，能够提供可抑制可靠性降低且能够高效地生产的半导体装置、以及半导体装置的制造方法。
附图说明
图1是表示第1实施方式的半导体装置的构成的一个例子的剖面图，
图2A是表示第1实施方式的接触孔的形成工序的剖面图，
图2B是表示第1实施方式的阻挡层的成膜工序的剖面图，
图2C是表示第1实施方式的接触孔的形成工序的剖面图，
图2D是表示第1实施方式的导电层的成膜工序的剖面图，
图3是表示第2实施方式的半导体装置的构成的一个例子的剖面图，
图4A是表示第2实施方式的接触孔的形成工序的剖面图，
图4B是表示第2实施方式的阻挡层的成膜工序的剖面图，
图4C是表示第2实施方式的接触孔的形成工序的剖面图，
图4D是表示第2实施方式的导电层的成膜工序的剖面图，
图5是表示第3实施方式的半导体装置的构成的一个例子的剖面图，
图6是从图5的A－A线俯视端子的情况下的俯视图，
图7A是表示第3实施方式的接触孔的形成工序的剖面图，
图7B是表示第3实施方式的阻挡层的成膜工序的剖面图，
图7C是表示第3实施方式的接触孔的形成工序的剖面图，
图7D是表示第3实施方式的导电层的成膜工序的剖面图。
具体实施方式
以下，边参照附图边对实施方式进行说明。此外，公开的只是一个例子，本领域技术人员针对保留了本发明的主旨的适当变更而容易想到的方案当然也包含于本发明的范围。另外，附图用于使说明更清楚，与实际的形态相比，存在示意性地表示各部分的宽度、厚度、形状等的情况，但也仅仅是一个例子，不用于限定本发明的解释。另外，在本说明书与各附图中，对与已有的附图中叙述过的要素发挥相同或者类似的功能的结构要素标注相同的附图标记，适当省略重复的详细说明。
此外，在实施方式的说明中，所谓上(或者上方)相当于方向Z的箭头朝向，所谓下(或者下方)相当于与方向Z的箭头相反的朝向。
图1是示出第1实施方式的半导体装置1的构成的一个例子的剖面图。图1所示的半导体装置1是具备多个薄膜晶体管(TFT；Thin Film Transistor)TR1以及TR2的TFT基板。
半导体装置1具备绝缘基板10、底涂层UC、半导体层SC1、绝缘膜11、栅电极ML1、金属层SL、绝缘膜12、绝缘膜13、半导体层SC2、绝缘膜14、栅电极ML2、以及绝缘膜15。以下，也有在绝缘基板10上将层叠的底涂层UC、绝缘膜11、绝缘膜12、绝缘膜13、绝缘膜14、以及绝缘膜15汇总称为绝缘层IL的情况。另外，在绝缘层IL中，也有将位于半导体层SC1和半导体层SC2之间的绝缘膜11、12、以及13称为层间绝缘层的情况。也有将绝缘膜11、12以及13汇总称为第1绝缘层，将绝缘膜14以及15汇总称为第2绝缘层的情况。
绝缘基板10例如由具有透光性的玻璃基板或树脂基板形成。底涂层UC为绝缘层，位于绝缘基板10之上。底涂层UC既可以是单层构造也可以是多层构造。例如，底涂层UC具备硅氮化物膜与硅氧化物膜。
半导体层SC1位于绝缘基板10的上方，在图示的例子中形成在底涂层UC之上。半导体层SC1由硅类半导体形成，在一个例子中，由多晶硅(polysilicon)形成。半导体层SC1具有高电阻区域SCc1、以及与高电阻区域SCc1相比电阻更低的低电阻区域SCa1、SCb1。此外，虽然未图示，也可以在绝缘基板10与半导体层SC1之间配置遮光膜。
绝缘膜11覆盖半导体层SC1。在图示的例子中，绝缘膜11也位于底涂层UC之上。在一个例子中，绝缘膜11由硅氧化物形成。
栅电极ML1位于绝缘膜11之上，隔着绝缘膜11而与半导体层SC1对置。栅电极ML1与半导体层SC1的高电阻区域SCc1对置。金属层SL位于绝缘膜11之上，并与栅电极ML1分离。栅电极ML1以及金属层SL分别由导电性的金属材料形成。在图示的例子中，栅电极ML1以及金属层SL因位于同一层上所以也能够利用相同的材料一并形成。栅电极ML1与未图示的第1扫描线电连接。金属层SL位于半导体层SC2的正下方。金属层SL可以作为对经由绝缘基板10以及底涂层UC入射的光向半导体层SC2的照射进行阻止的遮光膜发挥功能。金属层SL也可以作为栅电极发挥功能。金属层SL也可以作为累积电容的电极发挥功能。金属层SL也可以根据用途而变更图案面积。另外，金属层SL在作为遮光膜发挥功能的情况下，可以与由金属材料以外的物质形成的层替换。此外，在半导体装置1被应用于有机电致发光(EL)显示装置的情况下，也可以省略金属层SL。
绝缘膜12位于绝缘膜11之上，覆盖栅电极ML1以及金属层SL。在一个例子中，绝缘膜12由硅氮化物形成。
绝缘膜13位于绝缘膜12之上。在图示的例子中，绝缘膜13位于绝缘膜12与绝缘膜14之间。绝缘膜13在一个例子中由硅氧化物形成。
半导体层SC2相对于绝缘基板10位于比半导体层SC1靠上方的位置。在图示的例子中，半导体层SC2位于绝缘膜13之上，隔着绝缘膜12以及13而与金属层SL对置。半导体层SC2由金属氧化物类的半导体形成。从半导体特性的观点来看，优选形成半导体层SC2的金属氧化物包括铟、钾、锌、锡中的至少1种金属。半导体层SC2具有高电阻区域SCc2、相比于高电阻区域SCc2电阻更低的低电阻区域SCa2以及SCb2。
绝缘膜14位于绝缘膜13之上，覆盖半导体层SC2。绝缘膜14在一个例子中由硅氧化物形成。
栅电极ML2位于绝缘膜14之上，隔着绝缘膜14而与半导体层SC2对置。栅电极ML2与半导体层SC2的高电阻区域SCc2对置。栅电极ML2由导电性的金属材料形成。栅电极ML2与未图示的第2扫描线电连接。绝缘膜15覆盖栅电极ML2。在图示的例子中，绝缘膜15也位于绝缘膜14之上。绝缘膜15既可以是单层构造，也可以是多层构造。在一个例子中，绝缘膜15由硅氮化物或硅氧化膜形成。
并且，半导体装置1具备端子T1a、T1b、T2a、T2b、以及T3。端子T1a、T1b、T2a、T2b、以及T3分别位于绝缘膜15之上。端子T1a、T1b、T2a、T2b、以及T3与省略了图示的布线等电连接。在图示的例子中，端子T1a、T1b、T2a、T2b、以及T3分别具备阻挡层BC1a、BC1b、BC2a、BC2b、及BC3和导电层MC1a、MC1b、MC2a、MC2b、及MC3。
阻挡层BC1a、BC1b、BC2a、BC2b以及BC3由相同的导电性的金属材料、合金、或者低电阻的氧化物形成。而且，在本实施方式中，阻挡层BC优选为对于后述的制造方法中用于清洗的物质例如氢氟酸具有耐性。阻挡层BC1a、BC1b、BC2a、BC2b以及BC3既可以是单层构造，也可以是多层构造，例如由钛(Ti)等形成。此外，有时也将阻挡层BC1a、BC1b、BC2a、BC2b以及BC3称作导电层。
导电层MC1a、MC1b、MC2a、MC2b、以及MC3例如由导电性的金属材料形成，既可以是单层构造，也可以是多层构造。例如，导电层MC1a、MC1b、MC2a、MC2b、以及MC3为钛/铝/钛的多层构造。
端子T1a、T1b、T2a、T2b、以及T3的各自的端部在俯视的情况下，以导电层MC1a、MC1b、MC2a、MC2b、以及MC3和阻挡层BC1a、BC1b、BC2a、BC2b以及BC3重叠的方式形成。
端子T1a以及T1b分别覆盖将绝缘膜11、12、13、14以及15贯通的接触孔CH1a以及CH1b内，并与半导体层SC1电连接。以下，将接触孔CH1a内的由绝缘膜11、12、13、14以及15构成的表面称作侧面S1a，将接触孔CH1b内的由绝缘膜11、12、13、14以及15构成的表面称作侧面S1b。在图示的例子中，在端子T1a以及T1b中，阻挡层BC1a以及BC1b分别位于形成有接触孔CH1a以及CH1b的部分的绝缘膜15(或者，绝缘层IL)的上表面TP，在接触孔CH1a以及CH1b内不存在于半导体层SC1上。导电层MC1a以及MC1b分别在绝缘膜15的上方使一部分位于阻挡层BC1a以及BC1b之上，并覆盖接触孔CH1a的内表面S1a以及接触孔CH1b的内表面S1b，且在接触孔CH1a以及CH1b内覆盖半导体层SC1。导电层MC1a在接触孔CH1a中从内表面S1a遍及到低电阻区域SCa1地接触，导电层MC1b在接触孔CH1b中从内表面S1b遍及到低电阻区域SCb1地接触。此外，端子T1a以及T1b在绝缘膜15的上表面TP、接触孔CH1a以及CH1b内的层的厚度也可以分别不同。
端子T2a以及T2b分别将贯通了绝缘膜14以及15的接触孔CH2a以及接触孔CH2b内覆盖，并与半导体层SC2电连接。以下，将接触孔CH2a内的由绝缘膜14以及15构成的表面称作侧面S2a，将接触孔CH1b内的由绝缘膜14以及15构成的表面称作侧面S2b。在图示的例子中，在端子T2a以及T2b中，阻挡层BC2a以及BC2b分别使一部分位于绝缘膜15的上表面TP，并覆盖接触孔CH1a的内表面S1a以及接触孔CH1b的内表面S1b，且在接触孔CH2a以及CH2b内覆盖半导体层SC2。导电层MC2a以及MC2b分别在绝缘膜15的上方与接触孔CH2a以及CH2b内位于阻挡层BC2a以及BC2b之上。阻挡层BC2a在接触孔CH2a中从内表面S2a遍及到低电阻区域SCa2地接触，导电层MC2a在接触孔CH2a中接触于阻挡层BC2a。阻挡层BC2b在接触孔CH2b中从内表面S2b遍及到低电阻区域SCb2地接触，导电层MC2b在接触孔CH2b中接触于阻挡层BC2b。
端子T3将贯通了绝缘膜12、13、14、以及15的接触孔CH3内覆盖，并与金属层SL电连接。以下，将接触孔CH3内的由绝缘膜12、13、14、以及15构成的表面称作侧面S3。在图示的例子中，在端子T3中，阻挡层BC3位于绝缘膜15的上表面TP，且不存在于接触孔CH3内。导电层MC3在绝缘膜15的上方使一部分位于阻挡层BC3之上，并覆盖接触孔CH3的内表面S3，且在接触孔CH3内覆盖金属层SL。此外，端子T3在绝缘膜15之上和接触孔CH3内的层的厚度也可以不同。端子T3例如也可以与固定电位的电源线、或未图示的扫描线电连接。在端子T3与电源线连接的情况下，能够使金属层SL作为遮光膜或电容电极等发挥功能。另外，在端子T3与扫描线电连接的情况下，能够使金属层SL作为薄膜晶体管TR2的栅电极发挥功能。此外，金属层SL也可以为电浮置，此时，也可以省略端子T3以及接触孔CH3。
在图示的例子中，薄膜晶体管TR1以及TR2是栅电极ML1以及栅电极ML2分别位于半导体层SC1以及SC2的上方的所谓顶栅构造的TFT。但是，薄膜晶体管TR1以及TR2的构造不特别限定，薄膜晶体管TR1或者TR2也可以是底栅构造。
接下来，参照图2A、2B、2C以及2D，对本实施方式的半导体装置1的制造方法进行说明。
图2A是表示本实施方式的接触孔CH2a以及CH2b的形成工序的剖面图，图2B是表示本实施方式的阻挡层BC的成膜工序的剖面图，图2C是表示本实施方式的接触孔CH1a以及CH1b的形成工序的剖面图，图2D是表示本实施方式的导电层MC的成膜工序的剖面图。
首先，如图2A所示的那样，在绝缘基板10之上形成绝缘层IL、半导体层SC1以及SC2、金属层SL、栅电极ML1以及ML2等之后，形成接触孔CH2a以及CH2b。更具体而言，在绝缘膜15之上，在经由光刻工序而形成了图案化的光致抗蚀剂之后，通过对从光致抗蚀剂露出的区域进行蚀刻的光刻工序(以下，简称为光刻)，形成将绝缘层IL贯通至半导体层SC2的接触孔CH2a以及CH2b。
接下来，如图2B所示的那样，将阻挡层BC在图2A所示的状态的绝缘层IL之上成膜，并经由接触孔CH2a的内表面S2a以及CH2b的内表面S2b，在半导体层SC2之上成膜。阻挡层BC是加工成上述的阻挡层BC1a、BC1b、BC2a、BC2b以及BC3以前的状态的层。
接下来，如图2C所示，例如通过光刻，将阻挡层BC以及绝缘层IL一并蚀刻直至半导体层SC1而形成接触孔CH1a以及CH1b。之后，为了去除半导体层SC1的自然氧化膜、例如硅(Si)氧化膜，而执行清洗例如氢氟酸(HF)清洗。此时，半导体层SC2被阻挡层BC保护免受用于清洗的物质即氢氟酸的影响。此外，如图2C所示，在形成接触孔CH1a以及CH1b时，接触孔CH3也可以与接触孔CH1a以及CH1b同样地，例如通过光刻将阻挡层BC以及绝缘层IL一并蚀刻至金属层SL而形成。
而且，如图2D所示，导电层MC在图2C所示的阻挡层BC之上成膜，并经由接触孔CH1a的内表面S1a及接触孔CH1b的内表面S1b在半导体层SC1之上成膜。另外，导电层MC在图2C所示的阻挡层BC之上成膜，并经由接触孔CH3的内表面S3在金属层SL之上成膜。导电层MC是加工成上述导电层MC1a、MC1b、MC2a、MC2b、以及MC3以前的状态的层。最后，例如通过光刻一并对图2D所示的阻挡层BC以及导电层MC进行图案化，作为一个例子，形成图1所示的半导体装置1的端子T1a、T1b、T2a、T2b、以及T3。
如以上那样，根据本实施方式，在接触孔CH2a以及CH2b内将阻挡层BC成膜之后，通过对阻挡层BC与绝缘层IL一并进行蚀刻，形成接触孔CH1a以及CH1b。因此，半导体装置1能够在保护了氧化物半导体制的半导体层SC2的状态下，通过清洗去除形成于多晶硅制的半导体层SC1上的自然氧化膜。由于阻挡层BC具有导电性，因此无需被从接触孔CH2a以及CH2b去除，就能够形成与半导体层SC2电连接的端子T2a以及T2b。而且，通过一并对阻挡层BC与绝缘层IL进行蚀刻，能够减少制造工序。另外，半导体装置1在薄膜晶体管TR2为顶栅构造的情况下，不需要在半导体层SCa2或SCb2上形成用于在接触孔形成时防止半导体层穿透的导电层例如金属层等的工序。因此，半导体装置1能够抑制可靠性的降低，且能够实现高效的生产。
接下来，对其他实施方式的半导体装置进行说明。在以下说明的其他实施方式中，对与上述第1实施方式相同的部分标注相同的参照附图标记，并省略详细的说明，以与第1实施方式不同的部分为中心进行详细说明。此外，在其他实施方式中，也能够获得与上述第1实施方式相同的效果。
图3是表示第2实施方式的半导体装置的构成的一个例子的剖面图。第2实施方式的半导体装置1与第1实施方式的半导体装置1相比较，不同点在于，阻挡层BC1a、BC1b、BC2a以及BC2b和导电层MC1a、MC1b、MC2a以及MC2b的位置不同。此外，在图示的例子中，半导体装置1可以不具有接触孔CH3和端子T3，也可以与图1所示的第2实施方式相同具有这些。
在图示的例子中，在端子T1a以及T1b中，阻挡层BC1a以及BC1b分别使一部分位于绝缘膜15的上表面TP，覆盖接触孔CH1a的内表面S1a以及接触孔CH1b的内表面S1b，并且在接触孔CH1a以及CH1b内覆盖半导体层SC1。导电层MC1a以及MC1b分别位于阻挡层BC1a以及BC1b之上。并且，在图示的例子中，在端子T2a以及T2b中，阻挡层BC2a以及BC2b分别位于形成有接触孔CH2a以及CH2b的部分的绝缘膜15的上表面TP上，不存在于接触孔CH2a以及CH2b内。导电层MC2a以及MC2b分别使一部分位于阻挡层BC2a以及BC2b之上，覆盖接触孔CH2a的内表面S2a以及接触孔CH2b的内表面Sb，且在接触孔CH2a以及CH2b内覆盖半导体层SC2。
接下来，参照图4A、4B、4C以及4D，对本实施方式的半导体装置1的制造方法进行说明。
图4A是表示本实施方式的接触孔CH1a以及CH1b的形成工序的剖面图，图4B是表示本实施方式的阻挡层BC的成膜工序的剖面图，图4C是表示本实施方式的接触孔CH2a以及CH2b的形成工序的剖面图，图4D是表示本实施方式的导电层MC的成膜工序的剖面图。
首先，如图4A所示，通过光刻(工序)，形成将绝缘层IL贯通至半导体层SC1的接触孔CH1a以及CH1b。之后，为了去除半导体层SC1的自然氧化膜而执行清洗。
接下来，如图4B所示，为了防止半导体层SC1的氧化，阻挡层BC成膜在图4A所示的状态的绝缘层IL之上，并经由接触孔CH1a的内表面S1a以及接触孔CH1b的内表面S1b成膜在半导体层SC1之上。
接下来，如图4C所示，例如通过光刻，将阻挡层BC以及绝缘层IL一并蚀刻至半导体层SC2而形成接触孔CH2a以及CH2b。
进而，如图4D所示，导电层MC成膜在图4C所示的状态的阻挡层BC之上，并经由接触孔CH2a的内表面S2a以及接触孔CH2b的内表面S2b成膜在半导体层SC2之上。最后，例如通过光刻一并对图4D所示的阻挡层BC以及导电层MC进行图案化，作为一个例子而形成图3所示的半导体装置1的端子T1a、T1b、T2a以及T2b。
在这样的第2实施方式中，也可获得与第1实施方式相同的效果。
图5是表示第3实施方式的半导体装置的构成的一个例子的剖面图。
第3实施方式的半导体装置1与上述的实施方式的半导体装置1相比，不同点在于，薄膜晶体管TR1以及TR2的分离距离比上述的实施方式更近。
本实施方式的半导体装置1在接触孔CH12a的边缘的内侧形成接触孔CH12b，取代上述的实施方式的端子T1b以及T2a而具备端子T12。端子T12具备阻挡层BC12和导电层MC12。端子T12将接触孔CH12a以及CH12b内覆盖，并与半导体层SC1以及SC2电连接。这里，将接触孔CH12a内的由绝缘膜14以及15构成的表面称作侧面S12a，将接触孔CH12b内的由绝缘膜11以及12构成的表面称作侧面S12b。在图示的例子中，在端子T12中，阻挡层BC12的一部分位于绝缘膜15之上，覆盖接触孔S12a的内表面S12a，且在接触孔CH12a内覆盖半导体层SC2。导电层MC12在绝缘膜15的上方使一部分位于阻挡层BC12之上，覆盖接触孔S12b的内表面S12b，且在接触孔CH12a的边缘的内侧形成的接触孔CH12b内覆盖半导体层SC1。换句话说，导电层MC12将半导体层SC1以及SC2电连接。
图6是从图5的A－A线俯视端子T12的情况下的俯视图。
如图6所示，接触孔CH12a以及CH12b在俯视的情况下重叠地形成。此外，在俯视的情况下，接触孔CH12a以及CH12b无需在整个区域重叠地形成，只要在至少一部分的区域重叠地形成即可。另外，如图6所示，在端子T12中，阻挡层BC12与导电层MC12的端面在俯视的情况下重叠地形成。
接下来，参照图7A、7B、7C、以及7D，对本实施方式的半导体装置1的制造方法进行说明。此外，关于端子T1a以及T2b的制造方法，能够使用与第1实施方式相同的制造方法，因此省略详细的说明。
图7A是表示本实施方式的接触孔CH12a的形成工序的剖面图，图7B是表示本实施方式的阻挡层BC的成膜工序的剖面图，图7C是表示本实施方式的接触孔CH12b的形成工序的剖面图，图7D是表示本实施方式的导电层MC的成膜工序的剖面图。
首先，如图7A所示，通过光刻(工序)，形成将绝缘层IL贯通至半导体层SC2的接触孔CH12a。在图示的例子中，接触孔CH12a通过将从半导体层SC2的低电阻区域SCa2的上方至半导体层SC1的上方的绝缘膜14以及15刻蚀而形成，与上述的实施方式的接触孔CH2a相比较，形成得较宽。
接下来，如图7B所示，阻挡层BC成膜在图7A所示的状态的绝缘层IL之上，并经由接触孔CH12a的内表面S12a成膜在半导体层SC2之上。
接下来，如图7C所示，例如通过光刻，在接触孔CH12a的边缘的内侧的底部，将阻挡层BC以及绝缘层IL一并蚀刻至半导体层SC1而形成接触孔CH12b。之后，为了去除半导体层SC1的自然氧化膜而执行清洗。
而且，如图7D所示，导电层MC成膜在图7C所示的阻挡层BC之上，并经由接触孔CH12a的内表面S12a以及接触孔CH12b的内表面S12b成膜在半导体层SC1之上。最后，例如通过光刻对图7D所示的阻挡层BC以及导电层MC一并图案化，作为一个例子，形成图5所示的半导体装置1的端子T1a、T2b以及T12。
根据第3实施方式，可获得与上述的第1实施方式相同的效果。并且，在第3实施方式的半导体装置1中，在接触孔CH12a的边缘的内侧形成接触孔CH12b，由位于接触孔CH12a以及CH12b的单一的端子T12将半导体层SC1以及SC2电连接。因此，根据第3实施方式，与将接触孔CH12a以及CH12b形成于分开的位置的情况相比，能够在更小的空间内形成这些接触孔，并将薄膜晶体管TR1以及TR2电连接。由此，能够提供有利于高精细化的构成。
如以上说明，根据本实施方式，能够提供可抑制可靠性降低、且能够高效地生产的半导体装置。
虽然以上叙述了具体实施方式，但应当理解为上述实施方式仅是一例，对本发明不起限定性作用。实质上，在不脱离本发明主旨的范围内，上述实施方式能够以其他不同的变形方式加以实施，此外，进行了各种省略、替换以及变更的技术方案也包含于本发明。此外，本发明还包含与权利要求书等同的含义以及等同范围内的全部变更。

Claims (20)

1.一种半导体装置，具备：
绝缘基板；
第1半导体层，位于上述绝缘基板的上方；
第2半导体层，位于上述绝缘基板的上方，由与上述第1半导体层不同的物质形成；
绝缘层，位于上述绝缘基板的上方，覆盖上述第1半导体层和上述第2半导体层，并形成有贯通至上述第1半导体层的第1接触孔和贯通至上述第2半导体层的第2接触孔；
阻挡层，将上述第1接触孔内的上述第1半导体层和上述第2接触孔内的上述第2半导体层中的某一方覆盖，并具有导电性；以及
第1导电层，与上述阻挡层接触。
2.根据权利要求1所述的半导体装置，其中，具备：
第1栅电极，与上述第1半导体层对置；以及
第2栅电极，与上述第2半导体层对置。
3.根据权利要求1所述的半导体装置，其中，
具备在上述第1半导体层以及上述第2半导体层内的至少一方的下方对置的金属层。
4.根据权利要求1所述的半导体装置，其中，
上述第1半导体层以及上述第2半导体层内的某一方由多晶硅形成，另一方由氧化物半导体形成。
5.根据权利要求1所述的半导体装置，其中，
上述绝缘层在上述第1半导体层与上述第2半导体层之间具备层间绝缘层。
6.根据权利要求1所述的半导体装置，其中，
上述绝缘层具备第1绝缘层和位于上述第1绝缘层的上方的第2绝缘层，
上述第1半导体层由多晶硅形成，位于上述绝缘基板与上述第1绝缘层之间，
上述第2半导体层由氧化物半导体形成，位于上述第1绝缘层与上述第2绝缘层之间。
7.根据权利要求1所述的半导体装置，其中，
上述阻挡层的一部分位于上述绝缘层的上表面，上述第1导电层的一部分在上述绝缘层的上方位于上述阻挡层之上。
8.根据权利要求1所述的半导体装置，其中，
上述阻挡层与上述第1导电层的端面重叠。
9.根据权利要求8所述的半导体装置，其中，
上述阻挡层与上述第1导电层的端面位于上述绝缘层的上表面。
10.根据权利要求1所述的半导体装置，其中，
上述阻挡层由对氢氟酸具有耐性的导电性的金属材料形成。
11.根据权利要求1所述的半导体装置，其中，具备：
第2导电层，位于形成有上述第2接触孔的部分的上述绝缘层的上表面；以及
第3导电层，由与上述阻挡层相同的材料形成，位于上述第2导电层之上，并在上述第2接触孔内覆盖上述第2半导体层，
上述阻挡层在上述第1接触孔内覆盖上述第1半导体层。
12.根据权利要求11所述的半导体装置，其中，
上述第2导电层与上述第3导电层的端面重叠。
13.根据权利要求1所述的半导体装置，其中，
上述绝缘层具有贯通至上述第1半导体层以及上述第2半导体层的第3接触孔，
上述阻挡层在上述第3接触孔内覆盖上述第2半导体层，
上述第1导电层在上述第3接触孔内覆盖上述阻挡层以及上述第1半导体层。
14.根据权利要求13所述的半导体装置，其中，
上述阻挡层的一部分位于上述绝缘层的上表面，上述第1导电层的一部分在上述绝缘层的上方位于上述阻挡层之上。
15.一种半导体装置的制造方法，该半导体装置具备绝缘基板、第1绝缘层、位于上述第1绝缘层的上方的第2绝缘层、位于上述绝缘基板与上述第1绝缘层之间的第1半导体层、以及位于上述第1绝缘层与上述第2绝缘层之间并由与上述第1半导体层不同的物质形成的第2半导体层，其中，该半导体装置的制造方法具备如下工序：
形成将上述第2绝缘层贯通至上述第2半导体层的第1接触孔；
在上述第2绝缘层与上述第1接触孔内的上述第2半导体层之上，将导电性的阻挡层成膜；
形成将上述阻挡层、上述第1绝缘层以及上述第2绝缘层贯通至上述第1半导体层的第2接触孔；以及
形成在上述第1接触孔内与上述阻挡层接触且在上述第2接触孔内与上述第2半导体层接触的第1导电层。
16.根据权利要求15所述的半导体装置的制造方法，其中，
在形成上述第2接触孔之后，用氢氟酸进行清洗。
17.根据权利要求16所述的半导体装置的制造方法，其中，
在形成上述第1导电层之后，将上述阻挡层以及上述第1导电层一并图案化。
18.一种半导体装置的制造方法，该半导体装置具备绝缘基板、第1绝缘层、位于上述第1绝缘层的上方的第2绝缘层、位于上述绝缘基板与上述第1绝缘层之间的第1半导体层、以及位于上述第1绝缘层与上述第2绝缘层之间并由与上述第1半导体层不同的物质形成的第2半导体层，其中，该半导体装置的制造方法具备如下工序：
形成将上述第1绝缘层以及上述第2绝缘层贯通至上述第1半导体层的第1接触孔；
在上述2绝缘层和上述第1接触孔内的上述第1半导体层之上，将导电性的阻挡层成膜；
形成将上述阻挡层以及上述第2绝缘层贯通至上述第2半导体层的第2接触孔；以及
形成在上述第1接触孔内与上述阻挡层接触且在上述第2接触孔内与上述第2半导体层接触的上述第1导电层。
19.根据权利要求18所述的半导体装置的制造方法，其中，
在形成上述第1接触孔之后，用氢氟酸进行清洗。
20.根据权利要求19所述的半导体装置的制造方法，其中，
在形成上述第1导电层之后，将上述阻挡层以及上述第1导电层一并图案化。
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