CN1037924C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1037924C
CN1037924C CN95104250A CN95104250A CN1037924C CN 1037924 C CN1037924 C CN 1037924C CN 95104250 A CN95104250 A CN 95104250A CN 95104250 A CN95104250 A CN 95104250A CN 1037924 C CN1037924 C CN 1037924C
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金载甲
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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Abstract

本发明公开一种半导体器件，它显著缩小了元件隔离区的面积和基底电极的面积，因而促进了高集成化，该器件包括一含有N阱、P阱及深槽元件隔膜的P型半导体基片，该深槽元件隔离膜介于N阱和P阱之间，在每个N阱和P阱内分别建立P-MOSFET和N-MOSFET，形成与P-MOS-FET源电极相接触的N型基底电极被施加VDD电压。

Description

半导体器件及其制造方法
本发明一般涉及一种半导体器件，特别涉及一种大大缩小了N阱和P阱间的元件隔离区面积和基底电极面积的CMOS器件。另外，本发明还涉及该半导体器件的制造方法。
一般地说，在一集成电路中，一包括晶体管和电容器的半导体器件形成一个独立的元件，这样它要求在各有源区之间有元件隔离区，以避免元件在其工作中相互干扰。
近年来半导体器件高集成度的趋势迫使人们去做许多尝试，以减小在半导体器件中通常占有大面积的元件隔离区。为此目的已开发出许多工艺。有代表性的是硅局部氧化(LOCOS)工艺和选择性多硅氧化(SEPOX)工艺。按LOCOS工艺，元件的隔离氧化膜是在有氮化膜图形掩模的情况下，局部露出半导体基片，使半导体基片热氧化而形成的。同样，SEPOX工艺包括在有由多硅膜和氮化膜相结合的图形组成的掩模的情况下，局部露出半导体基片，使半导体基片热氧化。除以上工艺以外，还有一种工艺，是先使半导体基片有选择地腐蚀形成深槽，然后填以绝缘材料，而形成深槽元件隔离氧化膜。在上述各工艺中，LOCOS工艺是使用最广泛的，因为该工艺相对来说是比较简单的。
为了更好地了解本发明的背景技术，先描述一下LO-COS工艺。首先，使硅半导体基片的表面热氧化，以生长底衬氧化膜(pad oxide film)。然后，在底衬氧化膜上形成氮化膜图形，以露出预定要形成元件隔离区的半导体基片的预定面积，实施另一次热氧化，用氮化膜图形做掩模，使半导体基片生长一场氧化膜(field oxide film)。
然而，这种LOCOS工艺存在一种公知的鸟嘴问题，即场氧化膜侵入了有源区，导致有源区面积的减小。此外，为了形成光敏膜图形进行后序的曝光工艺时，光会被乌嘴的倾斜表面反射，以致使光敏膜受到不希望有的光照。其结果，产生了豁口问题。当设计标准为0.4μm或更细，在半导体器件内刻制一栅电极时，这些问题会引起生产效率和可靠性的下降。
参照图1，示出表示一个典型的由相互连接的一N型MOSFET和一P型MOSFET组成的CMOS器件的电路原理图。如图1所示，PMOS和NMOS的源电极(S)分别连到VDD和VSS，而其漏电极(D)相互连接。
参照图2，这是一个主掩模布局图，通常布置有N阱掩模1，、有源掩模2、栅掩模3、接触孔掩模4、以及布线掩模5，以便制作图1的电路。
图3表示一个用常规技术制作的沿图2的I-I线剖取的半导体器件。其制作工艺先分别用P阱掩模(未图示)和N阱掩模1，在P型半导体基片11的预定面积形成P阱13和N阱12。然后，在两阱之间的边界上和这些阱的预定面积上形成元件隔离膜14。在每个阱上形成栅氧化膜15，然后使用栅掩模3在栅氧化膜上形成栅电极16。同时，以该栅结构作为一掩模，使N型杂质注入到P阱13中，而使P型杂质注入到N阱12中。其结果，在每一阱内建立起一组源电极17和漏电极18。将VSS电压施加于P型半导体基底11。为给P阱13施加VDD电压，将N型杂质注入到源电极17A所分离的区域及P阱13内的元件隔离氧化膜14，从而建立起基底电极19。然后，在MOSFET结构上涂镀一铺垫层间绝缘膜。使用接触孔掩模4通过腐蚀工艺，对铺垫膜刻图，形成含有接触孔20的层间绝缘膜21的图形，通过各孔20露出源电极17A、17B、漏电极18A、18B以及基底电极19。使用布线掩模5，形成三条布线22。其一使P-MOSFET的源电极17A、基底电极19与VDD连接，另一个作为P-MOSFET的漏电极18A和N-MOSFET的漏电极18B之间的连接，第三条使N-MOSFET的源电极17B与VSS相连接。
如上所述，用于使N-MOSFET与P-MOSFET隔开的元件隔离氧化膜，若用LOCOS制作，会占很大面积。上述常规技术在使半导体器件达到高集成化上还有另一难题，因为额外形成的基底电极是被元件隔离氧化膜与P-MOSFET的源电极分开的，这要花费太多的面积。
本发明之主要目的在于克服现有技术中所遇到的上述问题，并提供一种有助于高集成化具有新结构的半导体器件。
本发明的另一目的在于提供一种制作该半导体器件的方法。
根据本发明的一种方案，提供一种半导体器件，它包括：一含N阱和P阱以及深槽元件隔离膜的P型半导体基片，各个所说的深槽元件隔离膜均介于N阱与P阱之间；分别建立在各N阱和P阱内的一个P-MOSFET和一个N-MOSFET；以及一个N型基底电极，该电极形成在P-MOS-FET的源电极的一定部分，并施加VDD电压。
根据本发明的另一方案，提供一种制作该半导体器件的方法，该方法包括以下各步骤：基底在P型半导体基片的预定部位形成N阱和P阱；在N阱和P阱间的边界形成填充以绝缘材料的深槽，所说的深槽用作所说各阱的元件隔离槽；在各N阱和P阱上建立栅结构，所说的栅结构是栅氧化膜、栅电极及第一绝缘膜图形的叠层；使杂质注入到N阱和P阱内，形成各自的源电极和漏电极，所说的杂质的类型与待注入的阱的类型相反；依次在所得结构上淀积第二绝缘膜和腐蚀阻止层；在所说的腐蚀阻止层的侧壁形成绝缘衬层，所说的侧壁被用作所说的叠质结构；使N型杂质注入到有光敏膜图形的P-MOSFET的源电极的一部分内，以形成N型基底电极，所说的光敏膜图形覆盖整个结构，但所说的源电极除外，其有一部分未被所说的绝缘衬垫覆盖；去掉所说的光敏膜图形亦在所得结构上涂镀铺垫第三绝缘膜；使用接触掩模有选择地腐蚀该第三绝缘膜，形成各接触孔，露出P阱的所述源电极、漏电极及基底电极；以及形成布线图形，以此使P阱的源电极和所说的基底电极与VDD相连接，P阱的漏电极与N阱的漏电极相连接，及使N阱的源电极与VSS相连接。
通过参照附图详细地描述本发明优选实施例会使本发明的上述目的及其它优点更加明了。
图1是表示包括相互连接的N型MOSFET和P型MOS-FET的典型CMOS器件的CMOS电路原理图；
图2是为制作图1的电路所常规布置的掩模布局图；
图3是表示使用图2的组合掩模所制造的常规半导体器件的沿图2的I-I线的示意剖面图；
图4是根据本发明为制造图1的电路布置的掩模布局图；
图5是表示使用图4的组合掩模所制造的半导体器件沿图4的II-II线示意剖面图；
图6A～6E是表明根据本发明制作半导体器件方法的示意剖面图。
参照附图会最好地了解本发明优选实施例的应用，其中相同的标号分别用于相同的及相对应的部分。
参照图4，这是掩模的布局图，图中是为制作图1的电路重新布置的N阱掩模1、栅掩模3、接触孔掩模4、布线掩模5及深槽掩模6。位于深槽掩模6内的方块面积是有源区。
参照图5，是根据本发明所制作的沿图4的II-II线的半导体器件的剖面图。下面进一步描述，本半导体器件在几个方面完全不同于常规器件。首先，取代场氧化膜，采用深槽作为元件隔离装置。在图3的常规半导体器件中，在半导体基片31内形成P阱32和N阱33，在N阱和P阱之间形成宽约0.3～3.0μm、深约1.5～10μm的深槽34。用绝缘材料填入该深槽34，形成掩埋层(buried layer)，达到使元件相互隔离的目的。所以，借助深槽使被元件隔离装置所占据半导体基片的面积最大限度地减小。另一明显差别是基底电极的位置。在常规半导体器件中，如上所述，在N阱区所形成的基底电极是与P-MOSFET的源电极和漏电极分离开的。与常规半导体器件相反，本发明的半导体器件所包括的基底电极39形成在与P-MOSFET的源电极37相接触的位置。所以，本发明中不再需要为使基底电极与源、漏电极分开的所必需的元件隔离氧化膜。因而，本半导体器件可确保更大的面积。
图6表示制造图5的半导体器件的优选工艺步骤。现在结构图6A～6E更详细的描述这些优选工艺步骤。
参照图6A，有一个半导体基片31，在其中交替形成P阱32和N阱33以及在其间形成的深槽34。使用N阱掩模(图4中用标号“1”代表)和P阱掩模(未图示)在半导体基片31各自的预定面积内形成P阱32和N阱33。至于深槽，使用深槽掩模(图4用标号“6”代表)腐蚀半导体基片31到预定深度。用一种绝缘材料，例如用氧化膜，填入所形成的深槽，以形成掩埋层43。
参照图6B，示出建立N-MOSFET和P-MOSFET结构的情况。为此，首先，在图6A的所得结构的整个表面上生长栅氧化物35，接着依次形成导电层，并在栅氧化物35上形成第一绝缘膜，然后使用栅掩模(在图4中用标号“3”代表)对整个结构进行腐蚀处理，以在P阱32和N阱33形成栅电极36。用栅电极36作掩模，使N型杂质注入到P阱32内，形成源电极37B和漏电极38B。同样，用P型杂质掺杂N阱33，形成源电极37A和漏电极38A。在所得N-MOSFET和P-MOSFET结构上，依次形成第二绝缘膜45、较薄的氧化膜及腐蚀阻止层46。腐蚀阻止层46是一层腐蚀速率不同于第二绝缘膜的膜，比如是氮化膜。
参照图6C，在腐蚀阻止层46的侧壁形成绝缘衬垫47，其侧壁用作由栅电极36和第一绝缘膜44组成的叠层结构，同时形成光敏膜图形48，以只露出一部分未被绝缘衬垫47覆盖的P-MOSFET的源电极37A，接着使N型杂质注入到源电极37A的裸露面积内。作为这种注入的结果，形成与源电极37A接触的N型基底电极39。该基底电极39是通过光敏膜图形48和绝缘衬垫47自对准的。
参照图6D，在去掉光敏膜图形48之后，为使所得结构平面化，形成铺垫第三绝缘层49，例如BPSG(硼磷硅玻璃)，然后用光敏膜图形50覆盖。至于该光敏膜图形50，在平坦的表面上完全形成一光敏膜，借助于接触孔掩模(在图4中用标号“4”代表)进行曝光和显影，以使其预定面积打开。
参照图6E，用光敏膜图形50作掩模，有选择地腐蚀从平坦层49至第二绝缘膜45的多层结构，形成接触孔，通过此孔露出源电极37A、37B、漏电极38A、38B及基底电极39，接着去掉光敏膜图形50。在去掉光敏膜图形50之后，形成布线42，它起到一种使各电极与外电压互连的作用：使P-MOSFET的源电极37A和基底电极39与VDD连接；使P-MOSFET的漏电极38A与N-MOSFET的源电极38B之间相连接；使N-MOSFET的源电极37B与VSS连接。这些布线42是通过淀积一层铺垫导电层，并利用布线掩模(图4中用标号“S”代表)使其刻成图形而形成的。
如上之所述，根据本发明，通过在半导体基片内所形成的位于P阱和N阱之间且填充以绝缘材料的深槽，可使通常在半导体器件中占有很大面积的元件隔离区显著地缩小。这种在元件隔离区中的面积的减小有助于达到半导体器件的高集成化。此外，根据本发明的半导体器件包括一个通过使N型杂质注入到P-MOSFET的一部分源电极内所形成的基底电极，因而可进一步缩小面积。
对于那些普通技术人员，在阅读前述说明之后，更容易了解本文所公开的发明的其它特点、优点和实施方案。虽然对本发明的特定实施例已做了相当详细地描述，在不脱离所说明的和所请求保护的本发明的精神和范畴的前提下，可实现这些实施例的变更和改型。

Claims (8)

1.一种半导体器件，包括含有N阱和P阱及深槽元件隔离膜的P型半导体基片，所说的深槽元件隔离膜介于N阱和P阱之间以及在每个N阱和P阱内分别建立的P-MOSFETT和N-MOSFET，其特征在于：
在P-MOSFET源电极的一定部分形成的N型基底电极，且被施加VDD电压。
2.根据权利要求1的半导体器件，其中所说的深槽元件隔离膜宽约0.3～3μm，深约1.5～10μm。
3.根据权利要求1的半导体器件，其中所述的N型基底电极是与P-MOSFET的源电极相接触，但与P-MOS-FET的栅电极是分开的，并通过一导线与VDD电压相连接。
4.一种制造半导体器件的方法，包括以下各步骤：
在P型半导体基底内的预定部位形成N阱和P阱；
在N阱和P阱之间的边界形成填充以绝缘材料的深槽，所说的深槽作为所说的阱的元件隔离层；
在每个N阱和P阱上建立栅结构，所说的栅结构是栅氧化膜、栅电极和第一绝缘膜图形的叠层；
使杂质注入到N阱和P阱中，形成各自的源电极和漏电极，所说的杂质类型与待注入杂质的阱的类型相反；
在所得的结构上依次淀积第二绝缘膜和腐蚀阻止层；
在腐蚀阻止层的侧壁形成绝缘衬垫，所说的侧壁被用作所说的叠层结构；
在有光敏膜图形的情况下，使N型杂质注入到P-MOS-FET源电极的一部分内，形成N型基底电极，所说的光敏膜图形覆盖着全部结构，但所说的源电极除外，它的一部分未被绝缘衬垫覆盖；
去掉所说的光敏膜图形，在所得结构上镀一铺垫第三绝缘膜；
使用接触掩模有选择的腐蚀第三绝缘膜，形成接触孔，通过接触孔露出P阱的源电极、漏电极及基底电极；以及
形成布线图形，以此使P阱的源电极和所说的基底电极与VDD相连接，使P阱的漏电极与N阱的漏电极相连接，以及使N阱的源电极与VSS相连接。
5.根据权利要求4的方法，其中所说的光敏膜图形是通过淀积一层铺垫光敏膜并有选择地腐蚀它而形成的，以便露出P阱的源电极及与所说的源电极相邻的部分栅电极。
6.根据权利要求4的方法，其中所说的深槽宽约0.3～3μm，深约1.5～10μm。
7.根据权利要求4的方法，其中所说的深槽被填充以一种氧化膜。
8.根据权利要求4的方法，其中所说的腐蚀阻止层是由氮化膜制成的，而所说的第三绝缘膜是由硼磷硅玻璃制成的。
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