CN107452797A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN107452797A
CN107452797A CN201710286361.0A CN201710286361A CN107452797A CN 107452797 A CN107452797 A CN 107452797A CN 201710286361 A CN201710286361 A CN 201710286361A CN 107452797 A CN107452797 A CN 107452797A
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China
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pattern
capping
capping pattern
sept
semiconductor devices
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CN201710286361.0A
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CN107452797B (zh
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金润载
金哲
孙龙勋
刘真赫
郑宇陈
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本公开涉及半导体器件。一种半导体器件包括具有有源图案的衬底、交叉有源图案的导电图案、在导电图案的至少一个侧表面上的间隔物结构、以及在导电图案上的封盖结构。封盖结构包括第一封盖图案和第二封盖图案。第二封盖图案设置在第一封盖图案的顶表面和间隔物结构的顶表面上。

Description

半导体器件
技术领域
本发明构思涉及半导体器件和制造其的方法。更具体地，本发明构思涉及场效应晶体管的栅结构和制造其的方法。
背景技术
由于高性能、小尺寸和/或低制造成本特性，在电子产业中，半导体器件已经作为必不可少的器件被使用。半导体器件被分类为用于存储逻辑数据的半导体存储器件、用于处理逻辑数据的半导体逻辑器件以及包括存储元件和逻辑元件的混合半导体器件。随着电子产业高度发展，对高速、高可靠性和多功能的半导体器件的需求一直在增长。为了满足这些特性，半导体器件已经变得高度集成，并且半导体器件的内部结构已经变得高度复杂。
发明内容
根据本发明构思，提供一种半导体器件，其包括：具有有源图案的衬底；交叉有源图案的导电图案；导电图案的侧表面中的至少一个中的每一个上的各自的间隔物结构，间隔物结构具有顶表面；以及在导电图案上的封盖结构，其中封盖结构包括第一封盖图案和第二封盖图案，第一封盖图案具有顶表面，并且第二封盖图案设置在第一封盖图案的顶表面上以及间隔物结构的顶表面上。
根据本发明构思，还提供一种半导体器件，其包括具有有源图案的衬底、交叉有源图案的导电图案、以及在导电图案上的封盖结构，其中封盖结构包括第一封盖图案和在第一封盖图案上的第二封盖图案，第一封盖图案具有凹口，第二封盖图案具有当与第一封盖图案啮合时被容纳在凹口中的凸起，以及第二封盖图案的宽度大于第一封盖图案的宽度。
根据本发明构思，还提供一种制造半导体器件的方法，其包括：在衬底上形成交叉有源图案的导电图案，在导电图案的彼此相反的侧表面上形成间隔物层，在导电图案和间隔物层上形成第一封盖层，使第一封盖层和间隔物层凹陷在绝缘材料内以形成第一封盖图案和间隔物结构，以及在第一封盖图案的顶表面和间隔物结构的顶表面上形成第二封盖图案。
根据本发明构思，还提供一种半导体器件，其包括：衬底，其具有包括源极/漏极(S/D)区的有源图案；在衬底上的层间绝缘层；层间绝缘层内在交叉有源图案的第一方向上纵向地延伸的至少一个导电图案；导电图案的侧表面中的至少一个中的每一个上的各自的间隔物结构；导电图案上的封盖结构；以及接触结构，其在层间绝缘层中垂直地延伸到S/D区，其中接触结构包括电连接到S/D区的导电构件，封盖结构包括第一封盖图案和第二封盖图案，第二封盖图案具有设置在第一封盖图案的顶表面上的第一部分和在间隔物结构的顶表面上的第二部分，接触结构依靠着间隔物结构和第二封盖图案的第二部分设置，以及第二封盖图案是相对于层间绝缘层的材料具有蚀刻选择性的材料。
附图说明
图1是示出根据本发明构思一示例的半导体器件的透视图。
图2是沿图1的线A-A'截取的剖视图。
图3是示出根据本发明构思一示例的半导体器件的俯视图。
图4A、4B和4C分别是沿图3的线A-A'、B-B'和C-C'截取的剖视图。
图5是图4A的区域“M”的放大剖视图。
图6A、6B和6C是图4A的区域“N”的放大剖视图。
图7、9、11、13、15、17、19、21、23和25是示出根据本发明构思一示例的制造半导体器件的方法的俯视图。
图8A、10A、12A、14A、16A、18A、20A、22A、24A和26A分别是沿图7、9、11、13、15、17、19、21、23和25的线A-A'截取的剖视图，图8B、10B、12B、14B、16B、18B、20B、22B、24B和26B分别是沿图7、9、11、13、15、17、19、21、23和25的线B-B'截取的剖视图，图10C、12C、14C、16C、18C、20C、22C、24C和26C分别是沿图9、11、13、15、17、19、21、23和25的线C-C'截取的剖视图。
图27是示出根据本发明构思一示例的半导体器件的俯视图。
图28A和28B分别是沿图27的线A-A'和B-B'截取的剖视图。
图29是示出根据本发明构思一示例的半导体器件的俯视图。
图30A和30B分别是沿图29的线A-A'和B-B'截取的剖视图。
具体实施方式
现在将参照附图更充分地描述本发明构思的各种各样的示例。然而，本发明构思可以以许多替代的形式来实施，并且不应被解释为只限于以下描述的示例。
图1是示出根据本发明构思一示例的半导体器件的透视图。图2是沿图1的线A-A'截取的剖视图。
参照图1和2，具有有源图案AP的衬底100可以被提供。衬底100可以是例如硅衬底、锗衬底或绝缘体上硅(SOI)衬底。有源图案AP可以设置在衬底100上。有源图案AP可以从衬底100向上地凸出。有源图案AP可以包括一对源极/漏极区SD和在该对源极/漏极区SD之间的沟道区CH。源极/漏极区SD可以是用具有与衬底100不同的导电类型的杂质掺杂的杂质区。
导电图案可以设置在沟道区CH上。作为一示例，导电图案可以包括交叉有源图案AP的栅电极GE。栅电极GE可以具有在平行于衬底100的顶表面的第一方向D1上延伸的线型形状。栅电极GE可以包括掺杂的半导体材料(例如掺杂的硅、掺杂的锗等等)、导电金属氮化物(例如钛氮化物、钽氮化物等等)和/或金属(例如铝、钨等等)。
间隔物结构GS可以分别设置在栅电极GE的彼此相反的侧壁上。间隔物结构GS可以沿着栅电极GE在第一方向D1上延伸。间隔物结构GS的顶表面GSt可以高于栅电极GE的顶表面GEt。间隔物结构GS可以每个包括多个间隔物SP1、SP2和SP3。换言之，所述多个间隔物SP1、SP2和SP3可以是顺序堆叠在栅电极GE的侧壁上的多个层。所述多个间隔物SP1、SP2和SP3可以包括第一间隔物SP1、第二间隔物SP2和第三间隔物SP3。
第一至第三间隔物SP1、SP2和SP3的底表面可以基本上彼此共面，并且第一至第三间隔物SP1、SP2和SP3的顶表面可以基本上彼此共面。第二间隔物SP2可以插置在第一间隔物SP1与第三间隔物SP3之间。第二间隔物SP2的介电常数可以低于第一间隔物SP1和第三间隔物SP3的介电常数。第二间隔物SP2可以具有比第一间隔物SP1和第三间隔物SP3的每一个的宽度更大的宽度。换言之，第二间隔物SP2在间隔物结构GS中按体积计的百分比可以大于第一间隔物SP1和第三间隔物SP3的每一个在间隔物结构GS中按体积计的百分比。因为第二间隔物SP2的介电常数相对较低，所以可以形成具有相对较低的介电常数的间隔物结构GS。
第一至第三间隔物SP1、SP2和SP3可以每个包括SiO2、SiCN、SiCON和SiN中的至少一种。在一些示例中，第二间隔物SP2可以包含比第一和第三间隔物更多的氧以具有相对较低的介电常数。换言之，第二间隔物SP2中的氧原子的浓度可以大于第一间隔物SP1和第三间隔物SP3的每一个中的氧原子的浓度。作为一示例，第一间隔物SP1和第三间隔物SP3可以包括SiN，第二间隔物SP2可以包括SiCON。
栅电介质图案GI可以设置在栅电极GE与沟道区CH之间以及栅电极与该对间隔物结构GS之间。栅电介质图案GI可以在第一方向D1上延伸。栅电介质图案GI可以包括一对延伸部分GIe。延伸部分GIe可以每个沿着间隔物结构GS的内侧壁在第三方向D3上延伸。第三方向D3可以是垂直于衬底100的顶表面的方向。延伸部分GIe的顶表面可以与间隔物结构GS的顶表面GSt基本上共面。换言之，延伸部分GIe的顶表面可以高于栅电极GE的顶表面GEt。
栅电介质图案GI可以包括硅氧化物、硅氮化物和高k电介质材料中的至少一种，该高k电介质材料具有比硅氧化物的介电常数更大的介电常数。高k电介质材料可以例如包括铪氧化物、铪硅氧化物、镧氧化物、锆氧化物、锆硅氧化物、钽氧化物、钛氧化物、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、锂氧化物、铝氧化物、铅钪钽氧化物和铌锌酸铅中的至少一种。
栅电极GE可以是凹入的，即它的顶表面GEt可以低于间隔物结构GS的顶表面GSt和栅电介质图案GI的顶表面。因此，第一凹陷区RC1可以被定义在栅电极GE上。具体地，第一凹陷区RC1可以包括由延伸部分GIe的内侧壁和栅电极GE的顶表面Get界定的凹陷。
封盖结构GP可以设置在栅电极GE上。封盖结构GP可以沿着栅电极GE在第一方向D1上延伸。作为一示例，封盖结构GP在交叉第一方向D1的第二方向D2上的剖面可以具有T形状(参照图2)。封盖结构GP可以包括顺序堆叠的第一封盖图案CP1和第二封盖图案CP2。
第一封盖图案CP1可以设置在栅电极GE的顶表面GEt上。第一封盖图案CP1可以插置在栅电极GE与第二封盖图案CP2之间。此外，第一封盖图案CP1可以插置在间隔物结构GS之间。第一封盖图案CP1可以设置在第一凹陷区RC1中。换言之，第一封盖图案CP1可以由栅电极GE、第二封盖图案CP2和该对间隔物结构GS围绕。第一封盖图案CP1的顶表面CP1t的至少一部分可以与间隔物结构GS的顶表面GSt基本上共面。换言之，第一封盖图案CP1的顶表面CP1t的至少一部分可以设置在与间隔物结构GS的顶表面GSt基本相同的高度处。
第一封盖图案CP1可以具有在第二方向D2上的宽度W1。例如，第一封盖图案CP1的宽度W1可以基本上等于栅电极GE在第二方向上的宽度。
第一封盖图案CP1可以包括形成在其顶表面中的凹口DE。凹口DE可以成在第一方向D1上纵向地延伸的槽的形式。凹口DE可以具有在第二方向D2上的宽度W3。宽度W3可以小于第一封盖图案CP1的宽度W1。
第二封盖图案CP2可以设置在第一封盖图案CP1的顶表面CP1t和间隔物结构GS的顶表面GSt上。换言之，第二封盖图案CP2可以覆盖第一封盖图案CP1的整个顶表面CP1t和间隔物结构GS的整个顶表面GSt。第二封盖图案CP2可以从第一封盖图案CP1的顶表面CP1t延伸到间隔物结构GS的顶表面GSt。第二封盖图案CP2的彼此相反的侧壁可以每一个与每个间隔物结构GS的侧壁对准。每个间隔物结构GS的侧壁可以是第三间隔物SP3的侧壁。第二封盖图案CP2的彼此相反的侧壁和每个间隔物结构GS的侧壁可以由层间绝缘层130覆盖。第二封盖图案CP2的顶表面CP2t可以与覆盖衬底100的第一层间绝缘层130的顶表面基本上共面。
第二封盖图案CP2可以具有在第二方向D2上的宽度W2。第二封盖图案CP2的宽度W2可以大于第一封盖图案CP1的宽度W1。
第二封盖图案CP2可以在其底表面包括朝衬底100凸出的凸起部分PP(或简称为“凸起”)。凸起部分PP可以具有在第一方向D1上延伸的线型形状。凸起部分PP可以与凹口DE互补并且可以被容纳在凹口DE中。
第二封盖图案CP2可以包括相对于第一层间绝缘层130具有蚀刻选择性的材料。例如，在将碳氟化合物(CxFy)用作蚀刻气体的干法蚀刻工艺中，第二封盖图案CP2可以包括相对于第一层间绝缘层130具有蚀刻选择性的材料。在一些示例中，在第一层间绝缘层130可以包括硅氧化物的情况下，第二封盖图案CP2可以包括SiON、SiCN、SiCON、SiN和Al2O3中的至少一种。
在一些示例中，第一封盖图案CP1可以包括与第二封盖图案CP2相同的材料。在另外的示例中，第一封盖图案CP1可以包括与第二封盖图案CP2不同的材料。在这样的情况下，第二封盖图案CP2的介电常数可以大于第一封盖图案CP1的介电常数。通常在具有相对较高的介电常数的材料的情况下，该材料相对于形成第一层间绝缘层130的硅氧化物的蚀刻选择性可以更高。第一封盖图案CP1可以包括SiON、SiCN、SiCON、SiN和Al2O3中的至少一种。作为一示例，第一封盖图案CP1和第二封盖图案CP2可以包括SiN。作为另一示例，第一封盖图案CP1可以包括SiON，第二封盖图案CP2可以包括SiN。作为又一示例，第一封盖图案CP1可以包括SiN，第二封盖图案CP2可以包括Al2O3。
图3是示出根据本发明构思一示例的半导体器件的俯视图。图4A、4B和4C分别是沿图3的线A-A'、B-B'和C-C'截取的剖视图。图5是图4A的区域“M”的放大的剖视图。图6A、6B和6C是图4A的区域“N”的放大的剖视图。在下文中，为了简洁与参照图1和2描述的相同的元件将不再被描述或者将只被简略地提及。
参照图3、4A至4C、5和6A，衬底100可以被提供。例如，衬底100可以是硅衬底、锗衬底或绝缘体上硅(SOI)衬底。第一晶体管TR1和第二晶体管TR2可以设置在衬底100上。第一晶体管TR1和第二晶体管TR2可以被提供在衬底100的区域上。
在一些示例中，衬底100的该区域可以是其中设置用于存储数据的多个存储单元的存储单元区。作为一示例，构造多个SRAM单元的存储单元晶体管可以设置在衬底100的存储单元区中。第一晶体管TR1和第二晶体管TR2可以构成存储单元晶体管中的两个，即可以是存储单元晶体管的代表。
在另外的示例中，衬底100的该区域可以是其中设置构造半导体器件的逻辑电路的逻辑晶体管的逻辑单元区。作为一示例，构造处理器核或I/O端子的逻辑晶体管可以设置在逻辑单元区中。第一晶体管TR1和第二晶体管TR2可以组成逻辑晶体管中的两个，即可以是逻辑晶体管的代表。然而，本发明构思的方面不限于此。
第一晶体管TR1和第二晶体管TR2可以是不同导电类型的晶体管。例如，第一晶体管TR1可以是PMOSFET，第二晶体管TR2可以是NMOSFET。
衬底100可以在其顶部包括第一有源图案AP1和第二有源图案AP2。第一有源图案AP1可以是用于第一晶体管TR1的有源图案，第二有源图案AP2可以是用于第二晶体管TR2的有源图案。
第一有源图案AP1和第二有源图案AP2可以在第二方向D2上彼此平行地延伸。第一有源图案AP1和第二有源图案AP2可以彼此间隔开，其间具有第二器件隔离图案ST2。第一器件隔离图案ST1可以设置在第一有源图案AP1的彼此相反的侧，并且可以限定第一有源图案AP1。另外，第一器件隔离图案ST1可以设置在第二有源图案AP2的彼此相反的侧，并且可以限定第二有源图案AP2。
虽然未示出，但第一有源图案AP1可以包括彼此相邻的多个第一有源区，第二有源图案AP2可以包括彼此相邻的多个第二有源区。在这样的情况下，第一器件隔离图案ST1可以插置在相邻的第一有源区之间以及相邻的第二有源区之间。
第一器件隔离图案ST1和第二器件隔离图案ST2可以是连接到彼此的绝缘层以成为绝缘材料的基本上一体的结构。第二器件隔离图案ST2可以具有比第一器件隔离图案ST1的厚度更大的厚度。在这样的情况下，第一器件隔离图案ST1可以通过与形成第二器件隔离图案ST2的工艺分开的工艺形成。在一些示例中，第一器件隔离图案ST1和第二器件隔离图案ST2可以同时地形成并且基本具有相同的厚度。第一器件隔离图案ST1和第二器件隔离图案ST2可以形成在衬底100的上部部分中。例如，第一器件隔离图案ST1和第二器件隔离图案ST2可以由硅氧化物层组成。
栅电极GE可以设置在第一有源图案AP1和第二有源图案AP2上并且交叉第一有源图案AP1和第二有源图案AP2。栅电极GE可以在第一方向D1上延伸以横越第一器件隔离图案ST1和第二器件隔离图案ST2。栅电极GE可以在第二方向D2上彼此间隔开。
界面层IL可以分别插置在第一有源图案AP1和第二有源图案AP2与栅电极GE之间。界面层IL可以分别覆盖第一有源图案AP1和第二有源图案AP2的上部部分(例如稍后将描述的沟道区CH的顶表面和侧壁)。界面层IL可以包括硅氧化物层。
再参照图6A，栅电介质图案GI可以插置在栅电极GE与界面层IL之间。间隔物结构GS可以分别设置在栅电极GE的彼此相反的侧表面上。封盖结构GP可以设置在栅电极GE上。间隔物结构GS可以每一个包括第一至第三间隔物SP1、SP2和SP3。封盖结构GP可以包括顺序堆叠的第一封盖图案CP1和第二封盖图案CP2。栅电极GE、栅电介质图案GI、间隔物结构GS和封盖图案GP可以与参照图1和2描述的那些相似。
再参照图3和图4A至4C，第一有源图案AP1和第二有源图案AP2可以包括分别设置在第一有源图案AP1和第二有源图案AP2的上部部分的源极/漏极区SD和沟道区CH。具体地，源极/漏极区SD可以设置在栅电极GE的彼此相反的侧。作为一示例，第一有源图案AP1的源极/漏极区SD可以具有p型导电性，第二有源图案AP2的源极/漏极区SD可以具有n型导电性。
沟道区CH可以设置在源极/漏极区SD的相应源极/漏极区之间。沟道区CH可以与栅电极GE垂直重叠。虽然如图1中所示的栅电极GE覆盖沟道区CH的顶表面，但根据本发明构思的示例的栅电极GE中的每一个可以覆盖沟道区CH的顶表面和侧壁。
源极/漏极区SD可以包括外延图案，所述外延图案利用源极/漏极区SD下方的第一有源图案AP1和第二有源图案AP2作为籽晶而被生长。在这样的情况下，第一有源图案AP1的源极/漏极区SD可以包括将压缩应变施加于沟道区CH的材料。第二有源图案AP2的源极/漏极区SD可以包括将拉伸应变施加于沟道区CH的材料。例如，在衬底100是硅衬底的情况下，第一有源图案AP1的源极/漏极区SD可以包括其晶格常数大于Si的晶格常数的SiGe。第二有源图案AP2的源极/漏极区SD可以包括其晶格常数小于Si的晶格常数的SiC，或者可以包括其晶格常数基本上等于衬底100的晶格常数的Si。当在横截面中观察时，参照图4C，第一有源图案AP1的源极/漏极区SD可以具有不同于第二有源图案AP2的源极/漏极区SD的形状。这可以是因为第一有源图案AP1的源极/漏极区SD和第二有源图案AP2的源极/漏极区SD使用不同的物质来被外延生长。
第一层间绝缘层130可以设置在衬底100上并且填充栅电极GE之间的间隙。第一层间绝缘层130的顶表面可以与封盖结构GP的顶表面共面。第二层间绝缘层140可以设置在第一绝缘层130上。第一层间绝缘层130和第二层间绝缘层140可以包括硅氧化物层。
电连接到源极/漏极区SD中的至少一个的有源接触(其也可称为“接触结构”)CA可以被提供。有源接触CA可以穿过第二层间绝缘层140和第一层间绝缘层130，并且电连接到源极/漏极区SD。有源接触CA可以设置在栅电极GE中的至少一个的一侧或彼此相反的侧。有源接触CA可以每一个包括导电结构185和围绕导电结构185的阻挡图案180。阻挡图案180可以包括阻挡导电层，阻挡导电层例如包括钛氮化物、钨氮化物和钽氮化物中的至少一种。导电结构185可以包括含例如钨、钛和钽中的至少一种的金属层。
将参照图4A和5更详细地描述与有源接触CA接触的封盖结构GP。在本发明构思的一示例中，有源接触CA可以是自对准接触(SAC)。有源接触CA可以设置在栅电极GE中的相邻栅电极之间。有源接触CA可以接触相邻栅电极GE中的至少一个上的封盖结构GP。
与不接触有源接触CA的另外的封盖结构GP相比，接触有源接触CA的封盖结构GP可以处于封盖结构GP的一部分被去除的状态。具体地，接触有源接触CA的封盖图案GP可以是凹入的。换言之，第二封盖图案CP2可以具有接触有源接触CA的倾斜的侧壁ER。
因为第二封盖图案CP2的一部分由于有源接触CA而缺失，所以第二封盖图案CP2的宽度可以在其高度的方向上变化。更具体地，在远离衬底100的方向上(例如在第三方向D3上)第二封盖图案CP2的宽度可以逐渐减小。换言之，第二封盖图案CP2的下部部分(例如宽度W2a)可以比第二封盖图案CP2的上部部分(例如宽度W2b)更宽(在图4A中的方向D2上)。
接触有源接触CA的间隔物结构GS的上部部分可以由于有源接触CA而凹入。在这方面，间隔物结构GS的上部部分可以具有倾斜的侧壁ERa。第二封盖图案CP2的倾斜的侧壁ER可以直接从间隔物结构GS的倾斜的侧壁ERa延伸，即与间隔物结构GS的倾斜的侧壁ERa相接，以形成连续倾斜或弯曲的侧壁ER和ERa。有源接触CA可以沿着倾斜的侧壁ER和ERa向下延伸并且直接覆盖间隔物结构GS的侧壁。
例如，第二封盖图案CP2的设置在间隔物结构GS顶上的部分可以具有与有源接触CA接触的凸表面。间隔物结构GS(即第三间隔物SP3)也可以具有与有源接触CA接触的凸表面。第二封盖图案CP2的凸表面在与有源接触CA相邻的位置与间隔物结构GS的凸表面(即第三间隔物SP3的凸表面)相接。邻近此位置(凸表面在此相接)，第二封盖图案CP2的凸表面的曲率半径可以与间隔物结构GS的凸表面的曲率半径(即第三间隔物SP3的凸表面的曲率半径)基本相同。换言之，在第二封盖图案CP2和间隔物结构GS的弯曲的侧表面相接的位置处，可以存在一个表面到另一个表面的平滑的过渡，即可以基本上没有拐点。
在形成有源接触CA的同时，第一至第三间隔物SP1、SP2和SP3可以被第二封盖图案CP2保护。因为第二间隔物SP2具有相对较低的介电常数，所以可以发生在栅电极GE与有源接触CA之间的寄生电容可以被减小。
第二封盖图案CP2可以通过第一封盖图案CP1和间隔物结构GS与栅电极GE垂直地间隔开。因此，即使第二封盖图案CP2具有相对较高的介电常数，但它可以不影响出现在栅电极GE与有源接触CA之间的寄生电容。
现在将参照图4A、6B和6C描述根据本发明构思的半导体器件的另外的示例的封盖结构GP。
作为本发明构思的一示例，首先，参照图4A和6B，绝缘图案NO可以插置在第一封盖图案CP1与第二封盖图案CP2之间。绝缘图案NO可以包括形成在第一封盖图案CP1和间隔物结构GS上的自然氧化物。因此，绝缘图案NO可以直接覆盖第一封盖图案CP1的顶表面CP1t和间隔物结构GS的顶表面GSt。
作为一示例，在第一封盖图案CP1包括SiN的情况下，绝缘图案NO可以包括形成在SiN层上的硅氧化物层(即自然氧化物层)。然而，自然氧化物层不限于硅氧化物层。自然氧化物层的材料取决于由其形成第一封盖图案CP1和间隔物结构GS的材料。例如，在第一封盖图案CP1包括Al2O3的情况下，绝缘图案NO可以包括形成在Al2O3层上的作为自然氧化物层的铝氧化物层。
作为本发明构思的另一示例，参照图4A和6C，第一封盖图案可以具有基本上平坦的顶表面CP1t。换言之，不同于如参照图1和2描述的第一封盖图案CP1和第二封盖图案CP2，根据此示例的第一封盖图案CP1可以不包括凹口DE，并且第二封盖图案CP2也可以不包括凸起部分PP。第一封盖图案CP1的顶表面CP1t可以与间隔物结构GS的顶表面GSt基本上共面。
图7、9、11、13、15、17、19、21、23和25是示出根据本发明构思一示例的制造半导体器件的方法的俯视图。图8A、10A、12A、14A、16A、18A、20A、22A、24A和26A分别是沿图7、9、11、13、15、17、19、21、23和25的线A-A'截取的剖视图，图8B、10B、12B、14B、16B、18B、20B、22B、24B和26B分别是沿图7、9、11、13、15、17、19、21、23和25的线B-B'截取的剖视图，图10C、12C、14C、16C、18C、20C、22C、24C和26C分别是沿图9、11、13、15、17、19、21、23和25的线C-C'截取的剖视图。
参照图7、8A和8B，第一有源图案AP1和第二有源图案AP2可以形成在衬底100的一区域中。例如，衬底100可以是硅衬底、锗衬底或绝缘体上硅(SOI)衬底。在一些示例中，衬底100的该区域可以是其中设置用于存储数据的多个存储单元的存储单元区。在另外的示例中，衬底100的该区域可以是其中设置用于形成逻辑电路的多个逻辑晶体管的逻辑单元区。
具体地，限定第一有源图案AP1和第二有源图案AP2的第一沟槽TC1可以通过图案化衬底100的上部部分形成。第一有源图案AP1和第二有源图案AP2可以在第一方向D1上彼此间隔开。第一有源图案AP1和第二有源图案AP2可以具有在第二方向D2上延伸的线型形状。第一器件隔离图案ST1可以被形成以填充第一沟槽TC1。第一器件隔离图案ST1可以形成为暴露第一有源图案AP1和第二有源图案AP2的上部部分。换言之，第一有源图案AP1和第二有源图案AP2的上部部分可以垂直地(例如在第三方向D3上)凸出在第一器件隔离图案ST1之上。
接着，衬底的上部部分可以再次被图案化以形成第二沟槽TC2。第二沟槽TC2中的至少一个可以形成在第一有源图案AP1与第二有源图案AP2之间。当形成第二沟槽TC2时，第一器件隔离图案ST1的一部分可以被去除。第二沟槽TC2的底表面可以低于第一沟槽TC1的底表面。第二器件隔离图案ST2可以被形成以填充第二沟槽TC2。
作为一示例，第一器件隔离图案ST1和第二器件隔离图案ST2可以一起形成绝缘材料的基本上一个整体或单一层的结构。第一器件隔离图案ST1和第二器件隔离图案ST2可以由硅氧化物形成。
参照图9、10A至10C，牺牲栅图案110和各牺牲栅图案110上的栅掩模图案115可以形成在衬底100上。牺牲栅图案110可以形成为交叉第一有源图案AP1和第二有源图案AP2并且在第一方向D1上延伸。牺牲栅图案110可以覆盖第一有源图案AP1和第二有源图案AP2的顶表面和侧壁。此外，牺牲栅图案110可以覆盖第一器件隔离图案ST1和第二器件隔离图案ST2的顶表面的一部分。
牺牲栅图案110和栅掩模图案115的形成可以包括在衬底100上顺序地形成牺牲栅层和栅掩模层以覆盖第一有源图案AP1和第二有源图案AP2、以及顺序地图案化牺牲栅层和栅掩模层。牺牲栅层可以包括多晶硅。栅掩模层可以包括硅氮化物或硅氮氧化物。
参照图11和12A至12C，一对间隔物结构GS可以被形成以覆盖牺牲栅图案110的每一个的彼此相反的侧壁。源极/漏极区SD可以形成在第一有源图案AP1和第二有源图案AP2的上部部分上。源极/漏极区SD可以设置在每一个牺牲栅图案110的彼此相反的侧。沟道区CH可以每一个设置在源极/漏极区SD中的相应源极/漏极区之间。
具体地，间隔物结构GS的形成可以包括在衬底100上形成栅间隔物层以共形地覆盖牺牲栅图案110和栅掩模图案115、以及各向异性地蚀刻栅间隔物层。栅间隔物层可以通过化学气相沉积(CVD)工艺或原子层沉积(ALD)工艺形成。栅间隔物层可以包括顺序堆叠的多个层，即可以是多层结构。在这方面，栅间隔物层可以由SiO2、SiCN、SiCON和SiN中的至少一种形成。
所得的间隔物结构GS可以包括第一间隔物SP1、第二间隔物SP2和第三间隔物SP3(参照图6A)。在这样的情况下，第二间隔物SP2可以由比第一间隔物SP1和第三间隔物SP3的材料具有更低的介电常数的材料形成。在一些示例中，第三间隔物SP3可以在形成第一间隔物SP1和第二间隔物SP2以及源极/漏极区SD之后形成。在另外的示例中，第一至第三间隔物SP1、SP2和SP3可以同时形成。
具体地，源极/漏极区SD的形成可以包括去除各牺牲栅图案110的彼此相反的侧处的第一有源图案AP1和第二有源图案AP2的上部部分、以及利用第一有源图案AP1和第二有源图案AP2的通过所述去除而暴露的部分作为籽晶来进行选择性外延生长工艺。第一有源图案AP1和第二有源图案AP2的上部部分的所述去除可以通过将栅掩模图案115和间隔物结构GS用作蚀刻掩模的湿法蚀刻工艺来进行。
第一有源图案AP1的源极/漏极区SD可以被形成为将压缩应变施加于其间的沟道区CH。作为一示例，在衬底100是硅衬底的情况下，第一有源图案AP1的源极/漏极区SD可以由SiGe形成。在外延生长工艺之后或在外延生长工艺期间，第一有源图案AP1的源极/漏极区SD可以用p型杂质掺杂。
第二有源图案AP2的源极/漏极区SD可以被形成为将拉伸应变施加于其间的沟道区CH。作为一示例，在衬底100是硅衬底的情况下，第二有源图案AP2的源极/漏极区SD可以由SiC或Si形成。在外延生长工艺之后或在外延生长工艺期间，第二有源图案AP2的源极/漏极区SD可以用n型杂质掺杂。
在一些示例中，因为第一有源图案AP1的源极/漏极区SD和第二有源图案AP2的源极/漏极区SD使用彼此不同的材料外延生长，所以第一有源图案AP1的源极/漏极区SD和第二有源图案AP2的源极/漏极区SD可以被形成为具有彼此不同的尺寸和彼此不同的形状。
参照图13和14A至14C，第一层间绝缘层130可以形成在衬底100上。例如，第一层间绝缘层130可以由硅氧化物形成。平坦化工艺可以对第一层间绝缘层130执行直到牺牲栅图案110的顶表面被暴露。平坦化工艺可以包括回蚀刻工艺和/或化学机械抛光(CMP)工艺。当平坦化第一层间绝缘层130时，栅掩模图案115可以被一起去除以暴露牺牲栅图案110。
暴露的牺牲栅图案110可以被去除使得栅沟槽GT可以形成为每一个暴露间隔物结构GS中的相邻间隔物结构之间的沟道区CH。栅沟槽GT可以通过执行选择性地去除牺牲栅图案110的蚀刻工艺来形成。
参照图15和16A至16C，氧化工艺可以利用等离子体对暴露的沟道区CH执行，使得界面层IL可以分别从沟道区CH生长。界面层IL可以是沟道区CH的热氧化和/或化学氧化的结果。氧化工艺可以使用例如氧气(O2)、臭氧(O3)和水蒸气(H2O)中的至少一种的氧化剂来实施。界面层IL可以包括硅氧化物层。
栅电介质图案GI和栅电极GE可以顺序形成在栅沟槽GT的每一个中以填充栅沟槽GT的每一个。具体地，栅电介质层可以形成在栅沟槽GT中以填充栅沟槽GT中的每一个的一部分。栅电介质层可以形成为覆盖沟道区CH的顶表面和侧壁。作为一示例，栅电介质层可以包括硅氧化物、硅氮氧化物和高k电介质材料中的至少一种，该高k电介质材料的介电常数高于硅氧化物的介电常数。
栅导电层可以形成在栅电介质层上以填充栅沟槽GT的剩余部分。例如，栅导电层可以包括掺杂半导体材料、导电金属氮化物和金属中的至少一种。顺序堆叠的栅电介质层和栅导电层可以被平坦化使得栅电介质图案GI和栅电极GE可以形成在每个栅沟槽GT中。
栅电极GE可以凹入使得第一凹陷区RC1可以被定义在各栅电极GE上。换言之，栅电极GE的顶表面可以低于间隔物结构GS的顶表面和栅电介质图案GI的顶表面。第一凹陷区RC1中的每一个可以具有由栅电介质图案GI的内侧壁和栅电极GE的顶表面限定的凹陷。栅电极GE的所述凹入可以包括选择性地蚀刻栅电极GE以去除其一部分。
参照图17和18A至18C，第一封盖层150可以形成在第一层间绝缘层130上。第一封盖层150可以填充第一凹陷区RC1的凹陷。由于第一凹陷区RC1，下陷区域DEa可以形成在第一封盖层150的顶表面中。第一封盖层150可以由SiON、SiCN、SiCON、SiN和Al2O3中的至少一种形成。
参照图19和20A至20C，第一封盖层150可以被蚀刻以形成栅电极GE上的第一封盖图案CP1。第一封盖图案CP1可以分别填充第一凹陷区RC1的凹陷。
第一封盖层150可以被蚀刻使得第一封盖图案CP1的顶表面低于第一层间绝缘层130的顶表面。当蚀刻第一封盖层150时，间隔物结构GS和栅电介质图案GI可以被一起蚀刻。因此，间隔物结构GS的顶表面和栅电介质图案GI的顶表面可以低于第一层间绝缘层130的顶表面。作为一示例，第一封盖图案CP1的顶表面的一部分可以与间隔物结构GS的顶表面基本上共面。
由于形成在第一封盖层150的顶表面中的下陷区域DEa，凹口DE可以分别形成在第一封盖图案CP1的顶表面中。归因于形成第一封盖图案CP1的对第一封盖层150的各向异性干蚀刻，凹口DE可以被形成。
在一些示例中，在蚀刻工艺在平坦化第一封盖层150之后执行的情况下，第一封盖层150的顶表面中的下陷区域DEa可以被去除。在这样的情况下，第一封盖图案CP1可以具有基本上平坦的顶表面而没有凹口DE(参照图6C)。
通过执行蚀刻工艺，间隔物结构GS的顶表面、栅电介质图案GI的顶表面和第一封盖图案CP1的顶表面可以低于第一层间绝缘层130的顶表面，使得第二凹陷区RC2可以形成。第二凹陷区RC2的凹陷可以每个暴露该对间隔物结构GS的顶表面、栅电介质图案GI的顶表面和第一封盖图案CP1的顶表面。
在一些示例中，绝缘图案NO可以形成在间隔物结构GS的暴露的顶表面、栅电介质图案GI的暴露的顶表面和第一封盖图案CP1的暴露的顶表面上。绝缘图案NO可以包括通过被暴露的层与空气的接触而自然形成的自然氧化物(参照图6B)。
参照图21和22A至22C，第二封盖层160可以形成在第一层间绝缘层130上。第二封盖层160可以填充第二凹陷区RC2。第二封盖层160可以由相对于第一层间绝缘层130具有蚀刻选择性的材料形成。第二封盖层可以由例如SiON、SiCN、SiCON、SiN和Al2O3中的至少一种形成。在一些示例中，第二封盖层160可以由与第一封盖图案CP1相同的材料形成。在另外的示例中，第二封盖层160可以由与第一封盖图案CP1的材料不同的材料形成。在这样的情况下，第二封盖层160的介电常数可以大于第一封盖图案CP1的介电常数。
参照图23和24A至24C，第二封盖层160的平坦化工艺可以被执行直到第一层间绝缘层130的顶表面被暴露。因此，第二封盖图案CP2可以形成在第二凹陷区RC2的各凹陷中。平坦化工艺可以包括回蚀刻工艺和/或CMP工艺。第一封盖图案CP1和第二封盖图案CP2可以形成封盖结构GP。第二封盖图案CP2可以被形成为完全覆盖第一封盖图案CP1的顶表面和该对间隔物结构GS的顶表面。换言之，第二封盖图案CP2可以形成为比第一封盖图案CP1具有更大的宽度。第二封盖图案CP2可以与栅电极GE间隔开，第一封盖图案CP1在其间。
参照图25和26A至26C，第二层间绝缘层140可以形成在第一层间绝缘层130上，第二层间绝缘层140可以由例如硅氧化物形成。
接触孔CAH可以形成在栅电极GE中的至少一个的一侧或彼此相反的侧。具体地，光致抗蚀剂图案PR可以形成在第二层间绝缘层140上。光致抗蚀剂图案PR可以包括定义接触孔CAH的位置的开口。开口可以每个与源极/漏极区SD垂直地重叠或对准。当在俯视图中观察时，开口可以每个被形成为具有比源极/漏极区SD的面积更大的面积。第一层间绝缘层130和第二层间绝缘层140可以利用光致抗蚀剂图案PR作为蚀刻掩模来被蚀刻，以形成暴露源极/漏极区SD的接触孔CAH。
用于形成接触孔CAH的蚀刻工艺可以包括能够选择性地蚀刻第一层间绝缘层130和第二层间绝缘层140的干法蚀刻工艺。例如，该蚀刻工艺可以利用碳氟化合物(CxFy)作为蚀刻气体来被执行。
光致抗蚀剂图案PR的开口可以每个被形成为具有比相邻栅电极GE之间的距离更大的宽度(参照图26A)。在执行蚀刻工艺的同时，封盖结构GP的一部分和间隔物结构GS的一部分可以被蚀刻，而封盖结构GP和间隔物结构GS的其它部分保持完好。因此，接触孔CAH可以选择性地暴露源极/漏极区SD，而不暴露与其相邻的栅电极GE。就是说，接触孔CAH可以以自对准的方式形成。由于封盖结构GP的一部分被蚀刻，因此封盖结构GP可以具有倾斜的侧壁ER。
间隔物结构GS可以包括低k电介质材料(例如第二间隔物SP2的材料)以减小栅电极GE与稍后描述的有源接触CA之间的寄生电容。然而，间隔物结构GS的归因于低k电介质材料的耐蚀刻性可以相对较低，因而在用于形成接触孔CAH的蚀刻工艺期间间隔物结构GS可以被容易地蚀刻。
因为第二封盖图案CP2被形成为完全覆盖间隔物结构GS的顶表面，所以间隔物结构GS在用于形成接触孔CAH的蚀刻工艺期间可以被有效地保护。例如，第二封盖图案CP2可以由相对于硅氧化物层具有高蚀刻选择性的高k电介质材料(例如Al2O3)形成。因此，第二封盖图案CP2相对于蚀刻工艺的耐蚀刻性可以相对较高。第二封盖图案CP2通过第一封盖图案CP1和间隔物结构GS与栅电极GE间隔开，从而具有高k电介质材料的第二封盖图案CP2可以不影响寄生电容。在一些示例中，第二封盖图案CP2可以具有与第一封盖图案CP1相同的材料(例如SiN)。然而，因为第二封盖图案CP2相比第一封盖图案CP1具有更大的体积，所以第二封盖图案CP2的耐蚀刻性可以凭借其物理结构而相对较高。
再参照图3和4A至4C，有源接触CA可以被形成以填充接触孔CAH。有源接触CA可以每个包括阻挡图案180和导电结构185。阻挡图案180可以包括由例如钛氮化物、钨氮化物和钽氮化物中的至少一种形成的阻挡导电层。导电结构185可以包括由例如钨、钛和钽中的至少一种形成的金属层。
虽然未示出，但通过后续工艺，互连层可以形成在第二层间绝缘层140上以接触有源接触CA。互连层可以包括导电材料。
图27是示出根据本发明构思一示例的半导体器件的俯视图。图28A和28B分别是沿图27的线A-A'和B-B'截取的剖视图。在下文中，为了简洁，与参照图3、4A至4C和6A至6C描述的相同的元件将不再被描述或者将只简略地被提及。
参照图27以及28A和28B，第一晶体管TR1和第二晶体管TR2可以设置在衬底100上。第一有源图案AP1和第二有源图案AP2可以设置在衬底100上。第一有源图案AP1和第二有源图案AP2可以分别是用于第一晶体管TR1和第二晶体管TR2的有源区。
栅电极GE可以设置在第一有源图案AP1和第二有源图案AP2上以交叉第一有源图案AP1和第二有源图案AP2。栅电介质图案GI可以沿着栅电极GE的每一个的侧壁和底表面延伸。间隔物结构GS可以与栅电极GE中的每一个间隔开，且栅电介质图案GI插置在其间。封盖结构GP可以设置在栅电极GE中的每一个上。栅电介质图案GI的顶表面和栅电极GE中的每一个的顶表面可以接触封盖结构GP的底表面。栅电极GE、栅电介质图案GI、间隔物结构GS和封盖结构GP可以与参照图3、4A至4C、5以及6A至6C描述的那些相似。
第一有源图案AP1和第二有源图案AP2可以每个包括源极/漏极区SD和沟道区CH。沟道区CH可以每个包括垂直堆叠的多个半导体图案NS。半导体图案NS可以在第三方向D3上彼此间隔开。源极/漏极区SD可以直接接触半导体图案NS的侧壁。换言之，半导体图案NS可以连接在其彼此相反的侧的源极/漏极区。再参照图28A，虽然三个半导体图案NS被示出，但本发明构思不具体地限于半导体图案NS的任何特定数量。在一些示例中，半导体图案NS可以包括例如Si、SiGe和Ge中的至少一种。半导体图案NS可以具有彼此相等的厚度，但本发明构思不限于此。
如上所述，栅电极GE和栅电介质图案GI可以覆盖沟道区CH并且可以在第一方向D1上延伸。更具体地，栅电极GE和栅电介质图案GI可以填充半导体图案NS之间的空间。在此示例中，栅电介质图案GI可以接触半导体图案NS。栅电极GE可以与半导体图案NS间隔开，且栅电介质图案GI插置在其间。
如参照图3和4A至4C描述的第一晶体管TR1和第二晶体管TR2可以每个是三栅型场效应晶体管(即FinFET)。栅电极GE可以围绕每个半导体图案NS的外周表面。第一晶体管TR1和第二晶体管TR2可以每个是包括沟道区CH的栅全围绕型场效应晶体管，沟道区的外周表面中的每一个被栅电极GE围绕。
阻挡绝缘图案BP可以被提供在源极/漏极区SD与栅电极GE之间。阻挡绝缘图案BP可以彼此间隔开，其间具有半导体图案NS。阻挡绝缘图案BP可以接触栅电介质图案GI。阻挡绝缘图案BP可以包括硅氧化物、硅氮化物和硅氮氧化物中的至少一种。
源极/漏极区SD可以包括利用半导体图案NS和衬底100作为籽晶来形成的外延图案。在第一晶体管TR1是PMOSFET的情况下，第一有源图案AP1的源极/漏极区SD可以包括将压缩应变施加于沟道区CH的半导体材料。在第二晶体管TR2是NMOSFET的情况下，第二有源图案AP2的源极/漏极区SD可以包括将拉伸应变施加于沟道区CH的半导体材料。
第一层间绝缘层130和第二层间绝缘层140可以设置在衬底100上以覆盖栅电极GE。有源接触CA可以形成为穿透第一层间绝缘层130和第二层间绝缘层140，并且电连接到源极/漏极区SD。有源接触CA中的至少一个可以是自对准接触。有源接触CA可以接触封盖结构GP。封盖结构GP可以具有接触有源接触CA的倾斜的侧壁ER。
图29是示出根据本发明构思一示例的半导体器件的俯视图。图30A和30B分别是沿图29的线A-A'和B-B'截取的剖视图。在下文中，为了简洁，如参照图1和2描述的相同的元件将不再被描述或者将只简略地被提及。
参照图29、30A和30B，界定有源图案AP的器件隔离图案ST可以被提供在衬底100上。器件隔离图案ST可以包括例如硅氧化物层。在俯视图中，有源图案AP可以每个被伸长(“条形的”)，其主轴取向在第三方向D3上。第三方向D3可以与彼此交叉的第一方向D1和第二方向D2交叉。第一方向D1、第二方向D2和第三方向D3可以每个是平行于衬底100的顶表面的方向。第四方向D4可以是垂直于衬底100的顶表面以及第一方向D1、第二方向D2和第三方向D3的方向。
栅线GL可以设置在衬底100中以交叉有源图案AP。栅线GL可以在第二方向D2上延伸并且沿第一方向D1间隔开。栅线GL可以被掩埋在衬底100内。栅线GL可以包括导电材料，例如掺杂半导体材料(例如掺杂的硅、掺杂的锗)、导电金属氮化物(例如钛氮化物、钽氮化物)、金属(例如钨、钛、钽)和金属-半导体化合物(例如钨硅化物、钴硅化物、钛硅化物)中的至少一种。
栅电介质图案104可以插置在栅线GL与有源图案AP之间以及栅线GL与器件隔离图案ST之间。栅电介质图案104可以包括例如硅氧化物层、硅氮化物层和/或硅氮氧化物层。
掩模图案108可以分别被提供在栅线GL的顶表面上。掩模图案108的顶表面可以与衬底100的顶表面基本上共面。掩模图案108可以包括例如硅氧化物层、硅氮化物层和/或硅氮氧化物层。
第一杂质区SD1以及彼此间隔开且第一杂质区SD1插置在其间的第二杂质区SD2可以被提供在每个有源图案AP中。第一杂质区SD1可以设置在有源图案AP中于相应的一对栅线GL中的相邻栅线之间。第二杂质区SD2可以分别设置在有源图案AP中于该对栅线GL的彼此相反的侧处。就是说，第二杂质区SD2可以彼此间隔开，其间具有该对栅线GL。第一杂质区SD1可以比第二杂质区SD2更深地延伸到有源图案AP中。第一杂质区SD1可以包括与第二杂质区SD2相同导电类型的杂质。
导电图案可以设置为交叉第一有源图案AP的第一杂质区SD1。导电图案可以包括位线BL。位线BL可以在第一方向D1上延伸并且在第二方向D2上排列。位线BL可以电连接到第一杂质区SD1。作为一示例，位线BL可以包括例如掺杂半导体材料、导电金属氮化物和金属中的至少一种。
间隔物结构BS可以分别设置在每条位线BL的彼此相反的侧壁上。封盖结构可以设置在每一条位线上。在一些示例中，位线BL、间隔物结构BS和封盖结构GP可与如参照图1和2描述的栅电极GE、间隔物结构GS和封盖结构GP相似。
第一层间绝缘层130和第二层间绝缘层140可以被提供在衬底100上。有源接触CA可以延伸穿过第一层间绝缘层130和第二层间绝缘层140，并且电连接到第二杂质区SD2。至少一个有源接触CA可以是自对准接触。有源接触CA可以接触封盖结构GP并且封盖结构GP可以具有接触有源接触CA的倾斜的侧壁ER。
落着焊盘(landing pad)LP可以设置在第二层间绝缘层140上以分别电连接到有源接触CA。落着焊盘LP可以按二维排列。落着焊盘LP可以重叠有源接触CA。落着焊盘LP可以包括导电材料，例如掺杂半导体材料、金属和/或金属半导体化合物。第三层间绝缘层145可以填充落着焊盘LP之间的间隙。
数据存储元件DS可以在分别电连接到落着焊盘LP时被设置在第三层间绝缘层145上。数据存储元件DS可以是能够存储数据的存储元件。在这样的情况下，包括有源图案AP和栅线GL的场效应晶体管可以起开关元件的作用。在一些示例中，数据存储元件DS可以每个是具有用于存储数据的电容器、磁隧道结(MTJ)图案或包括相变材料的可变电阻结构的存储元件。
在根据本发明构思的半导体器件中，导电图案能在形成自对准接触的同时被有效地保护，并且该接触与导电图案之间的寄生电容也能被减小。因此，提高半导体器件的操作速度是可能的。
虽然已经参照本发明构思的示例具体显示和描述了本发明构思，但本领域普通技术人员将理解，可以对这样的示例进行形式和细节上的各种各样的改变而不背离如所附权利要求限定的本发明构思的精神和范围。
本申请要求2016年4月28日向韩国知识产权局提交的韩国专利申请第10-2016-0052146号的优先权，其公开通过引用全文合并于此。

Claims (24)

1.一种半导体器件，包括：
衬底，其具有有源图案；
导电图案，其交叉所述有源图案，所述导电图案具有彼此相反的侧表面；
所述导电图案的所述侧表面中的至少一个中的每一个上的各自的间隔物结构，所述间隔物结构具有顶表面；以及
封盖结构，其在所述导电图案上，
其中所述封盖结构包括第一封盖图案和第二封盖图案，所述第一封盖图案具有顶表面，以及
所述第二封盖图案设置在所述第一封盖图案的所述顶表面上和所述间隔物结构的所述顶表面上。
2.如权利要求1所述的半导体器件，其中在所述导电图案的所述彼此相反的侧表面中的每一个上设置所述各自的间隔物结构，使得一对间隔物结构设置在所述导电图案的所述彼此相反的侧表面上，以及
所述第一封盖图案插置在所述对间隔物结构之间。
3.如权利要求1所述的半导体器件，其中所述间隔物结构的所述顶表面高于所述导电图案的顶表面。
4.如权利要求1所述的半导体器件，其中所述导电图案在第一方向上纵向地延伸，
所述第一封盖图案和所述第二封盖图案沿着所述导电图案在所述第一方向上纵向地延伸，以及
所述第二封盖图案在交叉所述第一方向的第二方向上的宽度大于所述第一封盖图案在所述第二方向上的宽度。
5.如权利要求1所述的半导体器件，其中所述第二封盖图案的侧表面的一端与所述间隔物结构的侧表面的一端相接。
6.如权利要求1所述的半导体器件，其中所述第一封盖图案包括在其顶表面中的凹口。
7.如权利要求1所述的半导体器件，其中所述封盖结构还包括所述第一封盖图案与所述第二封盖图案之间的包括氧化物层的绝缘图案。
8.如权利要求1所述的半导体器件，其中所述第一封盖图案的所述顶表面与所述间隔物结构的所述顶表面基本上共面。
9.如权利要求1所述的半导体器件，其中所述间隔物结构包括第一间隔物、第二间隔物以及第三间隔物，
所述第二间隔物插置在所述第一间隔物与所述第三间隔物之间，以及
所述第二间隔物的介电常数低于所述第一间隔物和所述第三间隔物中的每一个的介电常数。
10.如权利要求9所述的半导体器件，其中所述第二间隔物在垂直于所述导电图案的其上设置所述间隔物结构的所述侧表面的方向上的宽度大于所述第一间隔物和所述第三间隔物中的每一个的宽度。
11.如权利要求10所述的半导体器件，其中所述第二间隔物的氧浓度大于所述第一间隔物和所述第三间隔物中的每一个的氧浓度。
12.如权利要求1所述的半导体器件，还包括：
层间绝缘层，其覆盖所述封盖结构；以及
有源接触，其延伸穿过所述层间绝缘层，
其中所述第二封盖图案具有接触所述有源接触的，相对于垂直方向倾斜的侧表面，所述垂直方向垂直于所述衬底的上表面，以及
所述第二封盖图案具有在平行于所述衬底的所述上表面的方向上的，随着沿所述垂直方向远离所述衬底的所述上表面而减小的宽度。
13.如权利要求1所述的半导体器件，其中所述有源图案包括具有顶部以及彼此相反的侧的沟道区，以及所述导电图案覆盖所述沟道区的所述顶部和所述彼此相反的侧。
14.如权利要求1所述的半导体器件，其中所述有源图案包括沟道区，
所述沟道区包括彼此垂直地间隔开的半导体图案，以及
所述导电图案围绕所述半导体图案。
15.如权利要求1所述的半导体器件，其中所述有源图案具有杂质区，并且还包括：
在所述导电图案下方的栅线，所述栅线交叉所述导电图案和所述有源图案；
覆盖所述封盖结构的一侧和所述间隔物结构的一侧并且电连接到所述有源图案的所述杂质区的有源接触；以及
数据存储元件，其电连接到所述有源接触。
16.一种半导体器件，包括：
衬底，其具有有源图案；
导电图案，其交叉所述有源图案；以及
在所述导电图案上的封盖结构，所述封盖结构包括第一封盖图案和在所述第一封盖图案上的第二封盖图案，
其中所述第一封盖图案具有凹口，以及所述第二封盖图案具有当与所述第一封盖图案啮合时被容纳在所述凹口中的凸起，以及
其中所述第二封盖图案的宽度大于所述第一封盖图案的宽度。
17.如权利要求16所述的半导体器件，其中所述封盖结构还包括在所述第一封盖图案与所述第二封盖图案之间的绝缘图案，所述绝缘图案包括氧化物。
18.如权利要求16所述的半导体器件，还包括所述导电图案的彼此相反的侧表面中的至少一个中的每一个上的各自的间隔物结构，
其中所述间隔物结构具有高于所述导电图案的顶表面且低于所述第二封盖图案的顶表面的顶表面。
19.如权利要求16所述的半导体器件，还包括：
层间绝缘层，其覆盖所述封盖结构；以及
有源接触，其延伸穿过所述层间绝缘层，
其中所述第二封盖图案的下部部分具有比所述第二封盖图案的上部部分的宽度更大的宽度。
20.一种半导体器件，包括：
衬底，其具有包括源极/漏极(S/D)区的有源图案；
所述衬底上的层间绝缘层；
在所述层间绝缘层内在交叉所述有源图案的第一方向上纵向地延伸的至少一个导电图案，所述导电图案具有彼此相反的侧表面；
所述导电图案的所述侧表面中的至少一个中的每一个上的各自的间隔物结构；
封盖结构，其在所述导电图案上；以及
接触结构，其在所述层间绝缘层中垂直地延伸到所述源极/漏极区，所述接触结构包括电连接到所述源极/漏极区的导电构件，
其中所述封盖结构包括第一封盖图案和第二封盖图案，所述第一封盖图案具有顶表面，所述第二封盖图案具有设置在所述第一封盖图案的所述顶表面上的第一部分和在所述间隔物结构的顶表面上的第二部分，
所述接触结构倚着所述间隔物结构和所述第二封盖图案的所述第二部分设置，以及
所述第二封盖图案是相对于所述层间绝缘层的材料具有蚀刻选择性的材料。
21.如权利要求20所述的半导体器件，其中所述层间绝缘层包括氧化物，以及
所述第二封盖图案为SiN或Al2O3。
22.如权利要求20所述的半导体器件，其中所述间隔物结构包括第一间隔物、第二间隔物和第三间隔物，
所述第二间隔物是其成分包括氧的材料并且插置在所述第一间隔物与所述第三间隔物之间，以及
所述第二间隔物具有比所述第一间隔物和所述第三间隔物中的每一个的介电常数更低的介电常数。
23.如权利要求20所述的半导体器件，其中所述第二封盖图案的所述第二部分具有与所述接触结构接触的凸表面，
所述间隔物结构具有与所述接触结构接触的凸表面，
在与所述接触结构邻近的位置所述第二封盖图案的所述凸表面与所述间隔物结构的所述凸表面相接，以及
所述第二封盖图案的所述凸表面的邻近所述位置的曲率半径与所述间隔物结构的所述凸表面的邻近所述位置的曲率半径基本相同。
24.如权利要求20所述的半导体器件，其中所述导电图案包括一对导电图案，所述对导电图案中的每一个在交叉所述有源图案的所述第一方向上纵向地延伸，所述导电图案在垂直于所述第一方向的第二方向上彼此间隔开，使得所述导电图案具有沿所述第二方向面向彼此的侧表面，
所述导电图案的面向彼此的所述侧表面中的每一个上设置有所述间隔物结构，以及
所述接触结构通过所述间隔物结构与所述源极/漏极区对准。
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