CN107331711A - 一种超低漏电水平的低压tvs器件及其制造方法 - Google Patents
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Abstract
本发明公开了一种超低漏电水平的低压TVS器件及其制造方法，其纵向结构N+击穿区（1）与N+吸杂区（2）可采用垂直交叉式结构或圆形环状式结构。N+吸杂区（1）的结深为15~25um，宽度范围为20~50um，N+击穿区（2）的结深为8~15um，宽度范围为根据不同IPP要求定制；所述N+吸杂区与N+击穿区的间隙设计要求为5~50um。N+吸杂区的主要目的为吸收硅单晶在高温过程中产生的氧化诱生缺陷，形成重度缺陷区域，而N+击穿区则为器件实际有效工作区。通过该发明，实现了低漏电水平，并满足对高IPP通流能力的要求。
Description
技术领域
本发明涉及一种半导体芯片技术领域，具体是一种超低漏电水平的低压TVS器件的制造方法。
背景技术
瞬态抑制二极管TVS产品，广泛应用于太阳能逆变器、机顶盒、MOSFET保护、工业控制、电信基站和以太网供电（PoE）之类的应用。而近年来，越来越多的领域提出需求VBR低于10V，同时，对漏电流IR值希望越低越好，这对器件的开关相应速度及可靠性等有影响。
国内现有技术生产TVS器件，一般在较低电阻率的P型硅片上，通过扩散的方式形成一个深的大面积的N+结，采用挖槽的方式隔离，通过调整结深和掺杂浓度来调整电压。但是对于工作电压小于10V的低压TVS，由于此时P型称底材料为重掺杂硼，器件在高温下，容易生产氧化诱生缺陷，致使漏电不受控，造成误动作，使得产品可靠性降低。
发明内容
为了解决以上技术问题，本发明提供一种超低漏电水平的低压TVS器件，包括N+吸杂区和N+击穿区，N+吸杂区旁设有N+击穿区，两个区域间的间隙设为5~50um，两个区域的上表面设有SiO2钝化层将两个区域进行隔离，最终在上表面蒸发钛镍银金属，将击穿区互联；N+击穿区与N+吸杂区采用垂直交叉式结构或圆形环状式结构。
作为本发明的一种改进，N+吸杂区的结深为15~25um，宽度范围为20~50um，N+击穿区的结深为8~15um。
一种超低漏电水平的低压TVS器件的制造方法包括以下步骤：
1）取硅单晶片，要求：ρ=0.001-0.01 Ω·㎝，硅单晶片厚度t=（200～300）±5 um。
2）硅单晶片用抛光机进行抛光或化学腐蚀：采用HF、HNO2、HAC溶液对硅片进行酸腐蚀，而后采用CMP方式对硅片表面抛光，完成后的硅片厚度t=（170～270）±5 um。
3)氧化：在温度1140±20℃下氧化4.0±1h，生长出一层厚度为1.0-1.5um氧化层（3）。
4)双面光刻N+吸杂区1：纵向结构带有短路孔，利用双面光刻机，对准上、下两块光刻版，将硅片置于两块光刻版的中间，同时曝光；上、下两块光刻版的图形是相同的。
5)采用POCL3气相掺杂法对N+吸杂区（1）磷予扩，予沉积T=1050~1170℃，t=2.2±1.0h，R□=0.5~1.2Ω/□。
6)采用POCL3气相掺杂法对N+吸杂区（1）磷再扩，再分布T=1200~1250℃，t=15±5h，Xj=15~25um。
7)光刻形成N+击穿区。
8) N+击穿区（2）磷予扩：
予沉积T=850~950℃，t=1.0±0.5h, R□=15~35Ω/□。
9)N+击穿区（2）磷再扩：
再分布T=1100~1200℃，t=4.0±2.0h, Xj=8~15um。
10)光刻引线孔：用刻引线孔版进行光刻，将N+击穿区域刻出，用于金属互联。
11)双面蒸发钛镍银金属4：要求金属总厚度为3~4um。
12)反刻钛镍银金属（4）：用反刻版进行光刻，并腐蚀掉非有效区域的钛镍银金属（4）。
13)合金：合金条件为温度360~520℃，时间0.4±0.1h，形成芯片。
14)芯片测试：用冠魁的自动测试台进行测试。测试VBR、IR参数，并对VBR进行分档。
15)锯片：保留硅片1/2~1/3厚度，裂片将芯片分开。
16)将制造完毕的芯片包装。
本发明的原理是：引入N+吸杂区，将硅单晶体内的缺陷聚集，而在N+击穿区域，由于表面较少的缺陷存在，使得漏电流值大幅降低。而其大面积的N+击穿区域又保障了产品的浪涌IPP能力。
本发明的优点是：本发明工艺流程简单，而达到的漏电流值非常低，且产品通过浪涌电流IPP能力也满足需求。
附图说明
图1为本发明结构图
图2为本发明交叉结构俯视图
图3为本发明环状结构俯视图
图中，1代表N+吸杂区域， 2代表N+击穿区域， 3代表SiO2氧化层，4代表表面钛镍银金属。
具体实施方式
本发明超低漏电水平的低压TVS器件的制造方法，包括以下步骤：
1）取硅单晶片，要求：ρ=0.001-0.01 Ω·㎝，硅单晶片厚度t=（200～300）±5 um。
2）硅单晶片用抛光机进行抛光或化学腐蚀：采用HF、HNO2、HAC溶液对硅片进行酸腐蚀，而后采用CMP方式对硅片表面抛光，完成后的硅片厚度t=（170～270）±5 um。
3)氧化：在温度1140±20℃下氧化4.0±1h，生长出一层厚度为1.0-1.5um氧化层（3）。
4)双面光刻N+吸杂区1：纵向结构带有短路孔，利用双面光刻机，对准上、下两块光刻版，将硅片置于两块光刻版的中间，同时曝光；上、下两块光刻版的图形是相同的。
5)采用POCL3气相掺杂法对N+吸杂区（1）磷予扩，予沉积T=1050~1170℃，t=2.2±1.0h，R□=0.5~1.2Ω/□。
6)采用POCL3气相掺杂法对N+吸杂区（1）磷再扩，再分布T=1200~1250℃，t=15±5h，Xj=15~25um。
7)光刻形成N+击穿区。
8) N+击穿区（2）磷予扩：
予沉积T=850~950℃，t=1.0±0.5h, R□=15~35Ω/□
9)N+击穿区（2）磷再扩：
再分布T=1100~1200℃，t=4.0±2.0h, Xj=8~15um。
10)光刻引线孔：用刻引线孔版进行光刻，将N+击穿区域刻出，用于金属互联。
11)双面蒸发钛镍银金属4：要求金属总厚度为3~4um。
12)反刻钛镍银金属（4）：用反刻版进行光刻，并腐蚀掉非有效区域的钛镍银金属（4）。
13)合金：合金条件为温度360~520℃，时间0.4±0.1h，形成芯片。
14)芯片测试：用冠魁的自动测试台进行测试。测试VBR、IR参数，并对VBR进行分档。
15)锯片：保留硅片1/2~1/3厚度，裂片将芯片分开。
16)将制造完毕的芯片包装。
以1.78*1.78mm版面，SMBJ6.5CA测试数据如下（测试仪表采用冠魁TVR6000，VBR测试条件为10mA，IR测试条件为6.5V，雷击能力测试采用冠魁VC5300设备，波形为10/1000us）：
漏电主流分布在0.1至2uA，功率等级测试通过900W。
以下表格是某知名国外器件生产商制造的产品的测试结果：
漏电主要分布在40-80uA之间，功率等级为900W。
本发明工艺流程简单，达到的漏电流值非常低，分布在0.1至2uA之间，且产品通过浪涌电流IPP能力也满足需求。
Claims (3)
1.一种超低漏电水平的低压TVS器件，包括N+吸杂区（1）和N+击穿区（2），其特征在于：所述N+吸杂区（1）旁设有N+击穿区（2），两个区域间的间隙设为5~50um，两个区域的上表面设有SiO2钝化层（3）将两个区域进行隔离，最终在上表面蒸发钛镍银金属（4），将击穿区互联；N+击穿区（1）与N+吸杂区（2）采用垂直交叉式结构或圆形环状式结构。
2.根据权利要求1所述的一种超低漏电水平的低压TVS器件，其特征在于：所述N+吸杂区（1）的结深为15~25um，宽度范围为20~50um，N+击穿区（2）的结深为8~15um。
3.一种超低漏电水平的低压TVS器件的制造方法，包括以下步骤：
1）取硅单晶片，要求：ρ=0.001-0.01 Ω·㎝，硅单晶片厚度t=（200～300）±5 um；
2）硅单晶片用抛光机进行抛光或化学腐蚀：采用HF、HNO2、HAC溶液对硅片进行酸腐蚀，而后采用CMP方式对硅片表面抛光，完成后的硅片厚度t=（170～270）±5 um；
3)氧化：在温度1140±20℃下氧化4.0±1h，生长出一层厚度为1.0-1.5um氧化层（3）；
4)双面光刻N+吸杂区1：纵向结构带有短路孔，利用双面光刻机，对准上、下两块光刻版，将硅片置于两块光刻版的中间，同时曝光；上、下两块光刻版的图形是相同的；
5)采用POCL3气相掺杂法对N+吸杂区（1）磷予扩，予沉积T=1050~1170℃，t=2.2±1.0h，R□=0.5~1.2Ω/□；
6)采用POCL3气相掺杂法对N+吸杂区（1）磷再扩，再分布T=1200~1250℃，t=15±5h，Xj=15~25um；
7)光刻形成N+击穿区；
8) N+击穿区（2）磷予扩：
予沉积T=850~950℃，t=1.0±0.5h, R□=15~35Ω/□；
9)N+击穿区（2）磷再扩：
再分布T=1100~1200℃，t=4.0±2.0h, Xj=8~15um；
10)光刻引线孔：用刻引线孔版进行光刻，将N+击穿区域刻出，用于金属互联；
11)双面蒸发钛镍银金属4：要求金属总厚度为3~4um；
12)反刻钛镍银金属（4）：用反刻版进行光刻，并腐蚀掉非有效区域的钛镍银金属（4）；
13)合金：合金条件为温度360~520℃，时间0.4±0.1h，形成芯片；
14)芯片测试：用冠魁的自动测试台进行测试；测试VBR、IR参数，并对VBR进行分档；
15)锯片：保留硅片1/2~1/3厚度，裂片将芯片分开；
16)将制造完毕的芯片包装。
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1235380A (zh) * | 1999-04-07 | 1999-11-17 | 赵振华 | 一种小功率晶闸管的结构及其制造工艺 |
| US20050145945A1 (en) * | 2004-01-02 | 2005-07-07 | Semiconductor Components Industries, Llc | High energy ESD structure and method |
| CN103956324A (zh) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | 一种具备沟道效应的瞬态电压抑制器芯片的生产工艺 |
| CN105489612A (zh) * | 2015-12-07 | 2016-04-13 | 上海长园维安微电子有限公司 | 基于soi基底的低漏电低电容tvs阵列及其制备方法 |
| US20160365294A1 (en) * | 2015-06-11 | 2016-12-15 | Renesas Electronics Corporation | Semiconductor device |
| CN207038533U (zh) * | 2017-07-26 | 2018-02-23 | 捷捷半导体有限公司 | 一种超低漏电水平的低压tvs器件 |
-
2017
- 2017-07-26 CN CN201710618686.4A patent/CN107331711B/zh active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1235380A (zh) * | 1999-04-07 | 1999-11-17 | 赵振华 | 一种小功率晶闸管的结构及其制造工艺 |
| US20050145945A1 (en) * | 2004-01-02 | 2005-07-07 | Semiconductor Components Industries, Llc | High energy ESD structure and method |
| CN103956324A (zh) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | 一种具备沟道效应的瞬态电压抑制器芯片的生产工艺 |
| US20160365294A1 (en) * | 2015-06-11 | 2016-12-15 | Renesas Electronics Corporation | Semiconductor device |
| CN105489612A (zh) * | 2015-12-07 | 2016-04-13 | 上海长园维安微电子有限公司 | 基于soi基底的低漏电低电容tvs阵列及其制备方法 |
| CN207038533U (zh) * | 2017-07-26 | 2018-02-23 | 捷捷半导体有限公司 | 一种超低漏电水平的低压tvs器件 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2698741C1 (ru) * | 2019-01-30 | 2019-08-29 | Акционерное общество "Научно-исследовательский институт молекулярной электроники" | Способ изготовления вертикального низковольтного ограничителя напряжения |
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