CN1073284C - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN1073284C CN1073284C CN95117176A CN95117176A CN1073284C CN 1073284 C CN1073284 C CN 1073284C CN 95117176 A CN95117176 A CN 95117176A CN 95117176 A CN95117176 A CN 95117176A CN 1073284 C CN1073284 C CN 1073284C
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- lsi chip
- lead frame
- resin molding
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 229920005989 resin Polymers 0.000 claims abstract description 103
- 239000011347 resin Substances 0.000 claims abstract description 103
- 238000000465 moulding Methods 0.000 claims abstract description 51
- 238000000227 grinding Methods 0.000 claims description 92
- 238000012545 processing Methods 0.000 claims description 73
- 238000005498 polishing Methods 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 230000002787 reinforcement Effects 0.000 claims description 12
- 239000004744 fabric Substances 0.000 claims description 11
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 10
- 239000002245 particle Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000004033 plastic Substances 0.000 claims description 2
- 229920003023 plastic Polymers 0.000 claims description 2
- 206010027439 Metal poisoning Diseases 0.000 claims 3
- 239000008393 encapsulating agent Substances 0.000 claims 2
- 230000002708 enhancing effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 18
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 230000003014 reinforcing effect Effects 0.000 abstract description 6
- 230000008439 repair process Effects 0.000 abstract description 5
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 230000005855 radiation Effects 0.000 abstract 1
- 230000015654 memory Effects 0.000 description 79
- 238000000034 method Methods 0.000 description 52
- 239000010410 layer Substances 0.000 description 24
- 238000003475 lamination Methods 0.000 description 22
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 18
- 238000003754 machining Methods 0.000 description 18
- 230000008569 process Effects 0.000 description 15
- 238000005538 encapsulation Methods 0.000 description 13
- 239000004575 stone Substances 0.000 description 13
- 230000003746 surface roughness Effects 0.000 description 12
- 238000005452 bending Methods 0.000 description 11
- 230000014509 gene expression Effects 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000009434 installation Methods 0.000 description 8
- 238000003672 processing method Methods 0.000 description 8
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000006378 damage Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 239000012530 fluid Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 238000007598 dipping method Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 239000003513 alkali Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000005728 strengthening Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 239000002585 base Substances 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000008119 colloidal silica Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 238000003490 calendering Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 231100000241 scar Toxicity 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Abstract
根据本发明的一种树脂制模的引线框架型半导体器件,具有一个金属引线框架和一个制模树脂LSI芯片,其特征在于,金属引线框架的引线通过相应的突起电极与LSI芯片上的多个电极电连接,从而提供减薄了厚度的半导体器件,其中金属引线框架和LSI芯片被树脂制模在器件的表面上,使不形成LSI图形的一面呈露出状态并进行磨削加工。
Description
本发明是极小型高性能半导体器件的构造及制造方法,它涉及小型计算机及工作站等的存储元件以及前述OA机器中用做选择连接的卡片型存储载体,特别是在小型移动式具有相互通信功能的多媒体机器和可完成各种数字处理的图像摄影装置中,用做高速动作和数据编辑的优良存储载体。
现在市售的树脂型半导体器件中,为了构成LSI组件的外部电极,多采用制造费用比较低的引线框架。如特开昭61-241959号公报所记载的内容,可根据引线框架和LSI芯片的位置关系,分为引线框架在LSI芯片上面的LOC型(Lead on Chip)和引线框架在LSI芯片下面的COL型(Chip on Lead)。在COL型构造中,使用被称为模片小块的一部分引线框架,进行引线框架和LSI之间的粘结加工,把两者加以固定。在以上两种构造中,引线框架和LSI电极的电连接,用25μm左右的Au导线,使用超声波和热进行压接的导线粘接法。这时,为了确保温度周期的可靠性,至少要有110μm以上的导线环高度的外形尺寸。特别是在COL型中,要与模片小块的厚度相配合,即使薄型化也很难达到0.45mm以下。
为了实现构造上的薄型化,在聚酰亚胺带上层压35μm左右的Cu箔,对Cu箔进行蚀刻处理,形成电极图形的带式载体,再把带式载体电极上的电镀金属和LSI电极上的Au凸出,进行热压接,制成带式载体型半导体器件。然而,带式载体本身的标准化是困难的,加工也很费工夫,因此,使半导体器件的产品成本增加。在这种结构中,由于支持LSI芯片的电极部容易变形,在其周边为树脂制模情况下,因为树脂的流入压力,产生了金属模内部的LSI芯片移动和聚酰亚胺带热变形的问题,为此,如JPA-5-315384所述,设置了防止LSI芯片移动及变形的部件。由于附加了该部件,在采用导线粘接情况下,实现薄型化是可能的,然而,半导体器件的薄型化仍然是有限度的。
带式载体型半导体器件中,由于外部电极的机械强度不够,电极成形量是有偏差的,当向印刷电路基板等安装时,不能确保半导体装置的外部电极与装载基板上的电极图形的位置精度,操作是困难的。再加上机械强度不够,用焊锡连接时,在接合部位的引线材料将熔化,给安装后的修复工作造成很大困难。
某些特定种类的半导体,当紫外线等光线投射到LSI表面时,将出现误动作。半导体器件的薄型化,当然也要求周边树脂厚度变薄,因此就必须有防止误动作的措施,然而,当前还没有既考虑了遮光又使半导体器件薄型化的设计方案。
RAM和ROM安装到flash存储器种类的存储器LSI内装半导体器件的磁盘和CD-ROM,可代替磁带达到一定的存储容量,为了在有限的装载基板安装面积上有尽可能大的容量,把多个半导体器件,用具有同一功能的电极连接起来构成叠层配置,为此,提出了各种各样的方案。作为采用引线框架和导线粘接法的薄型组件的代表,是以厚1mm的TSOP组件为叠层单位,如JP-A-3-96266所记载,不仅是单层厚度而且叠层整体都变厚了,是不可能装载在存储器插件限定的空间,或者说不可能发挥出节省空间的效果。当利用带式载体构造制成叠层结构时,由于电极部强度不够,则叠层数目是有限的,而且当叠层结构中混入次品时,把次品去除换成正品的修复工作也有很大困难。
另外,美国专利5,021,865公开了一种半导体器件的引线架,其中的布线图形是在半导体芯片的连接部分形成的,其连接结构是传统式的,即并没有提供半导体芯片的各触脚与引线框架连接的结构。
如上所述,已有技术有优点也有缺点,能同时满足薄型化、安装时的操作性、耐有害光线、放热性、确保机构强度等的半导体器件是没有的。
本发明的目的是在采用导线粘接的构造中,实现因受导线环高度和树脂厚度制约的半导体器件的超薄型化和低成本,把该半导体器件制成叠层结构,从而提供提高了单位面积安装效率的半导体器件。
本发明的另一目的是提供一种半导体器件的制造方法,它可以在不增加工时和成本的情况下,加强LSI芯片及半导体器件,抑制由于制模树脂收缩引起的变形,改善修复的操作性,改善树脂制模工序中的制模操作性。
本发明的其它目的是提供一种半导体装置,它可以使叠层模块状态的LSI芯片高效率放热,遮挡有害光线投射到LSI表面,从而防止LSI芯片的误动作。
根据本发明的一种树脂制模的引线框架型半导体器件,具有一个金属引线框架和一个制模树脂LSI芯片,其特征在于,金属引线框架的引线通过触脚与LSI芯片上的一个电极电连接,从而提供减薄了的厚度的半导体器件,其中金属引线框架和LSI芯片被树脂制模在器件的没有LSI芯片的电路形成的表面上,且毗邻所述表面的树脂为一个加工表面。
为达到上述目的,实现本发明的半导体器件的超薄型化和低成本,要有极薄的压延工序,以使电极成形和安装时的修复有足够的强度,并使整体均一厚度的金属引线框架与LSI上的电极直接冶金连接,使其露出在LSI芯片里面未形成的电路图形的镜面上,树脂制模以后,从LSI镜面进行磨削加工,制成厚250μm以下的半导体器件。另一种情况是,把LSI芯片镜面进行前述的磨削加工后,把该面抛光或用碱性溶液在湿式蚀刻工序中进行磨削加工,以去除在LSI芯片镜面产生的加工变形。这样,可提高组件的可靠性。
按照本发明,还可以使用比较便宜的引线框架,实现低成本化,同时,为了防止薄型化带来的LSI芯片损坏和半导体器件的弯曲变形,特别提供了加强部和放热通路、LSI图形的遮光部件、以及在适当位置的部件。
用导线粘接法构造是不可能的,而用带式载体便可以低成本提供极薄的半导体器件。
不可能使用带式载体时,可选用适当厚度和种类的金属箔,形成引线框架,以使电极部达到适当的强度,提高基板装载时及功能模块形成时的修复性。对制成品很容易使用插座等进行分批检查。在树脂制模时,可以把LSI芯片保持在模型内部的规定位置,树脂部分的薄型化设计是容易的。
把引线框架的一部分作为加强部,在树脂制模后,从LSI芯片里面,用半导体器件的金刚石磨具进行磨削加工,再用游离的磨粒和抛光十字管进行抛光,以便薄型化稳定下来。在工序中对LSI芯片及晶片的处理与已有产品是一样的,这样可以实现整个器件的厚度和内装LSI芯片的极薄化。
由于LSI芯片的镜面是露出的,因此可高效率地放热。
半导体器件单元块可制成极薄型的,当在有限的存储器插件高度和安装面积情况下安装尽可能多的半导体器件时,可采用多个叠层配置的安装方法,以实现单位面积及单位体积的高功能化。
下面参见附图,说明本发明的实施例,图中同一参考数字或符号表示相同的元件或部件
附图简单说明。
图1A~1C是本发明的基本构造图,图1A是单层上面构造图,图1B是单层横剖面图,图1C是叠层构造图。
图2表示已有的引线框架蚀刻形状图。
图3表示本发明的有效引线框架蚀刻形状图。
图4A~4B表示热应力解放型内部引线形状图,图4A是切断前的引线框架平面图,图4B是芯片连接后切断加工状态的平面图。
图5A~5B表示适当位置的基准部分,图5A是适当位置的侧面图,图5B是适当位置的斜视图(挑出了元件)。
图6是锭模工序剖面图。
图7A~7B分别表示已有技术和本发明的半导体器件的弯曲状态。
图8A~8B是说明磨削加工薄型化方法的加工状态的上面图和剖面图。
图9是表示共同功能电极连接状态的斜视图。
图10A~10C是表示内部引线种类变更方法(蚀刻加工方法)图,图10A是芯片选择的形状图形(1),图10B是芯片选择的形状图形(2),图10C是芯片选择的形状图形(3)。
图11A~11C是表示内部引线种类变更方法(切断加工方法)图,图11A是芯片选择引线切断图形(1),图11B是芯片选择引线切断图形(2),图11C是芯片选择引线切断图形(3)。
图12表示本发明半导体器件的引线形状(2段折弯)图。
图13表示通过焊锡浸渍的焊锡供给方法图。
图14A~14B是表示已有叠层存储器插件与本发明叠层存储器插件的比较的侧面图,图14A是本发明的叠层存储器,图14B是已有叠层存储器。
图15A~15B是分别说明与磨削加工合用的抛光加工概念的斜视图和剖面图。
图16是薄壁化加工后的存储器剖面图。
图17是薄壁化加工后的存储器的加工形状。
图18A~18B是分别表示已有技术和本发明的存储器制造工序的流程图。
图19是引板构造存储器剖面图。
图20是LOC构造存储器剖面图。
图21是TSOP存储器剖面图(LOC构造)。
图22是超薄型存储器剖面图(LOC构造)。
(实施例1)
下面参照图1~图8,说明本发明的极薄半导体器件的构造和制造过程。
图1A~1C表示厚度250μm以下的薄型半导体器件的构成要素。其构成是:极薄金属性引线框架1;为了在其上形成电极部,用直接冶金学方法连接的LSI芯片2;通过制模树脂4,使不形成LSI图形的一面呈露出状态并予以密封,对制模后露出面进行磨削加工,使其薄型化,以LSI芯片2加强为主要目的进行加工的引线框架的一部分。数字3表示LSI加强部,5表示凸起。
引线框架1是以50μm以下的Fe-Ni系合金为材料的条形,用蚀刻使其图形化。如果引线框架材料没有热膨胀问题,而且机械强度足够时,Cu系合金也可以作为材料。
该极薄的引线框架1,特别是与LSI芯片2连接的部分,应与LSI芯片2上的电极尺寸密切配合,该电极部分为图2所示的通常厚度引线框架的形状,以防止树脂制模时树脂流出。在蚀刻和电镀工序中,由于蚀刻过多的损失和电镀液射流,使产生变形的可能性变大了。这里,数字6是已有的引线框架图形,8表示LSI芯片的安装位置。如图3所示表示本发明引线框架图形9的引线框架,在与LSI上电极连接部的接近处,设置了利于引线框架成形的加强部3,该形状一直保持到蚀刻及电镀工序完成。此后,在与LSI连接前,在规定位置断电,使其绝缘。7是适当位置的孔用加工部,10是切断加工位置,11是适当位置用孔。采用此方法,可使LSI芯片上的电极数增大时,更易于引线框架上电极的成形。在引线框架1和LSI连接部,由于引线框架的热膨胀,可能有断线问题,因此不用直线形状连接,而采用图4A~4B所示的曲线形状12,可以减小产生的应力,设置了应力释放部12。14表示适当位置的孔用加工部。不仅是蚀刻,而且用接线和冲孔等机械冲裁加工,也可以使引线框架成形。
已成形的引线框架1与LSI芯片2上的电极连接时,通过LSI电极上形成的Au突起电极和引线框架上Au或Ag电镀的热压,进行金属扩散接合。不在LSI芯片2上的电极,而在引线框架设置突起电极,也可以实现引线框架与LSI芯片的连接。
为了在引线框架上成形与LSI芯片连接用电极的加强部分3,不是全部去掉,而是其一部分与LSI芯片2重叠,但与引线框架1和LSI芯片2的电连接毫无关系。该部分作为LSI芯片的加强部分3,在LSI芯片及半导体器件薄型化时,可防止弯曲变形和LSI芯片破裂。通过对LSI芯片2加强部分3形状的改进,可作为放热用散热器,或者使其露出在制模树脂4外部,作为散热片。图5A~5B表示安装时,根据销和孔法,形成的适当位置孔13。这里,15是制模金属模。它可以遮当使LSI芯片误动作的有害光线,照射到LSI芯片上的图形形成面。
连接引线框架1和LSI芯片2后,用树脂在其周边进行制模。如图6所示,在不形成芯片2的LSI电路的镜面,由按压制模用金属模15进行制模,制模完成后,使镜面呈露出状态。由于引线框架1的刚性与带式载体型半导体的35μm Cu箔比较,是较高的,因此,树脂流入压力在制模内部产生的LSI芯片位移,通过树脂的薄型化设计,可得到充分抑制。
制模树脂4的流入不是侧面流动,而是从半导体器件的引线框架1方面(图形形成面)流入树脂,如图6所示,希望采用自顶向下流动。采用此法时,可更好抑制LSI芯片的位移。在树脂制模工序中,采用通常树脂粘度百分之一的低粘度树脂,使得树脂部分的薄型设计是可能的。
通常仅在LSI芯片2处进行树脂制模密封,由于树脂的硬化收缩,或者作为树脂材料的环氧树脂和作为LSI芯片材料的Si的热膨胀系数的差别,在半导体器件整体中可产生如图7A所示的弯曲,这时,可引起LSI芯片2破裂。这是半导体器件薄型化的特别问题。然而,如图7B所示,在本发明中,把引线框架1(9)的一部分作为LSI芯片的加强部3A,可抑制其变形。当装载大尺寸LSI芯片时,该加强是有效的。把加强部件装入树脂制模部4的结构,不必从后面在外部安装加强板,而是与里面磨削工序结合起来,这对薄型化是有利的。
到制模工序为止,半导体器件的厚度约为450μm左右。这是由引线框架1(9)的厚度、引线框架和LSI芯片接合部的高度、LSI芯片的厚度、以及制模可能的树脂硬度的最小值规定的。目前,把Si晶片加工在厚250μm以下时,则在晶片运送、切出每一个芯片的工序中,可因破裂损坏等原因,使不合格率显著增大。当前,磨削加工可使晶片本身的弯曲变形达数毫米,使得晶片的切断以及用导线粘接等与引线框架的连接,成为不可能。因此,单块晶片实用上的薄型化限度是200μm。在形成本发明的250μm以下超薄型半导体器件时,考虑到这一点,并不采用薄磨削加工的LSI芯片,而是在树脂制模工序完成后,从LSI芯片的镜面,也就是从LSI芯片的露出面,如图8A~8B所示,进行磨削加工,使整体薄型化。图中,27是工作架,28是制模后的半导体器件,例如包封后的存储器,29是磨削磨石。该方法可使LSI芯片2的厚度在50μm或其以下。在该工序中,使引线框架2的一部分构成加强部,可有效地防止LSI芯片的破裂、半导体器件的弯曲等。
在磨削加工时,由于已经预测到了加工产生的力对LSI芯片的破坏或者树脂与LSI芯片的剥离,以及由于加工后的表面粗糙,热冲击等外力容易造成破坏等现象,因此未发生这些情况。但要进行磨削加工条件、方法的选定。
下面,说明里面磨削加工方法。在磨削加工时,例如可用帽型金刚石磨石,进行平面磨削。该方法比用盘型磨石的方法,可使表面粗糙度小。用横切磨削方式,也有助于减小表面粗糙度。
加工时,工作架上有数个到数十个半导体器件,LSI芯片上的电路形成面在工作架一边,不形成电路的一面也像被加工面一样固定。磨削条件如下。
加工机:平面磨削机(日立精工株式会社制造GHR-SF)
磨削磨石:金属结合金刚石磨石
(SD1500P75M)
磨削磨石转数:5000转/分
工作轴转数:300转/分
进刀速度:50μm/分
进刀量:0.3、0.4、0.5、0.55mm
半导体器件内装的LSI芯片达0.05mm厚时的磨削加工,未发生LSI芯片的破裂、树脂的剥离、表面粗糙度达0.08μm Rmax时,可加工到近于镜面状态。加工后,进行了温度周期试验(-55℃~150℃)的可靠性检验,未发生因磨削加工引起的LSI芯片破裂、树脂剥离。
上述半导体器件的磨削加工,其薄型化的限度如下。作为LSI芯片表面布线层的激活层和布线层加在一起的厚度,必须确保约0.006mm以上。防止内装LSI芯片因紫外线等有害光线而误动作的树脂部分,其厚度须为0.1mm。两者合计厚为0.11mm。若引线框架部分的加强结构,能确保LSI芯片的机械强度,半导体器件的厚度也可以不限于这个厚度。
如前所述,仅进行了磨削加工的表面,由温度周期试验可见,也仅仅满足了可靠性。然而,要想完全防止加工表面的变形和微小裂缝,是极困难的。因此,为了消除这些缺点,提高可靠性,要对磨削加工后的加工面,进行下述的抛光和湿式蚀刻处理。
先说明抛光。
图15是抛光概念图。所谓抛光,在抛光平台上贴抛光布,在抛光布上有流动的抛光液,把被加工物按压在上面,然后使抛光平台转动。通过被加工物与抛光布间隙中的磨粒的滑动,对被加工物表面进行微细加工。
抛光加工条件如下。加工机:单面抛光机(スピ-
ファム制SH24)抛光液:胶态二氧化硅(FUJIMI制GLANZOX3900)平台转数:100转/分工作轴转数:100转/分抛光压力:20KPa抛光布:不织布(ロテ-ルニツタ制Suba400)经约10分钟的加工,加工面即为镜面状态。这时的表面粗糙度为0.01Rmax。未发生树脂与LSI芯片交界面的剥离和LSI芯片破裂现象。
以下说明湿式蚀刻。
湿式蚀刻的主要加工对象是LSI芯片的磨削加工面。硅晶片的蚀刻液有酸性液和碱性液两种,为了防止对42合金制引线框架的腐蚀,选择碱性蚀刻液。选择湿式蚀刻的条件如下。
蚀刻液:氢氧化钾(KOH)溶液
蚀刻时间:2分钟
2分钟蚀刻有20μm的蚀刻量,蚀刻后的LSI芯片表面粗糙度为1.5~2.3μmRmax。与抛光加工一样,蚀刻加工后,未发生树脂与LSI芯片交界面的剥离和LSI芯片破裂现象。
上述抛光和湿式蚀刘都是磨削加工的辅助加工,不是磨削加工后一定要进行的。为达到本发明的目的,也可以采用上述薄型化加工以外的其它方法。
在薄型化设计时,LSI芯片的图形面的树脂必须是薄型化的,然而,必须防止由于紫外线等有害光线照射的误动作,把引线框架的一部分加工成LSI芯片的加强部,可以同时起到遮光部的作用,能有效防止光线引起的误动作。
树脂制模工序完成后,分别切出每个半导体器件的单片,在向基板安装时,根据规定形状,加工电极部分,制成超薄型半导体器件。
在基板安装或其它同种类半导体器件叠层安装时,可以采用加工引线框架时的销和孔法形成的适当位置孔穴。
(实施例2)
参照图9~13,说明至少由2个以上叠层配置的本发明超薄型半导体器件构成的叠层半导体器件的实施例。
在用实施例1的方法制成的半导体器件中,例如安装存储器LSI时,从各LSI芯片引出的电极中,具有共同功能的地址电极和数据输出输入(I/O)电极,可以图9所示的形状共同连接。此外,各个电气上独立的芯片的功能电极,例如芯片选择(CS)电极,有图10A~10C所示的引线框架形状的不同芯片选择,根据引线方式(1)~(3),变化与LSI芯片上电极的连接方法,分别配置不同位置的电极。这时,在各层半导体器件中,为其它层半导体器件的芯片选择引导为目的电极,要设计成比叠层半导体器件少一个,使各LSI芯片都是电气上独立的。当以芯片选择电极的引导为目的,改变引线框架的形状时,除了用蚀刻改变图形的方法外,也可以根据图11A~11C的连接图形(1)~(3),对具有共同形状的引线框架,在接近LSI芯片上电极的连接部的规定位置,如切断加工位置19所示,进行切断,以分成不同种类,这种方法也可以有效地调整各种类的生产数量。
虽然引线框架形状各异,但制模后的外观,各层半导体器件都是同样的,这样可以提高电极成形等安装的操作性。当有必要区别各半导体时,设计了判别用表示标记。
叠层构造的电极部分的形状,是如图12所示的形状。图中,20是基板上的电极,21是基板和半导体模块连接部,22是各层间连接部。在树脂4的近端安装基板,反方向折弯,设置一定长度的平行部,再在安装基板处折弯,形成2段折弯。这种形状可减少动作时连接部分产生的热应力,也可减小各层LSI芯片及层间连接部产生的应力,达到半导体器件的长寿命、高可靠性。
叠层安装的连接,采用设置在各层引线框架的适当位置的孔穴。这样,在叠层具有多个微小电极的半导体器件时,很容易操作。在叠层连接时最初使用的固定夹具,仅进行电气连接。引线框架上的电极,由焊锡槽浸渍供给焊锡,此后,在适当的位置,一起连接各层间连接部。例如,Fe-Ni系材料制成的引线框架,在与LSI芯片上电极连接的位置和外部电极的位置,进行Ag电镀。制模工序完成后,切出规定形状的各半导体器件,浸渍在图13所示的焊锡槽中。这时,焊锡的供给量由Ag电镀的范围和浸渍深度控制。焊锡置换Ag电镀时,Ag电镀残留在一部分焊锡中,在叠层连接部,焊锡的熔点与基板安装的连接部比较,向高的方向呈阶层化发展。因此,对于基板安装的热工序来说,可提高层间连接的可靠性。
除了设置叠层连接部和基板安装连接部的温度阶层外,在各层间连接部使用了Sn/Pb、10/90焊锡,而在基板安装的电极使用了Sn/Pb、60/40低共熔晶体焊锡。使用高温焊锡时,引线框架上的电镀也可用Sn等。
无论在与LSI的连接部和基板安装连接部,引线框架上的电镀都可用同一种类,这样,就可减少引线框架的制造费用,焊锡浸渍也方便了。
叠层连接完成后,可通过设置的检验用插座或临时安装在检验基板上,进行叠层模块的电气检查,当全部确认半导体器件的动作后,用UV或热硬化型粘接剂,固定各层间的位置。与这种辅助固定一起使用,可提高层间电连接部的可靠性。
由于用焊锡进行层间连接,当电连接后对各层检查时发现一些半导体器件不合格,则可进行取换该层的修复工作。例如,可用焊锡吸收用吸油绳除去层间连接部的焊锡,以分开各层,再通过焊锡层浸渍,供给新合格品焊锡,替模不合格品,然后进行电连接。若由于焊锡量少引起断线时,则在该部分供给一定量的胶状焊锡,再进行电连接。
在安装叠层配置的半导体器件时,由于在叠层模块内部的LSI芯片,有多个动作,发热密度很高,必须考虑模块的放热问题。本发明的超薄型半导体器件,为了保护LSI芯片,设置了加强部分,并使这部分露出在制模树脂外,则该部分就成为模块在基板上的热传导通路或散热片。该方法在叠层更多半导体器件时,也可以从中间层促进放热。也可以在镜面的芯片露出部安装其它辅助放热装置。
(实施例3)
参照图14、图16~20,说明装有实施例1及实施例2的极薄型半导体器件及叠层型模块或其它必要的电子部件的功能插件的实施例。
例如内装存储器LSI时,规格尺寸必须是厚5mm以内,而本发明的半导体器件的内装叠层模块,一层平均厚度为0.25mm以下,8层叠层构造的厚度为2mm,可以在1mm左右的印刷电路基板的两面安装模块。采用通常的TSOP型半导体器件时,由于外壳厚度为1mm,在一面仅可安装2层。当采用带式载体型半导体器件时,如图14B所示的实际限度是在基板的一面安装4个每层平均0.6mm的模块。图中,25是带式载体型叠层模块,26是存储器等部件。由于带式载体型引线刚性较低,基板安装仅能是叠层状态,不可能处理单块叠层模块。这就使安装工程中的修复工作很困难。
如图14A所示,若采用本发明的半导体器件,对相同面积的基板,可以安装现有技术4倍的存储器LSI。这里,24表示构成半导体器件的叠层模块。若不采用叠层型模块,因为单层半导体器件的厚度在0.25mm以下,所以也可以制成极薄型插件。
插件形模块的放热,热传导方法是有效的。利用半导体器件上的LSI芯片加强部分,或者把装配在外部的放热部件作为插件的外壳,使其与金属制外皮接触,都可以实现高效率的放热。
上述实施例记述了叠层存储器,而进行了薄壁化加工的超薄型单块存储器,在安装上是有优点的,可以不用叠层。下面记述进行薄壁化加工的超薄型存储器的实施例。
先用图18A~18B说明已有的存储器制造程序。已有的制造工序如图18A所示,在6英寸或8英寸的硅晶片表面(镜面)上,用印刷(リソゲラフィ)技术形成薄膜电路,在一个硅晶片上形成数十个LSI。这时的硅晶片厚度是容易处理的,为了防止由于热处理工序中的热冲击使晶体破裂,使其为0.5~0.6mm。然而,为了改善放热性和减少功率晶体管的集电极电阻,在形成薄膜电路后,还要使晶片更薄。为此,在晶片里面进行磨削加工(里面磨削),使晶片厚度为0.3~0.4mm。此后,进行切块和制片,把LSI切成芯片。接着把LSI芯片固定在引线框架上(焊片),芯片内的端子与引线框架间,用导线连接。随后,用树脂(制模树脂)密封LSI芯片和引线框架(封装)后,切断封装后的突出的引线框架,并折弯成形(引线成形)。
如上所述,在已有的存储器制造工序中,没有封装后的存储器薄壁化工序,为了在本工序中使存储器薄壁化,必须在里面磨削时使晶片变薄。在里面磨削工序中,晶片可薄到0.1mm,然而,晶片变薄以后,操作就困难了。将产生数毫米的弯曲,而且在剥掉为防止加工时在薄膜电路形成面产生伤痕而贴的保护带时,可能引起晶片破裂等问题。在以后切块、焊片、导线连接、封装等工序中,因为晶片和切断后的芯片太薄,也容易产生破裂。另外,由于变薄后的弯曲量,无法完成切块和导线连接。由此可见,通过里面磨削使晶片薄壁化的限度是0.2m。
与上述已有工序相比,如图18B所示的本发明的工序,是在封装后加工LSI芯片的里面,使其薄壁化,这时,LSI芯片厚度可在0.05mm及其以下。采用此方法,虽然使LSI芯片变薄了,但由于封装树脂和引线框架加强了LSI芯片,因此,加工后的LSI芯片很难破裂。这时,半导体装置的厚度在0.25mm以上,对操作和后工序都不会发生问题。
下面,说明加工的存储器的构造。具有代表性的存储器构造,是图19所示的引板构造和图20所示的LOC构造(Lead On Chip)。所谓引板构造,是在引板上配置LSI芯片,LSI芯片2和引线框架1间,用导线34连接。再用树脂4进行密封。当对该引板构造36的存储器进行本发明的薄壁化加工时,由于引板36和引线框架1在LSI芯片2下面,LSI芯片不可能露出在加工面进行加工。这时,加工引板和引线框架下的树脂时,可实现薄壁化,然而,引线框架下的树脂4变薄后,引线成形时,引线框架就被拉出来了,这就成了问题。由此可见,本发明的引板构造存储器,薄壁化效果要小些。图20所示的LOC构造的存储器中,引线框架用粘接带35固定在LSI芯片上,LSI芯片2和引线框架1间用导线34连接。再用树脂进行密封。当对该LOC构造的存储器进行本发明的薄壁化加工时,先除去LSI芯片下面的树脂,再加工LSI芯片的里面(不形成电路的一面),以实现LSI芯片的薄壁化。与此同时,已封装的存储器的整体厚度也就薄壁化了,达到了本发明的目的。
图16是薄壁化加工后的存储器剖面图,图17表示存储器加工面构造。对LOC构造的存储器进行薄壁化加工时,如图16所示,是把LSI芯片的里面作为加工面的露出构造。从加工面可看到的正如图17所示。在LOC构造的存储器进行薄壁化加工时,LSI芯片的里面和树脂是加工对象面。对由可塑材料(树脂)和脆性性材料(LSI芯片)组成的复合材料,用具有代表性的切削加工、磨削加工、抛光加工等机械加工方法,实现薄壁化加工时,担心下面几点。
1.加工时产生的力,破坏LSI芯片(发生断裂)。
2.加工时产生的力,使LSI芯片与树脂的交界面剥离。
3.LSI芯片加工面的表面粗糙度恶化,可靠性下降。
考虑到以上三点,薄壁化加工法加工效率高,表面粗糙度良好,对包含陶瓷材料的复合材料的加工,以磨削加工为中心进行了研究。下面,就薄壁化加工法的实施例予以说明。
(实施例4)
所谓磨削加工法,是用帽型磨石进行平面磨削。用帽型磨石的平面磨削,比用盘型磨石的平面磨削,其加工面粗糙度更好,适用本发明的薄壁化加工法。用帽型磨石进行磨削加工时,有切入磨削式和旋转磨削式。这两种磨削方式是不同的,切入磨削式的表面粗糙度良好,特别有利于硅晶片的大加工物。本发明的薄壁化加工,哪一种加工方式都可以用,这里,采用了表面粗糙度良好的切入磨削。
图8A~8B表示磨削加工的概念图。加工时,在工件架27上固定了数个到数十个(图8是4个)封装后的存储器28。这时,存储器的表面固定在与工件架的粘接面。当由于封装而突出的引线框架进行引线成形折弯时,将妨害加工,因此,应在引线成形前加工存储器。加工工具采用帽型金刚石磨石29。
磨削加工时,使封装后的存储器里面与帽型金刚石磨石29的工作面接触,工件架和帽型金刚石磨石29处于旋转状态,并按图8箭头方向移动磨石(切入),进行加工。
下面,说明实际加工实例。如图21所示,采用LOS构造的TSOP存储器。存储器整体厚度是1mm,可以细分为:LSI芯片上的树脂厚度是0.4mm,LSI芯片2的厚度是0.3mm,LSI芯片下的树脂厚度是0.3mm。该存储器按以下条件进行切入磨削。
加工机:平面磨削机(日立精工株式会社制GHR-SF)
磨削磨石:金属结合剂金刚石磨石
(SD1500P75M)
磨削磨石转数:5000r/分
工作轴转数:300r/分
切入速度:50μm/分
切入量:0.3、0.4、0.5,0.55mm
按以上条件加工TSOP存储器,LSI芯片厚度可达0.05mm,未发生LSI芯片破裂以及树脂和LSI芯片交界面剥离等问题。加工后的LSI芯片里面粗糙度为0.08μm Rmax,近于镜面状态。以热周期试验(-55℃~+150℃,100周期)作为加工后的存储器的可靠性检验,未发生LSI芯片破裂等问题。
如上所述,当加工封装后的存储器里面时,如图17所示,LSI芯片的里面(加工面)需出来了。当这一状态一直延续到引线成形和检查时,可能损伤露出的LSI芯片的里面,使芯片破裂。为此,把聚酰亚胺带贴在加工面,保护LSI芯片。这样,在这种状态下进行引线成形和检查,都未发生问题。
从上述结果可见,对图20所示TSOP存储器进行薄壁化加工,其存储器厚度可为0.45mm,LSI芯片厚度可为0.05mm,是不会有问题的。
下面,说明对图22所示的超薄型存储进行磨削加工的结果。该存储器采用无引线结合技术,在引线框架1和LSI芯片2间没有导线,而用凸出5连接存储器。为了使存储器更薄,采用比原来薄0.05mm的引线框架,封装后,使LSI芯片的里面从树脂中露出来,存储器整体厚度为0.45mm。为使该存储器再薄一些,对存储器里面进行磨削加工使其薄壁化,也进行了研究。
在此类存储器情况下,因为露出了LSI芯片的里面,其切入量和芯片加工量大致相同。因此,很容易把握LSI芯片的加工量。另外,由于LSI芯片的里面露出来了,就不会在LSI芯片倾斜时进行封装,因此在薄壁化加工时,很难产生加工量误差。如上所述,图22所示LSI芯片里面从封装中露出来的存储器,适合薄壁化加工。
加工条件可在与上述TSOP存储器相同条件下进行加工。但是,加工量为0.2mm。加工结果是:加工存储器0.2mm,LSI芯片厚度为0.1mm,未发生LSI芯片破裂、树脂与LSI芯片交界面剥离等问题。加工后的LSI芯片里面的表面粗糙度与以前一样,为0.08μm Rmax,接近镜面状态。把聚酰亚胺带贴在加工面后,进行引线成形和检查时,未发生问题。由于加工后的存储器厚度为0.25mm,非常薄,在LSI芯片表面上有树脂应力,可产生0.06mm的弯曲,但不会出现特别的问题。
从以上结果可见,对图22所示的超薄型存储器进行薄壁化加工后,存储器的厚度可达0.25mm,LSI芯片厚度可达0.1mm,是没有问题的。
在上述封装后的存储器薄壁化加工中,其薄壁化的限度如下。
1)LSI芯片薄壁化的限度
在LSI芯片表面形成的薄膜电路的厚度是:配线层约0.005mm,下面的的活性层约0.001mm。在薄壁化加工时,必须保留该薄膜电路。在薄壁化加工时,LSI芯片薄壁化的限度是:配线层和活性层加起来的0.006mm。实际上,以封装后的存储器为对象,对LSI芯片薄壁化的限度进行了调查,其结果是:LSI芯片的厚度加工到0.01mm时,没有发生LSI芯片破裂等问题。
2)存储器薄壁化的限度
为防止存储器误动作,覆盖LSI芯片表面的树脂厚度约为0.1mm。这样,树脂厚度0.1mm,再加上LSI芯片薄壁化的限度0.006mm,就是存储器薄壁化的限度。因此,存储器薄壁化限度为0.1mm。
(实施例5)
实施例4记述了采用磨削加工的存储器薄壁化加工。通过磨削加工,可使LSI芯片里面大致加工成镜面,然而,在加工面上产生了若干加工变形和微小裂纹。为了消除它们,对磨削加工后的存储器里面再进行抛光加工。
抛光加工大致可分为擦光和抛光。擦光主要是对平面和圆筒面等形状进行粗加工的加工方法,而抛光是可提高表面粗糙度,消除加工面损伤的加工方法。这里,为了消除磨削加工后的加工变形和微小裂纹,进行抛光。以下对抛光加以说明。
图15A~15B表示抛光的概念图。所谓抛光就是把抛光布32贴在抛光平台30上,在抛光布上有流动的抛光液,把加工物的加工对象面按压在上面,然后在加压状态下使抛光平台30旋转。这样,加工物的加工对象面和抛光布32通过抛光液中的磨粒31而滑动,磨粒31可除去加工物表面的微小裂纹。
这里的抛光加工是在经磨削加工薄壁化后,把存储器固定在工作架架如图15所示安装加压圆筒33,进行抛光。
这里所说的存储器,是以图21所示的TSOP存储器和图22所示的超薄型存储器为加工对象。前加工是磨削加工,用与实施例4相同的条件进行加工。但是,磨削加工的加工量,前者是0.5mm,后者是02mm,各LSI芯片加工后的厚度是0.1mm。下面给出抛光加工的条件。
加工机:单面抛光盘(スピ-ドフアム制SH24)
抛光液:胶态二氧化硅(FUJIMI制GLANZOX3900)
平台转数:100r/分
工作轴转数:100r/分
抛光压力:20KPa
抛光布:不织布(ロデ-ルニシタ制Suba400)
按以上条件进行抛光的结果是经过10分钟的加工,即可使LSI芯片里面(加工面)为镜面。在磨削加工后进行的抛光,并未发生LSI芯片破裂、以及树脂和LSI芯片交界面剥离等问题。抛光后的LSI芯片里面的表面相糙度是0.01μm Rmax,为镜面。进行抛光,可以认为除去了磨削加工产生的加工变形和微小裂纹。
(实施例6)
如前所述,磨削加工在加工面可产生若干加工变形和微小裂纹。实施例5为了消除它们,进行了抛光。这里,为了消除磨削加工产生的加工变形和微小裂纹,进行了湿式蚀刻的研究。
硅晶片的蚀刻液有酸性液和碱性液,考虑到对引线框架的腐蚀,进行碱性蚀刻。
这里,加工图21所示的TSOP存储器和图22所示的超薄型存储器。前加工是磨削加工,采用与实施例4相同的条件进行加工。但是前者的磨削加工量是0.5mm,后者是0.2mm,各LSI芯片加工后的厚度是0.1mm。下面给出湿式蚀刻的条件。
蚀刻液:氢氧化钾KOH
蚀刻时间:2分钟
磨削加工后,按上述条件进行蚀刻2分钟后,LSI芯片里面(加工面)被蚀刻0.02mm,蚀刻后的LSI芯片里面的表面相糙度为1.5~2.3μm Rmax。但是,因为是化学除去,可以不考虑蚀刻后的加工变形和微小裂纹。另外,在磨削加工后进行的湿式蚀刻,也未发生LSI芯片破裂、树脂与LSI芯片交界面剥离等问题。
如上所述,可以认为通过湿式蚀刻,消除了磨削加工中在LSI芯片里面产生的加工变形和微小裂纹。
实施例4、5、6等3个实施例,都是以LOC构造的存储器为对象的,然而,对引板构造的存储器,对覆盖在LSI芯片里面的树脂进行加工,也可以实现薄壁化。这里仅以存储器为对象,但与存储器相同的LSI芯片,封装的逻辑半导体LSI等,都同样可薄型化。
采用本发明的半导体器件,可以构成加强了LSI芯片的极薄半导体器件。采用引线框架的一部分除了加强外,还可作为放热部、适当位置部、以及制模树脂的薄型化,还可作为防止由于紫外线等光线引起LSI误动作的遮光部。
一个半导体器件可以是极薄的,叠层配置的多个半导体器件,也可以比通常的半导体器件薄。在插件状机壳等极有限的体积中,可安装多个半导体器件,以构成更高功能的功能电路。
Claims (22)
1.一种树脂制模的引线框架型半导体器件,具有一个金属引线框架和一个制模树脂LSI芯片,其特征在于,金属引线框架的引线通过相应的突起电极与LSI芯片上的多个电极电连接,从而提供减薄了厚度的半导体器件,其中金属引线框架和LSI芯片被树脂制模在器件的表面上,使不形成LSI图形的一面呈露出状态并进行磨削加工。
2.如权利要求1所述的树脂制模的引线框架型半导体器件,其特征在于,所述金属引线框架与所述LSI芯片上的多个电极通过金属工艺彼此连接起来,所述引线框架的总厚度薄,所述引线框架的一部分构成增强片,用以防止所述LSI芯片变形,所述构件的外周边用树脂制模形成,且覆盖住没有所述LSI芯片的电路形成的镜面侧的树脂部分为经过研磨的表面,从而减小所述半导体器件的总厚度。
3.如权利要求1所述的树脂制模的引线框架型半导体器件,其特征在于,所述树脂制模半导体器件的所述引线框架具有多个引线和一个增强件,用于防止所述树脂制模半导体器件的所述LSI芯片变形,所述多个引线与所述增强件隔开,从而使彼引不致电连接,所述多个引线与所述LSI芯片上的所述电极电连接。
4.如权利要求1所述的树脂制模的引线框架型半导体器件,其特征在于,所述树脂制模半导体器件的所述引线框架具有多个引线和一个增强件,用于防止所述树脂制模半导体器件的LSI芯片变形,所述多个引线与所述增强件隔开,从而不致彼此电连接,所述多个引线与所述LSI芯片上的所述电极电连接,结构的外周边是树脂制模的,从而使所述树脂制模半导体器件的所述LSI芯片的后表面露出来。
5.如权利要求1所述的树脂制模的引线框架型半导体器件,其特征在于,所述金属引线框架和所述LSI芯片用金属工艺通过至少一个突起电极直接连接。
6.如权利要求3所述的树脂制模的引线框架型半导体器件,其特征在于,所述多个引线配置在所述LSI芯片的周边部位,所述增强件经树脂制模部分配置在所述LSI芯片的中心。
7.如权利要求3所述的树脂模制的引线框架型半导体器件,其特征在于,所述多个引线和所述增强件配置得使其从所述LSI芯片计起的长度相同。
8.如权利要求4所述的树脂制模的引线框架型半导体器件,其特征在于,所述多个引线配置在所述LSI芯片的周边部位,所述增强件通过树脂制模部分配置在所述LSI芯片的中心。
9.如权利要求4所述的树脂制模的引线框架型半导体器件,其特征在于,所述多个引线和所述增强件配置得使其从所述LSI芯片计起的长度相同。
10.如权利要求2所述的树脂制模的引线框架型半导体器件,其特征在于,所述多个引线配置在所述LSI芯片的周边部位,所述增强件通过树脂制模部分配置在所述LSI芯片的中心。
11.如权利要求2所述的树脂制模的引线框架型半导体器件,其特征在于,所述多个引线和所述增强件配置得使其从所述LSI芯片计起的长度相同。
12.如权利要求2所述的树脂制模的引线框架型半导体器件,其特征在于,所述金属引线框架和所述LSI芯片上的所述电极用金属工艺直接与一个突起电极连接。
13.如权利要求1所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是经磨削加工使半导体器件整体薄型化的半导体器件,而且,是对磨削加工后的磨削加工面再进行湿式蚀刻加工的半导体器件。
14.如权利要求1所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是薄型化的半导体器件,而且是对磨削加工后的磨削加工面用抛光布和抛光磨粒进行抛光加工的半导体器件。
15.如权利要求1所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是在不形成LSI芯片电路的一侧,进行薄型化加工的半导体器件。
16.如权利要求15所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是把密封材料作为加工对象的半导体器件。
17.如权利要求15所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是把密封材料及LSI芯片作为加工对象的半导体器件。
18.如权利要求15所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是把进行了LSI芯片的薄型化加工的面显露出来的半导体器件。
19.如权利要求15所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是在进行了薄型化加工的面上覆盖了塑料的半导体器件。
20.如权利要求15所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是加工后的LSI芯片厚度在0.006mm到0.15mm范围的薄型化半导体器件。
21.如权利要求15所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是是加工后的厚度在0.10mm到0.30范围的薄型化半导体器件。
22.如权利要求1所述的树脂制模的引线框架型半导体器件,其特征在于,所述半导体器件是在不形成LSI芯片电路的一侧,进行磨削加工,此后,再进行抛光加工的半导体器件。
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JP204852/94 | 1994-08-30 | ||
JP209552/94 | 1994-09-02 | ||
JP209552/1994 | 1994-09-02 | ||
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1995
- 1995-08-28 KR KR1019950026954A patent/KR100209782B1/ko not_active IP Right Cessation
- 1995-08-30 CN CN95117176A patent/CN1073284C/zh not_active Expired - Fee Related
- 1995-09-27 TW TW084110092A patent/TW353225B/zh not_active IP Right Cessation
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1997
- 1997-03-31 US US08/829,144 patent/US5811877A/en not_active Expired - Fee Related
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US5021865A (en) * | 1988-09-08 | 1991-06-04 | Mitsubishi Denki Kabushiki Kaisha | Lead frame for semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
CN1127429A (zh) | 1996-07-24 |
US5811877A (en) | 1998-09-22 |
KR960009133A (ko) | 1996-03-22 |
KR100209782B1 (ko) | 1999-07-15 |
TW353225B (en) | 1999-02-21 |
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