CN1323064A - 板状体及半导体装置的制造方法 - Google Patents
板状体及半导体装置的制造方法 Download PDFInfo
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- CN1323064A CN1323064A CN01103213A CN01103213A CN1323064A CN 1323064 A CN1323064 A CN 1323064A CN 01103213 A CN01103213 A CN 01103213A CN 01103213 A CN01103213 A CN 01103213A CN 1323064 A CN1323064 A CN 1323064A
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Abstract
通过形成第1垫55,系垫59等导电膜的板状体50或经第1垫55,系垫59等导电膜形成半刻蚀的板状体50,可以利用半导体厂的后工序制造混合IC。而且因为可以不采用支撑底板制造,所以作为混合IC,可以制造薄型,散热性优良的混合IC。
Description
本发明涉及板状体及半导体装置的制造方法,尤其涉及解决传统的混合IC的各种问题的板状体。
历来,装在电子设备内的电路装置为用于便携电话,便携式计算机等,要求小型化,薄型化,轻量化。
作为该电路装置多用混合IC,作为底板主要采用陶瓷底板,金属底板,印刷电路板或软性底板。
图17是示出其一例的图,以下说明其具体的结构。
首先有前述的底板1,在底板1上导电图形用Cu形成。该导电图形是系垫2,连接垫3,外部引出用电极4,芯片电阻或芯片电容等无源元件9连接用的固着垫5,以及与这些垫构成一体的配线6等,根据混合IC电路按照所希望形状图形化。
而且在前述系垫2上固着半导体元件7,把半导体元件7上的连接电极和前述连接垫3用金属细线8电连接。前述无源元件9经焊锡等焊料,银膏等与固着垫5固着,在垫4上经前述焊料或银膏固着外部引线10。而且考虑耐环境性,通过树脂密封等方法进行密封。在这里底板1的整个面上通过模子形成绝缘性树脂11。
也有用标准框20,实现混合IC的,图18是用标准框20实现图17的图形的。
在小岛21上固着半导体元件22,在小岛21的近旁配置的连接垫23和前述半导体元件22经金属细线24实现电连接。
也有在连接垫23中与配线25一体构成的,例如与引线端26电连接。这引线端26例如沿着标准框20的侧边设计多个。此外符号27是无源元件,符号28是为固着前述无源元件27的固着垫。
可是前述的图17的混合IC由于采用底板1,使只在底板部分的混合IC的厚度增厚,其重量也增加。成本的进一步降低有限度。尤其是为了在底板上形成由Cu箔构成的前述导电图形2到6,贴着Cu箔后附加图形化工序,所以具有该图形的底板1的成本使混合IC的价格上扬。况且为了形成导电图形2到6作为支撑底板利用底板1,底板1成为必要的。
通过用底板,使得安装好的半导体元件,无源元件等的散热成为问题。例如,印刷板,陶瓷底板及软片由绝缘材料构成,即使想经底板在安装好的底板上散热,也因为其热传导率差,所以密封的半导体元件,无源元件的热不能很好地向外部散出。即使是散热优良的金属底板,考虑与导电图形的短路,在金属底板表面涂复绝缘性树脂,这产生热阻。尤其是如果半导体元件的温度降低,则尽管可以更加提高驱动能力,但由于前述散热差,不能充分利用半导体元件的潜力。
混合IC与封装的分立元件,封装的半导体芯片不同,装载了大量的有源元件,无源元件,而且多用电连接这些元件的配线。而且由于装好的元件数不同,底板尺寸大,其上设置的配线长度变得很长。必须考虑翘曲等的变形。为了实现轻薄短小倾向,即使实现导电图形的细微化,但为了支撑而不使该细长的配线产生翘曲等变形,其问题是仍然需要支撑底板。
如果进一步考虑制造工序,则混合IC的制造厂把预定的图形数据转告底板制造厂,底板制造厂进行图形化,制造底板,随后混合IC制造厂购入已完成的底板,所以一直到制造混合IC为止,要花费非常多的时间。因此混合IC的制造厂不能在短的交货日期内把前述混合IC交付给用户,这也是问题所在。
采用图18的标准框20的混合IC,除了有图17已述的问题之外,还有如下诸问题。
标准框20通过印刷或刻蚀从表到里冲压形成。因此,引线端26或小岛21不能零零散散,应采取相应的措施。即在引线端26上设置系条29,小岛21设置吊线30。该系条29或吊线30本来并非必要,其问题是在模压后必需有拆除工序。
由于配线25是细长延伸,所以为了防止该配线也产生翘曲等变形,必须用吊线31。因此,如前所述,必需吊线31的排除工序。而且这些吊线30,31在形成其它配线,垫或小岛时造成障碍。尤其是为了回避配线的交叉。必需复杂的图形。
由于标准框20通过刻蚀或印刷从表到里逐渐冲压,因此也有问题,引线图形的细微化有界限。即使是图17的导电图形,这也是同样的。
例如在用印刷形成标准框20时,可以说冲裁的引线间隔与标准框的厚度大体相同的长度就是其界限值。因为通过刻蚀形成的标准框也只有厚度那种程度在纵向进行刻蚀,在横向方向也进行相同程度的刻蚀,所以说标准框的厚度是引线间隔的界限。
由此想要对标准框的图形进行微细化,则有必要使标准框的厚度减薄。可是如果标准框20本身的厚度变薄,则其强度降低,在标准框20上发生翘曲,使引线端26变形,产生移位。尤其是由于与金属细线24连接的连接垫23没有支撑,所以有发生变形,翘曲等问题。
而且如图18箭矢所示的部分是引线端26从封装的侧面引出处,引线端26和引线端26之间的空隙并不能用上金属模32和下金属模衔接,不能免除毛刺的发生。
如上所示,标准框在微细加工有限界,不能使封装总尺寸作得更小,可是如果为考虑工艺过程,则必须有防止标准框翘曲的方法,同时必须有消除毛刺的工序,由于必须切除吊线7和系条8,所以除了工艺过程复杂外,系条的切除工序中的引线变形或冲制问题成为半导体装置的可靠度低下的原因。
本发明的目的是鉴于前述诸多任务提供在微细化期间具有极高可靠性容易制造的标准框用板状体以及用此板状体的半导体装置。
本发明,第1,是具有由平坦面构成的第1表面和前述第1的表面对置的由平坦面构成的第2表面的板状体。
前述第2表面上通过与设置在半导体元件装载区或其近旁的多个第1垫相当的图形掩模的形成解决的。
如果采用这种结构,通过已形成的掩模用户只用腐蚀可以很容易地形成标准框。此外,搬运时由于是一般的板状体,不用担心受损伤,也不担心翘曲和变形,所以可能提供极容易处理的标准框。
第2,其特征为,前述掩模是导体膜。
第3,其特征为,前述掩模是光刻胶,该板状体也可以是双层构造。这时,第1次刻蚀后,半导体元件装载区等除去部分光刻胶,通过第2次刻蚀,也极容易形成,以便使系垫(半导体元件装载部)和引线端的连接垫的之间的水平面不同。
第4,其特征为,形成前述掩模直到与前述第1垫上连续形成的配线相当的区域为止。
第5,通过把前述第1垫作为连接垫或软焊料孔固着用垫利用解决。
第6,通过在前述半导体装载区上设置与系条实质同一图形的导电膜或光刻胶解决。
第7,通过在前述第2表面上形成与无源元件用的固着垫及/或外部引出用的电极实质同一的图形的导电模或光刻胶解决
通过对在板状体上形成的导电图形进行半刻蚀,可以形成由板状体支撑的导电图形。由此混合IC制造厂通过有光蚀刻设备,可以独自地从板状体直到混合IC连贯到底制造。
半导体元件的固着,使用金属细线的电连接,使用绝缘性树脂的密封工艺,可以采用该板状体做支撑底板,不要作为传统方式的支撑底板的底板。尤其是连接垫,系垫(小岛)以小岛状存在,以不稳定状态下配置,而由于与板状体呈一体,所以可以没有翘曲的变形。配线也可以长长地延伸,发生翘曲、扭弯曲,但由于与板状体呈一体,所以可以解决这些问题。
经导电膜,并非板状体从表到里一贯到底对垫进行印刷或刻蚀,而是通过在中途终止,可以使垫或配线等的间隔狭窄,形成更细微的图形。此外,密封绝缘性树脂,完全固着后,通过研磨或刻蚀板状体的第1面,可以使垫,系垫及配线分离,可以配置在没有位置偏移的预定位置上,而且即使使配线长长地绕行,也可以无变形配置。
第8,其特征为,前述无源元件是芯片电阻或芯片电容器。
第9,其特征为,前述板状体的对置的侧边上形成导向孔,用于插入与导向销实质同一的图形或前述导向销。
第10,其特征为板状体是由压延金属构成的。
第11,用导电箔构成前述板状体,由与前述导电箔材料相异的材料构成前述导电膜解决的。
通过与导电箔材料相异的材料构成前述导电膜,可以采用前述导电膜作刻蚀掩模。此外可以作为边沿形成导电膜,在导电图形上也可能具有固定的效果。
第12,是具有由平坦面构成的第1表面和以所希望高度形成的凸部,以及与前述第1表面对置构成的第2表面的板状体。
前述凸部通过在半导体元件装载区及其近旁构成多个第1垫解决的。
第13,前述凸部通过构成与前述第1垫一体设置的配线解决的。
第14,前述凸部通过构成与前述配线一体设置的第2垫解决的。
第15,前述第1垫及/或前述第2垫作为连接垫或软焊料孔固着用垫利用解决的。
第16,前述凸部通过构成在前述在半导体元件装载区设置的系垫解决的。
第17,前述凸部通过构成无源元件用的固着垫及/或外部引出用电极构成
用凸部构成导体图形的板状体用半导体工厂的后续工序的设备进行半导体元件的安装与垫的电连接及密封等成为可能。因此与传统的标准框同样,例如由标准框工厂供给板状体,半导体工厂可以制造混合IC。
半导体元件的固着,用金属细线的电连接,用绝缘性树脂的密封可以采用该板状体做支撑底板,可以不要作为传统的方式的支撑底板的底板。尤其是连接垫,系垫(小岛),呈小岛状存在,在不稳定状态下配置,由于与板状体一体,所以可以没有翘曲等变形。配线长长地延伸,即使产生翘曲,扭曲等变形,也由于与板状体一体,所以可以解决这些问题。
经导电膜,并非从板状体从表到里对垫一贯到底进行印刷或刻蚀,由于用半刻蚀构成,所以可以使垫或配线等的间隔变狭,可以形成更微细的图形。由于垫,电极或系垫与板状体一体构成,没有变形或翘曲等,所以不要系条,吊线。此外绝缘性树脂密封,完全固着后,通过研磨或刻蚀板状体的里面可以分离垫,系垫,及配线,可以在没有位置偏移的预定位置上配置。
第18,其特征为,前述无源元件是芯片电阻或芯片电容器。
第19,其特征为,在与前述的板状体对置的侧边上,形成导向孔,用于插入与导向销实质同一的图形或前述导向销。
第20,其特征为,在前述的板状体上由前述凸部构成的图形作为一单位的单元矩阵状配置。
第21,在前述凸部上面,通过形成与构成前述凸部材料相异的材料的导电膜解决的
第22,在前述凸部侧面,通过具有固定构造解决。
第23,前述导电膜在由前述凸部上面构成沿边解决。
第24,通过由Ni,Au,Ag或Pd形成前述导电膜解决
例如,如果采用Ni,Au,Ag或Pd做导电膜,则该导电膜可以作为刻蚀掩模代用,在凸部侧面上构成弯曲构造,而且在其表面可以用前述导电膜形成沿边。此外可以用该材料一次实现金属细线的连接,半导体元件的固着。
第25,具有与树脂密封区对应的整个面呈平坦的第1面以及形成成为配线的凸部的第2面的板状体,该配线由前述第1面以预定厚度的片状形成的,包围衔接上金属模的区域上在半导体元件装载区或其近旁设置的多个第1垫及与前述第1垫一体设置的。
至少通过由衔接前述上金属模区域包围的区域构成由前述第2面及前述上金属膜的密闭空间解决的。
第26的半导体装置制造方法具有由平坦面构成的第1表面和与前述第1表面对置设置的,由平坦面构成的第2表面,其特征为,具有以下工序,即:
在前述的第2表面上形成与半导体元件装载区或其近旁设置的多个第1垫相当的图形的掩模的板状体的准备工序,
经前述掩模,通过对前述第2表面的一部分刻蚀,除去与前述第1垫相当的区域,降低前述第2表面的水平面,在与前述第1垫相当的区域上,形成凸部的工序,
在前述半导体元件装载区装载半导体元件的同时,经前述第1垫进行电连接的半导体元件的装载工序。
把前述板状体装载在金属模上,在由前述板状体和前述上金属模构成的空间填充树脂的工序,
除去前述填充的树脂里面露出的板状体,使前述凸部各自分离的分离工序。
第27,其特征为:它包含以下工序,在形成前述凸部的工序之后,除去前述半导体元件装载区的掩模,接着通过刻蚀,降低前述半导体元件装载区的水平面,以便使其处于在前述凸部表面和除去前述凸部区域的水平面之间,构成前述半导体元件的装载面比连接垫的水平面还低。
为了防止由于对连接线芯片的接触产生的短路,众知有降低系垫水平面的结构,而用该法通过选择性除去掩模,可以极容易实现。
第28,准备具有与树脂密封区对应的整个面呈平坦的第1面,以及形成为配线的凸部的表面的板状体,该配线由前述第1面以预定厚度的片状形成的,被衔接上金属模的区域包围的区域上在半导体元件装载区或其近旁设置的多个第1垫及与前述第1垫一体设置的,
在前述半导体元件装载区装载半导体元件的同时,电连接前述第1垫和前述半导体元件,
把前述板状体装载在金属模上,在由前述板状体和前述上金属模构成的空间内充填树脂,通过除去在前述填充树脂第1面露出的板状体,使前述凸部各自分离的工序来解决。
第29,通过与前述树脂密封区对应的前述板状体的第1面的整个区域对下金属模衔接解决的,
由于板状体片状形成,所以板状体的第1面与下金属模全面衔接,而且由于垫等导电图形配置在前述密封空间内,所以不全完全排除在本发明应解决的任务中所述的毛刺。
根据这些制造方法,由于用导电图形,半导体元件及使其些密封的绝缘性树脂构成,可以没有底板,因此可以实现半导体装置的薄型,轻量化,而且由于埋入导电电路,导电电路也不会从绝缘性树脂剥离。通过在导电箔表面形成导电膜,在表面上可以形成有沿边的引线、小岛,可以产生固定的效果。
第30,其特征为,前述下金属模的衔接区由分散真空吸附手段配置。
希望在导电电路上用压延体。
根据本发明,作为用于形成导电电路图形的导电板的一块板状体为原材料,由于通过对其冲裁加工或半刻蚀加工形成分离沟,形成导电电路,所以可以形成片电阻小,致密且表面平坦度高的导电电路。从而连接精度高,即使在高集成度化的电路装置的安装时也可以实现高精度和高可靠性。
尤其是通过用金属压延体,粒界随机配置,可以形成片电阻小,致密,从微观看平坦度高的导电电路。
附带地说,在镀膜的情况下,作为导电电路,可以获得足够膜厚程度那样厚厚地形成时,膜厚偏差大,不能获得表面的充分平坦性。例如想形成20-35μ程度的镀膜,则膜厚的偏差大,连接强度大幅度降低。与此相反,如本发明所示,刻蚀铜等的压延金属形成时可获得极平坦,连接强度及连接精度高的电路装置。
在镀膜的情况下,通过把镀膜成长面作成镜面,除去支撑体,如果想把成长面一侧作连接面使用,则有可能改善平坦性。但是与用铜等金属压延体的情况相比,精度大幅度降低。
附图的简单说明。
图1是说明本发明的板状体的图。
图2是说明采用本发明的板状体的半导体装置制造方法的图。
图3是说明采用本发明的板状体的半导体装置制造方法的图。
图4是说明在板状体上形成导电图形的图。
图5是说明本发明的板状体的图。
图6是说明本发明的板状体的图。
图7是说明采用本发明的板状体的半导体装置制造方法的图。
图8是说明采用本发明的板状体的半导体装置制造方法的图。
图9是说明采用本发明的板状体的半导体装置制造方法的图。
图10是说明采用本发明的板状体的半导体装置制造方法的图。
图11是采用本板状体作为标准框的图。
图12是进一步说明本发明板状体的图。
图13是说明本发明板状体的图。
图14是说明本发明板状体的图。
图15是说明本发明板状体的图。
图16是说明本发明板状体的图。
图17是说明传统的混合IC安装的图。
图18是使用传统的标准框实现混合IC的图。
说明板状体的第1实施例
图1A是示出通过比传统的IC或采用标准框的混合IC可实现在微细化期间可靠性更佳,更薄型的封装的板状体。
该板状体50,如图1A所示,其传统的混合IC的图形是由导电膜56形成的。
即板状体50具有由平坦面构成的第1表面52,以及与前述第1表面52对置设置的,由平坦面构成的第2表面53。
在前述第2表面53上形成与在半导体元件装载区54或其近旁设置的多个第一垫55实质同一的图形的第1导电膜56。
该板状体50,也可以形成光刻胶等耐刻蚀掩模取代前述导电膜。这时,至少与连接垫对应的部分形成导电膜,整个图形被光刻胶涂复。
本发明的特征在于前述板状体。正如以后的说明所判明的那样,经板状体50的导电膜56或光刻胶,进行半刻蚀,把半导体元件57装载其上,用绝缘性树脂密封。而且直到前述第1垫55分离为止,对在绝缘性树脂58的里面露出的板状体50进行刻蚀,研磨或研削等加工。通过采用该制造方法,可以由半导体元件57,第1垫55,埋入该第1垫55的绝缘性树脂58的3种材料构成。而且该板状体最终可以作为混合IC发挥功能。
本构造的最大特征是在板状体50的表面形成耐刻蚀的掩模,以便进行半刻蚀。
一般刻蚀是在随着纵向进行刻蚀,在横向也进行刻蚀,例如在各向同性刻蚀情况下这种现象显著出现,纵方向的刻蚀深度和横方向的刻蚀长度实质上是相同的。在各向异性,横方向的刻蚀长度比各向同性少许多,而在前述横向进行刻蚀。
即,如果冲裁图形以便从表到里贯通标准框,则导电图形间在横方向刻蚀,第1垫55和相邻的导电图形之间隔不可能比某界限值还小,难以形成微型图形。
而且在板状体50上形成导电模56或光刻胶,如果其后进行半刻蚀,则由于纵方向的刻蚀深度变浅,可以控制横方向的刻蚀量,可以实现更微细的第1垫55。
这在其它导电图形,例如系垫59,配线60,固着垫61以及外部引出用电极也是同样的。配线60的连接。例如固着垫61和外部引出用电极62之间。以下把把这些总称为导电图形。
例如2盎司(70微米)厚度的板状体50上作为图形化的导电膜形成Ni,Ag,Au或Pd等的导电膜56,如果以此做掩模直到完全贯通进行刻蚀,则导电图形的间隔是最狭的,实质上为70微米。可是把导电膜56作为耐刻蚀掩模充分利用,如果把板状体50刻蚀到35微米的深度,则导电图形的间隔实质上可以狭窄加工到35μm。即可以实现2倍的安装效率。该微细图形对板状体的半刻蚀深度越浅,则可能实现更微细的图形。
在本发明的板状体50,如果考虑刻蚀设备,大量生产性,制造成本,则最好采用湿刻蚀。可是湿刻是各向异性的。在横方向的刻蚀较多。从而,使用导电膜56或光刻胶的半刻蚀在更细微的导电图形形成中很出色。
由于导电图形通过经导电膜56或光刻胶通过刻蚀显现,与片状的板状体50一体构成,所以不要系条,吊线的形成。由此用绝缘性树脂58密封后,也可以不要去除系条工序或切割吊线的工序。
在本发明的板状体50,由于导电图形与板状体50一体形成,所以只要固定板状体,则导电图形没有畸变,翘曲。
从而其特征为:也可以稳定对第1垫61的连接。况且由于不要吊线,没有必要考虑与吊线的交叉,其优点是可以在任意的位置上配置导电图形。
此外,如果在板状体50上设置导向孔63,则在把板状体50装载在金属模上时是便利的。
该导向孔63是与导销实质上具有同一形状,在对应的位置上,也可以用导电膜或光刻胶形成呈圆形的图形,也可以在模压前,沿该图形用钻孔,冲孔或刻蚀等开口。也可以预先准备好开口。通过在该导向孔63插入金属模的导销,可以实现位置精度高的模压。
正如以前所述,导电图形经导电膜56或光刻胶通过刻蚀显现,作为传统的标准框也可以采用它。
半导体装置厂一般分为前工序和后工序,有车间,采用本板状体50,在模压后工序中,通常不设置刻蚀设备。从而通过设置导电膜的成膜设备,刻蚀设备,从标准框工厂购入形成导电膜或光刻胶的板状体,半导体厂可以制造用该板状体的混合IC
说明板状体的第2实施例
如图1B所示,该板状体50经前述导电膜56进行半刻蚀,导电图形呈凸形形成的。此外,也可以取代导电膜使用光刻胶进行半刻蚀。
即,具有由平坦面形成的第1表面52包含按照所希望高度形成的凸部70,与前述第1表面对置而成的第2表面的板状体50。
前述凸部70是在半导体元件装载区54或其近旁构成多个第1垫55的。
本板状体55实质上是与第1实施例说明的板状体的构成,效果相同的。不同点仅在于导电膜进行半刻蚀。
因此,在这里阐述半刻蚀。即,半导体厂,尤其在后工序并不配备有Cu板状体的电镀设备,以及刻蚀等的光刻技术设备。因此通过半刻蚀,如果购入具有凸部结构的导电图形的板状体,则可以与传统的标准框同样处理,使得用原有的后工序设备制造成为可能。
说明采用板状体的半导体装置的制造方法的第3实施例。
采用前述的板状体50,采用图1到图3说明半导体装置73的制造。
首先准备好图1的板状体50。该板状体的第1表面52,第2表面53是平坦的,况且在第2表面上形成对导电图形取形的导电膜56或光刻胶。导电图形是用斜线划影阴36部分。在用光刻胶代替导电膜时,在光刻胶的下层至少与连接垫对应部分形成导电膜(以上参阅图1A)。
经前述导电膜56或光刻胶对板状体50进行半刻蚀。刻蚀深度可以比板状体50的深度还浅。刻蚀深度越浅,则越可以形成微细的图形。
而且通过半刻蚀,如图1B所示,在板状体50的第2表面出现呈凸状的导电图形。板状体50也可以是Cu-Al的层叠体,Al-Cu-Al层叠体。尤其是Al-Cu-Al层叠体可以防止因热膨胀系数差产生的翘曲。
例如,在半导体厂,如果在后续工序有刻蚀设备,则从标准框厂购入图1所示的板状体50,如果在后工序没有刻蚀设备,则进行半刻蚀,通过购入导电图形呈凸状的板状体50,不引进任何设备,用原有的设备也可以容易地移位到以下的工序(以上参阅图1B)
接着,半导体元件57固着在半导体装载区57上,第1垫55和半导体元件57的连接电极进行电连接。在附图上由于用正面朝上安装半导体元件,所以作为连接手段采用金属细线71。
在该连接,第1垫55与板状体50呈一体,而且,板状体50的里面由于是扁平的,所以用焊接机的桌上在面上垫接。从而如果板状体完全固定在焊接桌上,则也无第1垫55的位置偏移,可以高效地把焊接能量传递给金属细丝和第1垫55,可以提高金属细丝的焊接强度。焊接桌的固定例如可以在整个桌面上设置多个真空吸气孔。
在采用正面朝下型的半导体元件时,配置半导体元件57上的电极,以便形成焊锡球,Au或焊锡等的凸起,在其正下面,第1垫55来到,两者固着。
在固着的垫61上,无源元件72经焊锡等的焊料,Ag膏等的导电膏等固着。在这里可以采用的无源元件是芯片电阻,芯片电容器,印刷电阻,线圈等。
形成绝缘性树脂58,以便覆盖前述导电图形,半导体元件57及连接装置。
例如用金属模密封时,在这阶段,开导向孔63,在这里插入金属模的导销,实现高精度的板状体50的配置。由于板状体50的第1表面52是平坦的,所以下金属模的面也是平坦地形成。
接着注入绝缘性树脂58。作为绝缘性树脂可以用热可塑性,热固化性中的一种。
通过传递模,注射模,翻转模或涂布可以实现。作为树脂材料,环氧树脂等的热固化性树脂可以用传递模实现。液晶聚合物、对聚苯硫等热可塑性树脂可以实现注射膜。
在本实施例,调整绝缘性树脂的厚度,以便从金属细线71的顶部开始涂复约100μm。该厚度考虑半导体装置的强度,厚些,薄些也是可能的。
在注入时,由于导电图形与片形的板状体50一体形成,所以只要没有板状体50的偏移,则完全没有导电图形的位置偏移。
在这里下金属模和板状体50里面的固定用真空吸引法实现。
以上,在绝缘性树脂58内埋入作为凸部形成的导电图形,半导体元件,在凸部下方的板状体50在里面露出(以上参考图2)。
接着除去在前述绝缘性树脂58的里面露出的板状体50,使导电图形各个分离。
该分离工序考虑各种方法,也可以通过刻蚀里面去除,也可以用研磨,研削刮入。也可以两者都采用。例如一旦刮入到绝缘性树脂58露出为止,则存在的问题是:板状体50的切削渣或在外侧薄薄地脱落的毛刺状金属会侵入绝缘性树脂58内。因在虑到露出绝缘性树脂58之前,停止削入。其后如果通过刻蚀使导电图形分离,则可以完全没有板状体50的金属侵入位于导电图形间的绝缘性树脂内。由此可以防止微细间隔的导电图形相互间的短路。
用半刻蚀,因刻蚀深度的偏差在绝缘性树脂厚度上产生偏差。因此由导电图形形成的引线分离后,通过用研磨或研削,削入到预定厚度,可以形成高精度具有一定厚度的封装。
而且在多个形成为半导体装置73的1单元的情况下,在该分离工序后,作为各个半导体装置60具有切成小块工序。
这里采用切块装置使各个分离,而即使是巧克力薄片也可以印刷或切割(以上参阅图3)。
根据以上制造方法,依靠多个导电图形,半导体元件57及绝缘性树脂58的三要素可以实现轻薄短小的封装。
其次,说明由以上制造方法产生的效果。
首先,第1,由于导电图形进行半刻蚀,与板状体一体构成,支撑,所以没有作为传统支撑底板用的底板。
第2,由于板状体半刻蚀形成为凸部的图形,所以使导电图形的微细化成为可能。从而可以使导电图形宽度和导电图形间隔变狭,可以形成平面尺寸小的封装。
第3,由于用前述三要素构成的,可以在最小限下构成,可以尽可能不浪费材料,实现大幅度控制成本的薄型半导体装置73。
第4,系垫59,配线60,垫55,61用半刻蚀形成凸部,由于在密封后进行各自的分离,所以不要系条,吊线。因此系条(吊线)的形成,切割在本发明中都不要。
第5,形成凸部的导电图形在埋入绝缘树脂后,由于从绝缘树脂的里面除去板状体,分离引线,所以可以没有如传统的标准框那样和引线间产生的树脂毛刺。
第6,因为从绝缘性树脂58的里面露出半导体元件的里面,所以可以更高效,从半导体装置里放出从半导体装置73里产生的热。
图4是说明导电图形一例的图。由于混合IC有源元件,无源元件作为IC电路发挥功能,设置了金属细线或配线。
这里作为半导体元件多个形成晶体管57A,IC元件57B等,无源元件72根据需要形成。在该元件周围,为电连接,形成垫55A…,55B,…。配线55以各种形态形成。例如与第1垫55B一体设置的配线60按照所要求的电路长长延长,以便从半导体装置一端到另一端或迂回焊接区57。
这样,配线55具有各种各样的,短的,长的,作为电源用宽度宽的,作为信号输出入用细长的。而且由于与标准框不同,这些配线的特征为,由于与板状体一体构成,密封后分离,没有翘曲等的变形。此外还有特征为使侧面作成弯曲形,由于可以用导电图形上的导电膜形成边沿,所以可以制止从绝缘性树脂来的冲出配线。
说明板状体的第4实施例
图5是与第1实施例同样示出由导电膜CF形成图形的板状体80的图。也可以用形成光刻胶取代导电膜。这时,在光刻胶的下层在与光刻垫对应的部分上形成导电膜。由于用图12说明详细的的形状,所以在这里只作大概的说明。
图5的图形是图1更具体化的图形,具体讲,在用点线包围的导电图形上构成半导体装置的图形单元83是矩形状形成,金属模衔接区84呈环状具有预定宽度形成,以便包围它。即,是示出在一个空腔内形成的图形的。
在该金属模衔接区84的内侧,设置定位标志85,86。连接定位标志85A和86A的线表示横向的划线,而连接定位标志85B和86B的线表示纵向的划线。各定位标志至少由一根短直线形成,以该直线为基准,调整划线装置的刀刃的方向。这里定位的标志设置所希望的间隔(裕度),由两条直线构成,以便按所希望的精度切削刀刃。
在前述的金属模衔接区84的外侧上形成用于形成导向孔的第1图形87,第2图形88。第2图形88的十字是在用钻形成导向孔时的定心标志。也可以不形成该图形而预先设置与第1图形同一形状的导向孔。
以上由于除了划线标志,金属模衔接区84之外,都与第1实施例相同,所以省略本实施例的特征和效果。
说明板状体的第5实施例
本板状体90是具有图6所示的形状,经第4实施例所示的导电膜CF或光刻胶进行半刻蚀的。
本板状体90可能在传统的标准框,例如SIP,DIP,QIP等内应用。除了导电图形,金属模衔接区84之外的区域进行半刻蚀。但是不一定要形成系垫,考虑散热性也可以省略。第1定位标志87,第2定位标志88也可以通过半刻蚀呈凸状形成。
即由平坦面构成的第1表面91和具有以所希望高度形成的凸部92并与前述第1表面91对置形成的第2表面93的板状体构成。
前述凸部92构成设置在半导体元件装载区95或在临近半导体元件装载区95的多个第1垫93。
其特征为本板状体90处于对各图形进行半刻蚀的状态,原封不动地可以进行半导体元件的固着,电连接,密封,可以用后工序的原有设备制造。
因为其效果在第1实施例,第4实施例说明,在这里省略。
说明半导体装置制造方法的第6实施例
以下使用图5到图12说明制造方法。
首先如图5所示,准备好板状体80。考虑该板状体的焊料的附着性,焊接性,电镀性选择其材料,作为材料,采用以Cu做主材料的导电箔,以Al做主材料的导电箔或由Fe-Ni等的合金制成的片状导电箔,Cu-Al的层叠体,Al-Cu-Al的层叠体。而且在该板状体80的表面上通过导电膜或光刻胶形成第1固着垫93,系垫82,配线4,金属模衔接区84,定位标志85,86,图形87,88。
导电箔的厚度,如果不考虑以后的刻蚀,最好用10μm到300μm的量级。在这里用70μm(2盎司)的铜箔。而且即使在300μm以上,10μm以下基本上也行。(以上参考图5)
接着比板状体80的厚度还浅地除去至少形成第1固着垫93,系垫82,配线4,金属模衔接区84,定位标志85,86,图形87,88区域的板状体80。
这里作为耐刻蚀掩模使用导电膜CF或光刻胶,通过刻蚀,如图6所示,形成比板状体80的厚度还浅的分离沟100。
在本制造方法其特征为:用湿刻蚀或干刻蚀进行非各向异性刻蚀,其侧面成粗糙面,而且是弯曲的。
在湿刻蚀情况下腐蚀剂一般采用氯化铁或氯化铜,前述导电箔在该腐蚀剂内浸渍或该腐蚀剂喷淋。
尤其是成为刻蚀掩模的导电膜CF或光刻胶的正下面进行横方向刻蚀,比其深的部分进行横向刻蚀。由此随着从分离沟100的一侧面向上方,因为与其位置对应的开口部的孔径变小,构成倒锥形,成为具有固定锚构造的的构造。此外通过采用喷淋,进行向深度方向的刻蚀,由于抑制横方向的刻蚀,该固定构造显著呈现。
在干刻蚀情况下,可以各向异性,非各向异性刻蚀。现在不能用反应离子刻蚀除去Cu,但可以用溅射除去。根据溅射条件可以进行各向异性,非各向异性刻蚀。
作为导电膜考虑的材料有Ag,Au,或Pd等。而这些耐蚀性导电膜的特征为可以作为系垫,焊接垫原封不动地利用。
例如Ag膜与Au焊接,也可以与焊料焊接。由此如果在芯片里面涂复Au膜,则可以把芯片原样热压在系垫82上的Ag膜上,经焊锡等焊料可以固着芯片。由于Ag的导电膜上可以粘接Au细线,所以也可以线焊接。从而其优点为可以把这些导电膜原样作为系垫,焊接垫利用(以上参照图6)
如图7所示,具有在形成分离沟100的系垫82上各安装半导体元件101的工序。
作为半导体元件101有晶体管,二极管,IC芯片等。厚度变厚,也可以安装晶片规模型的CSP,BGA等的SHD(含面向下半导体元件)或倒装片等。这里裸晶体管100在系垫82上焊片连接,经由晶体管101上的焊接垫和第1垫93热压接的球焊接或通过超声波的楔形焊接等固着的金属线102进行连接。
图示的第1垫93其尺寸非常小,与板状体90成一体。由此,其优点是可以传递焊接工具的能量,提高焊接性。在焊接后的金属细线切割,有时牵引切割金属细线。这时由于第1垫与板状体90呈一体,所以没有焊接垫浮动的现象,也提高了全切割性。(以上参考图7)
如图8所示,具有在侧面弯曲的分离沟100上附着绝缘性树脂103的工序。这可以通过传递模,注入模,浸渍或涂布实现。作为树脂材料,环氧树脂等热固化性树脂可以用传递模实现,液晶聚合物,对聚苯硫等的热可塑树脂可用注入模实现。
在本实施例,调整绝缘性树脂的厚度,以便从金属细线102的顶部上涂复的100μm。该厚度考虑半导体装置的强度也可以增厚,也可以减薄。
本工序的特征是,涂复绝缘性树脂103,直到固化,板状体90成为支撑底板。在本发明不要在传统的混合IC上的玻璃环氧底板,软片底板或陶瓷底板。
由于在具有弯曲构造的分离沟100上填充绝缘性树脂103,在该部分产生固定效果,可防止前述导电图形从绝缘性树脂103剥落。
在该绝缘性树脂103涂复前,为了保护例如半导体芯片或金属细线的连接部,也可以浇注封装硅树脂等。
图9示出这模压方法的图。图9是示出金属模104的空腔105内填充树脂状态的剖面图。可以看到板状体90的里面整个区域与下金属模104A衔接,上金属模104B在金属模衔接区衔接。符号V表示其它吸气孔。图9B表示在下金属模104A内装着板状体90的状态。符号105是在下金属模上安装的导电销130。经板状体90上开口的导向孔露出导向销130的样子。
图9C是说明在金属模内形成的空腔105,流道107及罐106关系的图。如图所示,空腔105在横方向多个排列设计,以便用一个标准框配多个半导体装置。用点线示出的符号108表示板状体的配置区,例如如图11所示的板状体109与传统的标准框同样处理,安装。这是多个一体形成图6的板状体的。其特征为用该板状体制造的半导体装置本身尺寸小,而且在一个空腔内可能配多个,可能大量生产,降低造价。
接着具有从金属模104取出密封的板状体,去除在绝缘性树脂103里面露出的板状体90,使第1垫,系垫等的导电图形分离的工序。
图10A是示出分离的线的平面图,图10B是示出绝缘性树脂103里面和第1垫里面或绝缘性树脂103里面和系垫里面一致的图。这可以通过用研磨装置磨削直到露出分离沟100为止。在里面形成阻焊等绝缘膜,也可以只露出电连接必要的部分。
图10C是使该研磨中途停止,在第1垫81的另一端110上形成凸部111的图,这在与凸部111对应的部分上,形成光刻胶,对此以之外部分进行刻蚀,而且形成绝缘膜112,以便露出凸部111。通过采取措施,可以防止与通过系垫87下面的安装底板侧的导体短路。通过经焊料固着,也不可能在第1垫上爬迁的焊料延伸与相邻的垫81或小岛82接触。特别在越是在微细图形上形成,则该绝缘膜越有效。
而且最后,把该模压的标准框90配置在划线桌上以定位标志85,86作为基准,调整平板的位置,沿着用点线所示的线进行划线,作为半导体装置完成。
用本制造方法,在小岛82上只安装晶体管,也可以安装二极管,IC。根据构造,在一个小岛上也可以固着多个半导体芯片,也可以分别设置小岛用于固着各自的半导体芯片。
参照图12进一步说明本实施例中采用的半导体装置。
本构造作为导电图形151形成配线L1,L2,作为第1垫及/或外部引出用电极,形成平台状电极151B,CE到J,作为系垫形成151A,151D。
IC电路有从大规模电路直到小规模电路。而在这里也根据附图,在图12A上表示小规模电路。该电路是自动放大电路中多用的差动放大电路和电流镜电路。前述差动放大电路如图12A所示用TR1和TR2构成,前述电流镜电路主要由TR3和TR4构成。
图12B是在本半导体装置内实现图12A电路时的平面图,图12C是沿图12B的A-A线的断面图,图12D是沿B-B线的断面图。在左侧设置安装了TR1和TR3的系垫151A,在右侧设置安装了TR2和TR4的系垫151D。在该系垫151A,151D,的上侧设置外部连接用电极151D,151E到151G,在下侧设置151C,151H到151J。而且由于TR1的发射极共同连接,所以配线L2与电极151E,151G一体形成。而由于TR3的基极和TR4的基极,TR3的发射极和TR4的发射极共同连接,所以配线L1与电极151C,155J一体设置,配线L3与电极155H,155I一体设置。
本发明的特征在于该配线L1到L3。如用图4说明,则配线60是与其符合的。这些配线依本混合IC的集成度而异,但宽度为25μm,非常狭窄,该25μm的宽度是在采用湿刻蚀时的数值,如果采用干刻蚀,该宽度可以更狭窄。
正如图12D所示,配线L1只露出里面,其它侧面完全受绝缘性树脂150支撑。如果作其它表示,则由于配线埋入绝缘性树脂150内,所以有可能防止配线的拔出,翘曲。尤其是通过导电通路的侧面由粗面构成或弯曲面构成,在导电通路表面形成边沿等,产生固定效果,形成前述导电通路很难从绝缘性树脂拔出的结构。
由于外部连接用电极151B,151C,151E到151J用前述所示的用绝缘性树脂埋入,所以形成的结构即使从固着的外部引线加外力,也不会剥离。
接着采用多个晶体管,边参照图13到16,说明构成简单电路的半导体装置的图形。最外侧所示的矩形是表示半导体装置的外形的图。
图13表示在各系垫200,201上固定着半导体元件203,204,用金属细线把第1垫连接到兼作外部引出电极的电极205到207上。电极206是使两根金属细线处于同电位,以省略设置在电极间的配线。即电极206是作为使焊接垫。外部引出电极及二电极处于同电位的配线工作的。
图14表示在系垫210,211上固定半导体元件212,213,214,215,在第1垫216到220上连接金属细线。电极220与系垫210一体构成,在其间设置连接用的配线221。与图13不同,焊接垫分散形成的。
图15是在一侧边,一列形成第1垫230…,而在系垫231,232上固定着半导体元件233到235的图。系垫232作为半导体元件的固定用平台及焊接垫发挥功能。
图16是在系垫240到242上固定着半导体元件243到245的图。而且配置第1垫246…,247。垫247是使三电极处于同电位的。
从以上说明也可以判定,金属细线是电连接在半导体元件的电极和焊接垫之间,同时假如使用原来的配线,则可以作为象交叉那样的地方跨越而充分利用。
对于全部实施例而言,在板状体上涂复刻蚀率小的导电膜,经该导电膜通过半刻蚀可实现边沿和弯曲构造,可以具有固定效果。
如果例如在Cu箔上涂复Ni,则可利用氯化铁或氯化铜等一次刻蚀,通过刻蚀率之差Ni呈边沿成形,所以是恰当的。由于半导体芯片的里面直接露出,或小岛露出,可以与安装底板的导电通路热耦合,所以可以提高半导体装置的散热性。由此可以降低半导体芯片的温度,可以相应地提高半导体芯片的驱动能力。
例如功率MOS,IGBT,SIT,大电流驱动用晶体管,大电流驱动IC(MOS型,BIP型,Bi-CMOS型)存储元件等是合适的。
正如以上说明所示,本发明的板状体具有可以经导电膜或光刻胶对导电图形进行半刻蚀的构造。而且也可以对半导体从表到里进行印刷或刻蚀,在中途终止,作为混合IC的导电图形构成。通过可以采用该半刻蚀的构造,可以使导电图形的间隔变窄,使更微细的混合IC用的图形成为可能。由于第1垫,系垫,配线与板状体一体构成,所以可以抑制变形或翘曲,可以不要系条,吊线。在密封绝缘性树脂而且完全固定后,通过研制或刻蚀板状体里面,可以分离导电图形。可以把导电图形配置在无位置偏移的预定位置上。而且也可以无任何变形地配置混合IC特有的长长迂回的配线。
在树脂密封区内通过配置导电图形整个区域,可以没有在传统的引线和引线之间产生的变化。
通过形成与导销相同的图形,在用绝缘性树脂密封期间,可以作为导销开口,通过预先对导销开口,可以设置在密封用金属模的导销内,实现高精度的树脂密封。
如果以Cu作主料构成板状体,导电膜用Ni,Ag,或Pd等构成,则可以用导电膜作刻蚀掩模,而且在刻蚀时,其侧面是弯曲构造,在导电图形的表面可以通过导电膜形成边沿,可以形成有固定效果的构造,从而可以防止位于绝缘性树脂里面的导电图形的拔出,翘曲。
由于系垫本身与板状体一体构成,可以形成不采用吊线的构造。
用板状体制造的半导体装置,用必须最低限度的导电膜等的导电通路及绝缘性树脂的构成,成为资源不浪费的半导体装置。因此能实现可大幅降低成本的半导体装置。通过使绝缘性树脂的涂复膜厚和导电箔厚度的最佳化,可以实现非常小型化,薄型化及轻量化的半导体装置。
由于导电图形里面从绝缘性树脂露出,导电图形的里面可以提供直接与外部连接,其优点是可以不要如传统构造的软片那样穿孔等加工。
半导体元件经焊锡,Au,Ag等的导电膜直接固着在系垫上时,由于系垫的里面露出,从半导体元件发生的热可以经系垫直接把热传输给安装底板上。尤其是依靠该散热性也可以安装功率元件。
半导体装置成为具有分离沟表面和导电图形的表面实质一致的平坦表面的构造,即使把狭窄间距QFP等安装在安装底板上,因为半导体装置本身可以原封不动地水平移动,所以极容易修正外部引出用电极的偏移。
导电图形的侧面作为弯曲构造,而且可以在表面形成边沿。由此可以产生固定效果,可以防止导电图形的翘曲,拔出。
直到绝缘性树脂的固着时为止用板状体支撑全体,导电图形分离,划线,绝缘性树脂成支撑底板,从而其优点是不要如传统例所说明的那样,要支撑底板,因此成本也低。
Claims (31)
1.一种板状体,具有由平坦面构成的第1表面,以及和与前述第1表面对置设置的,由平坦面构成的第2表面,其特征为:在前述第2表面上形成在与半导体元件装载区或其近旁设置的多个第1垫相当的图形掩模。
2.根据前述权利要求1所述的板状体,其特征为,前述掩模是导电膜。
3.根据前述权利要求1所述的板状体,其特征为,前述掩模是光刻胶。
4.根据前述权利要求1所述的板状体,其特征为,形成前述掩模,直到与前述第1垫上连续形成的配线相当的区域为止。
5.根据前述权利要求1所述的板状体,其特征为,前述第1垫是焊接垫或焊接球固定用垫。
6.根据前述权利要求1所述的板状体,其特征为,在前述半导体元件装载区上设置与系垫实质相同图形的导电膜或光刻胶。
7.根据前述权利要求1所述的板状体,其特征为,在前述第2表面上形成与无源元件用固定垫及/或外部引出用电极实质相同图形的导电膜或光刻胶。
8.根据前述权利要求7所述的板状体,其特征为,前述无源元件是芯片电阻和电容器。
9.根据前述权利要求1所述的板状体,其特征为,在前述板状体的对置的侧边上,形成导向孔,用于插入与导销实质相同的图形或前述导销。
10.根据前述权利要求1所述的板状体,其特征为,前述板状体是用压延金属构成。
11.根据前述权利要求1所述的板状体,其特征为,前述板状体由导电箔构成,前述导电膜由与前述导电箔材料不同的材料构成。
12.一种板状体,它具有由平坦面构成的第1表面,以及具有按照所希望高度形成凸部,与前述第1表面对置而成的第2表面,其特征为,前述凸部在半导体装载区及其近旁构成多个第1垫。
13.根据前述权利要求12所述的板状体,其特征为,前述凸部构成与前述第1垫一体设置的配线。
14.根据前述权利要求13所述的板状体,其特征为,前述凸部构成与前述配线一体设置的第2垫。
15.根据前述权利要求12所述的板状体,其特征为,前述第1垫和/或前述第2垫是焊接垫或焊接球固定用垫。
16.根据前述权利要求12所述的板状体,其特征为,前述凸部构成设置在前述半导体元件装载区的系垫。
17.根据前述权利要求12所述的板状体,其特征为,前述凸部构成无源元件用的固定垫及/或外部引出用电极。
18.根据前述权利要求12所述的板状体,其特征为,前述无源元件是芯片电阻或芯片电容器。
19.根据前述权利要求12所述的板状体,其特征为,在与前述板状体对置的侧边上,形成插入与导销实质相同的图形或前述导销的导向孔。
20.根据前述权利要求12所述的板状体,其特征为,把前述凸部形成的图形作为一单位的单元矩阵状地配置所述板状体。
21.根据前述权利要求12所述的板状体,其特征为,前述板状体由Cu,Al,Fe-Ni合金,Cu-Al层叠体或Al-Cu-Al的层叠体形成。
22.根据前述权利要求12所述的板状体,其特征为,在前述凸部的上面形成与构成前述凸部材料不同的材料的导电膜。
23.根据前述权利要求12所述的板状体,其特征为,前述凸部的侧面有固定构造。
24.根据前述权利要求12所述的板状体,其特征为,前述导电膜在前述凸部上面构成边檐。
25.根据前述权利要求1所述的板状体,其特征为,前述导电膜由Ni,Au,Ag或Pd形成。
26.一种板状体,具有与树脂密封区对应的整个面平坦的第1面和形成凸部的第2面,该凸部用于形成与多个第1垫以及对前述第1垫一体设置的配线,所述多个第1垫从所述第1面按规定厚度形成片状,在以与上金属模相接的区域包围的区域中设置在半导体元件装载区或其近旁,其特征为,至少被前述上金属模衔接的区域包围的区域由前述第2面及前述上金属模构成密闭空间。
27.一种半导体装置的制造方法,其特征为具有以下工序
板状体准备工序,所述板状体具有由平坦面形成的第1表面以及与前述第1表面对置设置的,由平坦面形成的第2表面,在前述第2表面上,形成与设置在半导体元件装载区域或其近旁的多个第1垫相当的图形掩模;
形成凸部的工序,通过经前述掩模对其前述第2表面的一部分进行刻蚀,去除与前述第1垫相当的区域,通过降低前述第2表面的水平面,在与前述第1垫相当的区域内形成凸部;
半导体元件装载工序,在前述半导体元件装载区装载半导体元件,同时,经前述第1垫进行电连接;
充填树脂工序,把前述板状体装载在金属摸上,在由前述板状体和前述上金属模构成的空间充填树脂;
分离工序,在去除前述充填的树脂的里面露出的板状体,使前述凸部各自分离。
28.根据前述权利要求26所述的板状体,其特征为,包含降低水平面工序,在形成前述凸部的工序后,除去前述半导体元件装载区的掩模,接着通过刻蚀,使前述半导体元件装载区的水平面处于前述凸部的表面和除去前述凸部的区域水平面之间,前述半导体元件装载面还比焊接垫的水平面低。
29.一种半导体装置的制造方法,其特征为,包含以下工序:
准备板状体,该板状体具有与树脂密封区对应的整个面呈平坦的第1面,和形成凸部的第2面,该凸部用于形成在由前述第1面以预定厚度形成为片状,与上金属模的衔接区包围的区域上,在半导体元件装载区或近旁设置的多个第1垫以及与前述第1垫一体设置的配线,
在前述半导体元件装载区上装载半导体元件,同时,对前述第1垫和前述半导体元件电连接;
把前述板状体装载在金属模上,在由前述板状体和前述上金属模构成的空间内填充树脂;
除去在前述填充树脂的第1面露出的板状体,使前述凸部各自分离的工序。
30.根据前述权利要求26所述的半导体装置的制造方法,其特征为,与前述树脂密封区对应的前述板状体的第1面的整个面与下金属模衔接。
31.根据前述权利要求26所述的半导体装置的制造方法,其特征为,前述下金属模的衔接区通过真空吸气手段分散配置。
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JP2000135283A JP3778773B2 (ja) | 2000-05-09 | 2000-05-09 | 板状体および半導体装置の製造方法 |
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US (1) | US7220921B1 (zh) |
EP (1) | EP1154473A3 (zh) |
JP (1) | JP3778773B2 (zh) |
KR (1) | KR100374278B1 (zh) |
CN (1) | CN1237610C (zh) |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1331220C (zh) * | 2002-04-11 | 2007-08-08 | 皇家飞利浦电子股份有限公司 | 制造电子器件的方法和电子器件 |
CN102064139A (zh) * | 2009-11-18 | 2011-05-18 | 南亚科技股份有限公司 | 半导体封装结构 |
CN102224587A (zh) * | 2008-11-25 | 2011-10-19 | 株式会社三井高科技 | 引线框、使用该引线框的半导体装置、该半导体装置的中间产品以及它们的制造方法 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10153615C1 (de) * | 2001-10-31 | 2003-07-24 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung von elektronischen Bauteilen |
US6774470B2 (en) * | 2001-12-28 | 2004-08-10 | Dai Nippon Printing Co., Ltd. | Non-contact data carrier and method of fabricating the same |
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US7927920B2 (en) * | 2007-02-15 | 2011-04-19 | Headway Technologies, Inc. | Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package |
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US9545009B2 (en) * | 2007-05-23 | 2017-01-10 | Spectra Logic, Corporation | Passive alterable electrical component |
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US8384231B2 (en) * | 2010-01-18 | 2013-02-26 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
US9054417B2 (en) * | 2011-07-25 | 2015-06-09 | Auden Techno Corp. | Manufacturing method of antenna structure |
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WO2017136305A1 (en) * | 2016-02-01 | 2017-08-10 | Octavo Systems Llc | Systems and methods for manufacturing electronic devices |
CN108882519A (zh) * | 2018-08-27 | 2018-11-23 | 惠科股份有限公司 | 电路板及其制造方法、驱动电路板、显示设备、显示系统 |
JP7427087B2 (ja) * | 2020-05-29 | 2024-02-02 | 三井化学株式会社 | 異方導電性シート、異方導電性シートの製造方法、電気検査装置および電気検査方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4447857A (en) * | 1981-12-09 | 1984-05-08 | International Business Machines Corporation | Substrate with multiple type connections |
US5200362A (en) * | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
US5177591A (en) * | 1991-08-20 | 1993-01-05 | Emanuel Norbert T | Multi-layered fluid soluble alignment bars |
US5976912A (en) * | 1994-03-18 | 1999-11-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
US5493075A (en) * | 1994-09-30 | 1996-02-20 | International Business Machines Corporation | Fine pitch solder formation on printed circuit board process and product |
JPH08204103A (ja) | 1995-01-30 | 1996-08-09 | Mitsui Toatsu Chem Inc | 多端子半導体パッケージ |
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
US5796590A (en) * | 1996-11-05 | 1998-08-18 | Micron Electronics, Inc. | Assembly aid for mounting packaged integrated circuit devices to printed circuit boards |
JP3094948B2 (ja) * | 1997-05-26 | 2000-10-03 | 日本電気株式会社 | 半導体素子搭載用回路基板とその半導体素子との接続方法 |
JP3837215B2 (ja) * | 1997-10-09 | 2006-10-25 | 三菱電機株式会社 | 個別半導体装置およびその製造方法 |
JPH11126952A (ja) | 1997-10-22 | 1999-05-11 | Sanyo Electric Co Ltd | 混成集積回路装置およびその製造方法 |
US6329605B1 (en) * | 1998-03-26 | 2001-12-11 | Tessera, Inc. | Components with conductive solder mask layers |
US6377464B1 (en) * | 1999-01-29 | 2002-04-23 | Conexant Systems, Inc. | Multiple chip module with integrated RF capabilities |
-
2000
- 2000-05-09 JP JP2000135283A patent/JP3778773B2/ja not_active Expired - Fee Related
- 2000-10-03 US US09/678,142 patent/US7220921B1/en not_active Expired - Fee Related
- 2000-10-03 EP EP00308679A patent/EP1154473A3/en not_active Ceased
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2001
- 2001-02-05 CN CNB011032138A patent/CN1237610C/zh not_active Expired - Fee Related
- 2001-02-12 KR KR10-2001-0006676A patent/KR100374278B1/ko not_active IP Right Cessation
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1331220C (zh) * | 2002-04-11 | 2007-08-08 | 皇家飞利浦电子股份有限公司 | 制造电子器件的方法和电子器件 |
CN102224587A (zh) * | 2008-11-25 | 2011-10-19 | 株式会社三井高科技 | 引线框、使用该引线框的半导体装置、该半导体装置的中间产品以及它们的制造方法 |
US8680657B2 (en) | 2008-11-25 | 2014-03-25 | Mitsui High-Tec, Inc. | Lead frame, semiconductor apparatus using this lead frame, intermediate product thereof and manufacturing method thereof |
CN102064139A (zh) * | 2009-11-18 | 2011-05-18 | 南亚科技股份有限公司 | 半导体封装结构 |
Also Published As
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US7220921B1 (en) | 2007-05-22 |
JP2001320011A (ja) | 2001-11-16 |
EP1154473A3 (en) | 2004-10-20 |
TWI276211B (en) | 2007-03-11 |
KR20010103567A (ko) | 2001-11-23 |
CN1237610C (zh) | 2006-01-18 |
KR100374278B1 (ko) | 2003-03-03 |
JP3778773B2 (ja) | 2006-05-24 |
EP1154473A2 (en) | 2001-11-14 |
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