JP2010153726A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- JP2010153726A JP2010153726A JP2008332637A JP2008332637A JP2010153726A JP 2010153726 A JP2010153726 A JP 2010153726A JP 2008332637 A JP2008332637 A JP 2008332637A JP 2008332637 A JP2008332637 A JP 2008332637A JP 2010153726 A JP2010153726 A JP 2010153726A
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Abstract
【解決手段】半導体装置の製造工程における封止工程を以下のように行う。上型17a、下型17bを有する成形金型17を準備し、上型17aと下型17bとの間にフィルムを配置する。次に、タブ1の上面に第1接着材9、半導体チップ3、第2接着材11、基材4の順で各部材が搭載されたリードフレーム15をフィルム18と下型17bとの間に配置する。基材4には、開口部4dが形成され、開口部4dは保護シート12で覆われている。半導体チップ3の主面3aには受光部3dが形成されている。次に、上型17aおよび下型17bをクランプし、基材4の一部をフィルム18に食い込ませる。その後、フィルム18および下型17bとの間に封止用の樹脂16aを供給し、一括封止体16を形成し、受光部3d上に樹脂バリのない光センサ系半導体装置を得る。
【選択図】図33
Description
(a)チップ搭載部、および前記チップ搭載部の周囲に配置された複数の電極部を備えた第1基材を準備する工程;
(b)第1主面、前記第1主面に形成されたセンサ部、前記第1主面に形成され、前記センサ部と電気的に接続された複数のパッド、前記第1主面と反対側の第1裏面、および前記第1主面と前記第1裏面との間に位置する第1側面、を有する半導体チップを、前記第1裏面が前記チップ搭載部と対向するように、第1接着材を介して前記チップ搭載部上に搭載する工程;
(c)第2主面、前記第2主面と反対側の第2裏面、前記第2主面と前記第2裏面との間に位置する第2側面、および前記第2主面から前記第2裏面まで貫通する開口部を有し、前記開口部が前記第2主面上に貼り付けられた保護シートにより覆われた第2基材を、前記第2裏面が前記半導体チップの前記第1主面と対向するように、第2接着材を介して前記半導体チップの前記第1主面上に搭載する工程;
(d)前記半導体チップの前記複数のパッドと前記複数の電極部とを、複数の導電性部材を介してそれぞれ電気的に接続する工程;
(e)前記第2基材の前記第2側面の一部および前記第2基材の前記第2主面が露出するように、前記半導体チップ、前記第2基材、および前記複数の導電性部材を樹脂で封止し、封止体を形成する工程;
ここで、前記封止体は、以下の工程により形成される、
(e1)上型、前記上型と対向する下型を有する成形金型を準備する工程;
(e2)前記上型と前記下型との間にフィルムを配置する工程;
(e3)前記半導体チップおよび前記第2基材が搭載された前記第1基材を、前記フィルムと前記下型との間に配置する工程;
(e4)前記(e3)工程の後、前記上型および前記下型をクランプし、前記第2基材の一部を前記フィルムに食い込ませる工程;
(e5)前記(e4)工程の後、前記フィルムおよび前記下型との間に前記樹脂を供給し、前記封止体を形成する工程;
(e6)前記(e5)工程の後、前記上型および前記下型を型開きし、前記封止体が形成された前記第1基材を前記成形金型から取り出す工程。
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
まず、図1〜図4を用いて、本実施の形態の半導体装置の概略構成を説明する。図1は本実施の形態の半導体装置の上面側を示す平面図、図2は図1に示す半導体装置の下面側を示す平面図、図3は図1に示すA−A線に沿った断面図である。また、図4は、図1に示す半導体装置の封止体内部における平面構造を示す平面図である。このため、図4では、内部の構成が分かるように、封止体を透過して内部構造を示す平面図としている。
次に図1〜図4に示すQFN10の製造方法について説明する。
次に本実施の形態の変形例について説明する。
1a 上面
1b 下面
2 リード(電極部)
2a 上面
2b 下面
2c 側面
3 半導体チップ
3a 主面(第1主面)
3b 裏面(第1裏面)
3c 側面(第1側面)
3d 受光部(センサ部)
3e パッド
4 基材(第2基材)
4a 主面(第2主面)
4b 裏面(第2裏面)
4c 側面(第2側面)
4d 開口部(貫通孔)
5 ワイヤ(導電性部材)
6 封止体
6a 上面
6b 下面
6d 窪み部
7 外装めっき層(金属層)
8 吊りリード
9 第1接着材
10、23、24 QFN(半導体装置)
11 第2接着材
12 保護シート
12a 上面
12b 下面
15 リードフレーム(第1基材)
15a 製品形成領域(デバイス形成領域)
15b 枠体
16 一括封止体
16a 樹脂
17 成形金型
17a 上型
17b 下型
17c 上型面
17d キャビティ
17da 側面
17e ゲート部
17f 下型面
17g 段差部
17ga 側面
17h ポット部
17j プランジャ
18 フィルム(上型面被覆フィルム、第1フィルム)
18a 上面
18b 下面
19a 第1速度
19b 第2速度
20 ダイシングライン
21 ダイシングブレード(切断治具)
22 ダイシングテープ
27 下型面被覆フィルム(第2フィルム)
27a 上面
34 BGA(半導体装置)
35 配線基板(第1基材)
35a 上面
35b 下面
35c チップ搭載部
35d ボンディングリード(電極部)
35e バンプ電極(外部端子)
35f ランド部
41 ウエハ
41a 主面
41b 裏面
42 ダイシングテープ
43 マスク
43a 開口部
Claims (17)
- 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)チップ搭載部、および前記チップ搭載部の周囲に配置された複数の電極部を備えた第1基材を準備する工程;
(b)第1主面、前記第1主面に形成されたセンサ部、前記第1主面に形成され、前記センサ部と電気的に接続された複数のパッド、前記第1主面と反対側の第1裏面、および前記第1主面と前記第1裏面との間に位置する第1側面、を有する半導体チップを、前記第1裏面が前記チップ搭載部と対向するように、第1接着材を介して前記チップ搭載部上に搭載する工程;
(c)第2主面、前記第2主面と反対側の第2裏面、前記第2主面と前記第2裏面との間に位置する第2側面、および前記第2主面から前記第2裏面まで貫通する開口部を有し、前記開口部が前記第2主面上に貼り付けられた保護シートにより覆われた第2基材を、前記第2裏面が前記半導体チップの前記第1主面と対向するように、第2接着材を介して前記半導体チップの前記第1主面上に搭載する工程;
(d)前記半導体チップの前記複数のパッドと前記複数の電極部とを、複数の導電性部材を介してそれぞれ電気的に接続する工程;
(e)前記第2基材の前記第2側面の一部および前記第2基材の前記第2主面が露出するように、前記半導体チップ、前記第2基材、および前記複数の導電性部材を樹脂で封止し、封止体を形成する工程;
ここで、前記封止体は、以下の工程により形成される、
(e1)上型、前記上型と対向する下型を有する成形金型を準備する工程;
(e2)前記上型と前記下型との間にフィルムを配置する工程;
(e3)前記半導体チップおよび前記第2基材が搭載された前記第1基材を、前記フィルムと前記下型との間に配置する工程;
(e4)前記(e3)工程の後、前記上型および前記下型をクランプし、前記第2基材の一部を前記フィルムに食い込ませる工程;
(e5)前記(e4)工程の後、前記フィルムおよび前記下型との間に前記樹脂を供給し、前記封止体を形成する工程;
(e6)前記(e5)工程の後、前記上型および前記下型を型開きし、前記封止体が形成された前記第1基材を前記成形金型から取り出す工程。 - 請求項1において、
前記半導体チップの前記第1主面において、前記センサ部の全体が、前記開口部の内側に配置されていることを特徴とする半導体装置の製造方法。 - 請求項2において、
前記第2基材は、前記半導体チップを構成する材料と同じ半導体材料からなることを特徴とする半導体装置の製造方法。 - 請求項2において、
前記半導体チップの前記第1主面において、前記第2接着材は前記センサ部の外縁よりも外側に配置されていることを特徴とする半導体装置の製造方法。 - 請求項1において、
前記第2基材は、前記チップ搭載部、前記チップ搭載部を支持する複数の吊りリード、前記チップ搭載部の周囲に配置された前記複数の電極部である複数のリード、および前記複数の吊りリードおよび前記複数のリードと一体に形成された枠体とを備えたリードフレームであって、
前記チップ搭載部の下面が、前記封止体の下面側から露出していることを特徴とする半導体装置の製造方法。 - 請求項5において、
前記(e4)工程では、前記チップ搭載部、前記第1接着材、前記半導体チップ、前記第2接着材、および前記第2基材の中心が、それぞれ厚さ方向に重なる位置に配置された状態で前記第2基材の一部を前記フィルムに食い込ませることを特徴とする半導体装置の製造方法。 - 請求項1において、
前記(e4)工程には、
(e4a)前記上型と前記下型の距離を、第1速度で近づけて、前記フィルムの下面と前記保護シートの上面とを当接させる工程と、
(e4b)前記(e4a)工程の後、前記上型と前記下型の距離を、前記第1速度よりも遅い第2速度で近づけて前記第2基材の一部を前記フィルムに食い込ませる工程とが含まれることを特徴とする半導体装置の製造方法。 - 請求項7において、
前記第2速度は、前記上型と前記下型の距離が近づくにつれて遅くなることを特徴とする半導体装置の製造方法。 - 請求項1において、
前記チップ搭載部の上面の面積は、前記半導体チップの前記第1裏面の面積よりも大きいことを特徴とする半導体装置の製造方法。 - 請求項1において、
前記第2接着材の厚さは、前記第1接着材の厚さよりも薄いことを特徴とする半導体装置の製造方法。 - 請求項1において、
前記(c)工程において、前記半導体チップの前記第1主面上に搭載される前記第2基材の前記第2主面の高さは、前記(d)工程において、前記複数のパッドと前記複数の電極部とをそれぞれ電気的に接続した前記複数の導電性部材の頂部の高さよりも上側となるように搭載することを特徴とする半導体装置の製造方法。 - チップ搭載部と、
前記チップ搭載部の周囲に配置された複数の電極部と、
第1主面、前記第1主面に形成されたセンサ部、前記第1主面に形成され、前記センサ部と電気的に接続された複数のパッド、前記第1主面と反対側の第1裏面、および前記第1主面と前記第1裏面との間に位置する第1側面を有し、前記第1裏面が前記チップ搭載部と対向するように、第1接着材を介して前記チップ搭載部上に搭載された半導体チップと、
第2主面、前記第2主面と反対側の第2裏面、前記第2主面と前記第2裏面との間に位置する第2側面、および前記第2主面から前記第2裏面まで貫通する開口部を有し、前記第2裏面が前記半導体チップの前記第1主面と対向するように、第2接着材を介して前記半導体チップの前記第1主面上に搭載された基材と、
前記半導体チップの前記複数のパッドと前記複数の電極部とをそれぞれ電気的に接続する複数の導電性部材と、
前記基材の前記第2側面の一部および前記基材の前記第2主面が露出するように、前記半導体チップ、前記基材、および前記複数の導電性部材を封止する封止体と、を含み、
前記半導体チップの前記センサ部は、前記基材の開口部において、露出していることを特徴とする半導体装置。 - 請求項12において、
前記半導体チップの前記第1主面において、前記センサ部の全体が、前記開口部の内側に配置されていることを特徴とする半導体装置。 - 請求項13において、
前記基材は、前記半導体チップを構成する材料と同じ半導体材料からなることを特徴とする半導体装置。 - 請求項12において、
前記基材の前記第2主面上には、前記開口部を覆う保護シートが貼り付けられていることを特徴とする半導体装置。 - 請求項13において、
前記半導体チップの前記第1主面において、前記第2接着材は前記センサ部の外縁よりも外側に配置されていることを特徴とする半導体装置。 - 請求項12において、
前記チップ搭載部の下面が前記封止体の下面側から露出していることを特徴とする半導体装置。
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