CN106960795A - Pmos晶体管的形成方法 - Google Patents

Pmos晶体管的形成方法 Download PDF

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CN106960795A
CN106960795A CN201610016236.3A CN201610016236A CN106960795A CN 106960795 A CN106960795 A CN 106960795A CN 201610016236 A CN201610016236 A CN 201610016236A CN 106960795 A CN106960795 A CN 106960795A
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side wall
semiconductor substrate
ion
grid structure
pmos transistor
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CN106960795B (zh
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

一种PMOS晶体管的形成方法，包括：提供半导体衬底，在所述半导体衬底上形成栅极结构；以所述栅极结构为掩膜，在栅极结构两侧的半导体衬底中注入锗离子，在栅极结构两侧的半导体衬底内形成锗硅区；在所述栅极结构的侧壁表面以及与侧壁相邻的部分锗硅区表面形成侧墙；以所述侧墙为掩膜，刻蚀去除侧墙两侧的锗硅区，暴露出锗硅区底部的半导体衬底；以所述侧墙和侧墙底部剩余的锗硅区为掩膜，刻蚀侧墙和剩余的锗硅区两侧的半导体衬底，在侧墙和侧墙底部剩余的锗硅区两侧的半导体衬底内形成sigma形状的凹槽；在sigma形状的凹槽中填充压应力材料，形成源漏区。本发明方法形成的晶体管增加了施加在晶体管沟道区的压应力。

Description

PMOS晶体管的形成方法
技术领域
本发明涉及半导体制作领域，特别涉及一种PMOS晶体管的形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件为了达到更高的运算速度、更大的数据存储量、以及更多的功能，半导体器件朝向更高的元件密度、更高的集成度方向发展，因此，互补金属氧化物半导体(Complementary MetalOxide Semiconductor，CMOS)晶体管的栅极变得越来越细且长度变得比以往更短。为了获得较好的电学性能，通常需要通过控制载流子迁移率来提高半导体器件性能。控制载流子迁移率的一个关键要素是控制晶体管沟道中的应力，以提高驱动电流。
目前，采用嵌入式锗硅(Embedded GeSi)技术来提高应力，即在需要形成源区和漏区的区域先形成锗硅材料，然后再进行掺杂形成PMOS晶体管的源区和漏区；形成所述锗硅材料是为了引入硅和锗硅(SiGe)之间晶格失配形成的压应力，控制载流子迁移率，提高PMOS晶体管的性能。
现有技术具有硅锗源漏区的PMOS晶体管的形成方法，包括：提供半导体衬底，所述半导体衬底上形成有栅极结构，所述栅极结构包括栅介质层和位于栅介质层上的栅电极；在栅结构的侧壁形成偏移侧墙；以所述栅极结构和偏移侧墙为掩膜，对栅极结构和偏移侧墙半导体衬底进行浅掺杂离子注入，在栅极结构和偏移侧墙两侧的半导体衬底内形成浅掺杂区；在所述偏移侧墙表面形成主侧墙；以所述栅极结构和主侧墙为掩膜，刻蚀栅极结构和主侧墙两侧的半导体衬底，在栅极结构和主侧墙两侧的半导体衬底内形成凹槽；在所述凹槽内填充硅锗材料，并对硅锗材料掺杂杂质离子，形成硅锗源漏区。
现有技术形成的PMOS晶体管的性能仍有待提升。
发明内容
本发明解决的问题是怎样提高PMOS晶体管沟道区载流子的迁移率。
为解决上述问题，本发明提供一种PMOS晶体管的形成方法，包括：
提供半导体衬底，在所述半导体衬底上形成栅极结构；以所述栅极结构为掩膜，在栅极结构两侧的半导体衬底中注入锗离子，在栅极结构两侧的半导体衬底内形成锗硅区；在所述栅极结构的侧壁表面以及与侧壁相邻的部分锗硅区表面形成侧墙；以所述侧墙为掩膜，刻蚀去除侧墙两侧的锗硅区，暴露出锗硅区底部的半导体衬底；以所述侧墙和侧墙底部剩余的锗硅区为掩膜，刻蚀侧墙和剩余的锗硅区两侧的半导体衬底，在侧墙和侧墙底部剩余的锗硅区两侧的半导体衬底内形成sigma形状的凹槽；在sigma形状的凹槽中填充压应力材料，形成源漏区。
可选的，在栅极结构两侧的半导体衬底中注入锗离子采用离子注入工艺。
可选的，所述注入锗离子时的离子注入工艺的注入能量为10～100Kev，注入角度为0～40°，注入剂量为5E15～5E16atom/cm2。
可选的，在半导体衬底中注入锗离子的同时或之后，还包括：以所述栅极结构为掩膜，对栅极结构两侧的半导体衬底进行第一浅掺杂离子注入，在栅极结构两侧的半导体衬底内形成第一浅掺杂区。
可选的，在半导体衬底中注入锗离子之后，还包括：在栅极结构的侧壁表面形成偏移侧墙，以所述栅极结构和偏移侧墙为掩膜，对栅极结构和偏移侧墙两侧的半导体衬底进行第一浅掺杂离子注入，在栅极结构和偏移侧墙两侧的半导体衬底内形成第一浅掺杂区。
可选的，刻蚀去除侧墙两侧的锗硅区，暴露出锗硅区底部的半导体衬底之后，还包括：以所述侧墙和侧墙底部剩余的锗硅区为掩膜，对所述侧墙和剩余的锗硅区两侧半导体衬底进行第二浅掺杂离子注入，在所述侧墙和剩余的锗硅区两侧的半导体衬底内形成第二浅掺杂区，第二浅掺杂区的深度大于第一浅掺杂区的深度，且第二浅掺杂区的边缘的离栅极结构边缘的垂直距离大于第一浅掺杂区离栅极结构的边缘的垂直距离。
可选的，形成第二浅掺杂区后，进行第一退火工艺，使得第一浅掺杂区和第二浅掺杂区中的杂质离子扩散。
可选的，第一浅掺杂离子注入和第二浅掺杂离子注入注入的杂质离子为P型杂质离子。
可选的，所述第一浅掺杂离子注入注入P型杂质离子时的能量为2KeV～5KeV，剂量为5e14～2e15atom/cm2，角度为0～7度，所述第二浅掺杂离子注入注入P型杂质离子时的能量为2KeV～5KeV，剂量为1e14～5e14atom/cm2，角度为15～30度。
可选的，第二浅掺杂离子注入注入的杂质离子除了P型杂质离子外，还包括C、N或F离子中一种或几种。如权利要求10所述的PMOS晶体管的形成方法，其特征在于，第二浅掺杂离子注入注入C、N或F离子中一种或几种时的能量为0.5～20kev，注入角度为0～40°，注入剂量为1E14～1E15atom/cm2。
可选的，sigma形状的凹槽形成过程：以所述侧墙和侧墙底部剩余的锗硅区为掩膜，采用干法刻蚀工艺刻蚀侧墙和剩余的锗硅区两侧的半导体衬底，在侧墙和侧墙底部剩余的锗硅区两侧的半导体衬底内形成矩形凹槽；采用湿法刻蚀工艺继续刻蚀矩形凹槽，形成sigma形状的凹槽。
可选的，所述干法刻蚀工艺采用的气体包括：CF4、HBr、He和O2，CF4的气体流量为20-200sccm，HBr的气体流量为50-1000sccm，He的气体流量为200-1000sccm，O2的气体流量为5-20sccm，腔室温度为40-80℃，腔室压力为5-50mTorr，射频功率为400-750W，偏置功率为0-100W；刻蚀时间为20-80S。
可选的，所述湿法刻蚀工艺采用刻蚀容易为TMAH溶液或NH3.H2O溶液，TMAH溶液或NH3.H2O溶液的质量百分比为1％-5％，刻蚀时间为20-80S。如权利要求1所述的PMOS晶体管的形成方法，其特征在于，所述压应力材料为硅锗或锡锗硅。
可选的，压应力材料为硅锗时，压应力材料中锗原子的含量为20～50％。
可选的，所述压应力材料为锡锗硅时，压应力材料中锗原子的含量为20～50％，锡原子的含量为1～5％。
可选的，压应力材料的填充工艺为选择性外延工艺。
如可选的，所述压应力材料中掺杂有P型杂质离子。
可选的，通过自掺杂工艺或离子注入工艺在压应力材料中掺杂P型杂质离子。
与现有技术相比，本发明的技术方案具有以下优点：
本发明的晶体管的形成方法，在形成源漏区之前，以所述栅极结构为掩膜，在栅极结构两侧的半导体衬底中注入锗离子，在栅极结构两侧的半导体衬底内形成锗硅区，使得形成的硅锗区可以位于栅极结构两侧的半导体衬底表面附近，并且硅锗区的一端与栅极结构正方向的半导体衬底的表面附近区域(PMOS晶体管工作时形成沟道的区域)接触，硅锗区可以直接对沟道区域施加压应力，因而硅锗区对沟道区施加的压应力无需较大距离的传递，减少了压应力的损耗，因而硅锗区可以对沟道区域施加较大的压应力，并且，在形成硅锗区后，在半导体衬底内形成sigma形状的凹槽，然后在sigma形状的凹槽中填充压应力材料，形成源漏区，填充的压应力材料也会对沟道区域产生压应力，因而硅锗区和填充的压应力材料两种的应力叠加，使得作用在沟道区域的压应力更大，有利于提高了沟道区域的载流子(空穴)的迁移率。
进一步，在半导体衬底中注入锗离子之后，在栅极结构的侧壁表面形成偏移侧墙，以所述栅极结构和偏移侧墙为掩膜，对栅极结构和偏移侧墙两侧的半导体衬底进行第一浅掺杂离子注入，在栅极结构和偏移侧墙两侧的半导体衬底内形成第一浅掺杂区，形成偏移侧墙的目的是控制形成的第一浅掺杂区的位置，防止短沟道效应。
进一步，以所述侧墙和侧墙底部剩余的锗硅区为掩膜，对所述侧墙和剩余的锗硅区两侧半导体衬底进行第二浅掺杂离子注入，在所述侧墙和剩余的锗硅区两侧的半导体衬底内形成第二浅掺杂区，第二浅掺杂区的深度大于第一浅掺杂区的深度，且第二浅掺杂区的边缘的离栅极结构边缘的垂直距离大于第一浅掺杂区离栅极结构的边缘的垂直距离，以使得栅极结构与后续形成的源漏区之间的电势呈阶梯分布，进一步防止热载流子注入的产生。
附图说明
图1～图7为本发明实施例PMOS晶体管形成过程的结构示意图。
具体实施方式
如背景技术所言，现有技术形成的PMOS晶体管的性能仍有待提升，如现有技术形成的PMOS晶体管的沟道区载流子的迁移率仍有待提升。
研究发现，为了增加晶体管沟道区的应力，现有技术形成的凹槽为sigma(“∑”)形状，即形成的凹槽具有向栅极结构正下方的半导体衬底中凸起，当在凹槽中填充硅锗材料后，使得硅锗材料对晶体管沟道区的施加的压应力更大，但是由于晶体管工作时，沟道区形成在栅极结构底部的半导体衬底的表面附近，而现有技术形成的sigma形状的凹槽的凸起距离沟道区仍较远，因而sigma形状的凹槽中填充硅锗材料后，硅锗材料施加的压应力需要经过较长距离的传递才能作用在沟道区域(栅极结构底部的半导体衬底的表面附近区域)，不可避免的压应力会产生损耗，使得直接施加在沟道区域的压应力仍比较有限。
为此，本发明提供了一种晶体管的形成方法，本发明的晶体管的形成方法，在形成源漏区之前，以所述栅极结构为掩膜，在栅极结构两侧的半导体衬底中注入锗离子，在栅极结构两侧的半导体衬底内形成锗硅区，使得形成的硅锗区位于栅极结构两侧的半导体衬底表面附近，并且硅锗区的一端与栅极结构正方向的半导体衬底的表面附近区域(PMOS晶体管工作时形成沟道的区域)接触，硅锗区可以直接对沟道区域施加压应力，因而硅锗区对沟道区施加的压应力无需较大距离的传递，减少了压应力的损耗，因而硅锗区可以对沟道区域施加较大的压应力，并且，在形成硅锗区后，在半导体衬底内形成sigma形状的凹槽，然后在sigma形状的凹槽中填充压应力材料，形成源漏区，填充的压应力材料也会对沟道区域产生压应力，因而硅锗区和填充的压应力材料两种的应力叠加，使得作用在沟道区域的压应力更大，有利于提高了沟道区域的载流子(空穴)的迁移率。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。在详述本发明实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图1～图7为本发明实施例PMOS晶体管形成过程的结构示意图。
参考图1，提供半导体衬底200。
所述半导体衬底200为后续工艺的载体，所述半导体衬底200的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中，所述半导体衬底200的材料为硅。本实施例中，所述半导体衬底200的材料为硅。
所述半导体衬底内形成有若干浅沟槽隔离结构，所述浅沟槽隔离结构201用于隔离相邻的有源区。在一实施例中，所述浅沟槽隔离结构201形成过程为：刻蚀所述半导体衬底，形成沟槽；采用沉积工艺形成覆盖所述半导体衬底并填充满沟槽的隔离材料层；平坦化去除半导体衬底表面上的隔离材料层，在沟槽中形成浅沟槽隔离结构。
所述沉积工艺可以为等离子体增强化学汽相淀积工艺、大气压化学汽相淀积工艺、低压化学汽相淀积工艺、高密度等离子体化学汽相淀积工艺或原子层化学汽相淀积工艺，平坦化工艺为化学机械研磨工艺。
在另一实施例中，在沟槽中填充隔离材料层之前，在所述沟槽的侧壁和底部表面上还形成衬垫层，在形成衬垫层后在衬垫层上形成填充凹槽的隔离材料。所述衬垫层的材料可以氧化硅，所述隔离材料可以为氧化硅、氮氧化硅或碳氧化硅。
所述有源区内还形成有阱区(图中未示出)，所述阱区通过离子注入工艺形成，本实施例中形成晶体管为PMOS晶体管，离子注入时，注入的杂质离子为N型的杂质离子，N型的杂质离子可以为磷离子、砷离子或锑离子中的一种或几种。
参考图2，在所述半导体衬底200上形成栅极结构。
所述栅极结构包括位于半导体衬底200表面的栅介质层202和位于栅介质层202上的栅电极203。
在一实施例中，所述栅介质层202和栅电极203的形成过程为：在所述半导体衬底200表面上形成栅介质材料层；在所述栅介质材料层表面形成栅电极材料层；在所述栅电极材料层表面形成图形化的硬掩膜层204；以所述图形化的硬掩膜层204为掩膜，刻蚀所述栅电极材料层和栅介质材料层，在半导体衬底200表面上形成栅介质层202和和位于栅介质层202上的栅电极203。
本实施例中，所述栅介质层202的材料为氧化硅，所述栅电极203的材料为多晶硅。
在其他实施例中，所述栅介质层202的材料可以高K介质材料，高K介质材料可以为HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3或BaSrTiO，所述栅电极203的材料为金属，所述金属可以为W、Al或Cu。
在形成栅极结构后，所述硬掩膜层204仍保留，在后续工艺中保护栅极结构的顶部表面。
参考图3，以所述栅极结构为掩膜，在栅极结构两侧的半导体衬底200中注入锗离子，在栅极结构两侧的半导体衬底200内形成锗硅区206。
在栅极结构两侧的半导体衬底中注入锗离子采用离子注入工艺。
所述形成的硅锗区206位于栅极结构两侧的半导体衬底表面附近，并且硅锗区206的一端与栅极结构正方向的半导体衬底的表面附近区域(PMOS晶体管工作时形成沟道的区域)接触，硅锗区206可以直接对沟道区域施加压应力，因而硅锗区206对沟道区施加的压应力无需较大距离的传递，减少了压应力的损耗，因而硅锗区206可以对沟道区域施加较大的压应力，并且，后续在半导体衬底内形成sigma形状的凹槽，然后在sigma形状的凹槽中填充压应力材料，形成源漏区，填充的压应力材料也会对沟道区域产生压应力，因而硅锗区206和填充的压应力材料两种的应力叠加，使得作用在沟道区域的压应力更大，有利于提高了沟道区域的载流子(空穴)的迁移率。在一实施例中，所述注入锗离子时的离子注入工艺的注入能量为10～100Kev，注入角度为0～40°，注入剂量为5E15～5E16atom/cm2。
在一实施例中，在半导体衬底200中注入锗离子的同时或之后，以所述栅极结构为掩膜，对栅极结构两侧的半导体衬底进行第一浅掺杂离子注入，在栅极结构两侧的半导体衬底内形成第一浅掺杂区，所述第一浅掺杂区用于防止热载流子注入效应。
在另一实施例中，在半导体衬底中注入锗离子之后，在栅极结构的侧壁表面形成偏移侧墙，以所述栅极结构和偏移侧墙为掩膜，对栅极结构和偏移侧墙两侧的半导体衬底进行第一浅掺杂离子注入，在栅极结构和偏移侧墙两侧的半导体衬底内形成第一浅掺杂区，形成偏移侧墙的目的是控制形成的第一浅掺杂区的位置，防止短沟道效应。
第一浅掺杂离子注入注入的离子类型与后续源漏区中掺杂的离子类型相同，本实施例中，第一浅掺杂离子注入注入的杂质离子为P型杂质离子，所述P型杂质离子为硼离子、镓离子或铟离子中的一种或几种。
所述第一浅掺杂离子注入注入P型杂质离子时的能量为2KeV～5KeV，剂量为5e14～2e15atom/cm2，角度为0～7度。
参考图4，在所述栅极结构的侧壁表面以及与侧壁相邻的部分锗硅区206表面形成侧墙207。
所述侧墙207用于在后续刻蚀去除部分硅锗区时保护栅极结构的侧壁，并且控制侧墙207底部剩余的硅锗区的宽度，以使侧墙207底部剩余的硅锗区仍能对沟道区产生较大的应力。在一实施例中，所述侧墙207的宽度为50～200埃，所述宽度是指侧墙与硅锗区206接触部分的宽度。
所述侧墙207的形成过程为：形成覆盖所述半导体衬底、硅锗区206表面以及栅极结构侧壁表面以及硬掩膜层204表面的侧墙材料层；无掩膜刻蚀工艺刻蚀所述侧墙材料层，在栅极结构的侧壁表面以及与侧壁相邻的部分锗硅区206表面形成侧墙207。
所述侧墙207的材料为氧化硅、氮化硅、氮氧化硅、氮碳化硅、碳化硅中的几种或几种。所述侧墙207可以为单层或多层(≥2层)堆叠结构。
在其他实施例中，当栅极结构的侧壁表面形成有偏移侧墙时，所述侧墙207位于偏移侧墙的表面。
参考图5，以所述侧墙207为掩膜，刻蚀去除侧墙207两侧的锗硅区，暴露出锗硅区底部的半导体衬底200。
刻蚀去除侧墙207两侧的锗硅区，暴露出锗硅区底部的半导体衬底200的目的是便于第二浅掺杂离子注入以及后续的sigma形状的凹槽刻蚀工艺的进行。
刻蚀工艺可以采用等离子刻蚀工艺。
在一实施例中，刻蚀去除侧墙两侧的锗硅区，暴露出锗硅区底部的半导体衬底之后，还包括：以所述侧墙和侧墙底部剩余的锗硅区为掩膜，对所述侧墙和剩余的锗硅区两侧半导体衬底进行第二浅掺杂离子注入，在所述侧墙和剩余的锗硅区两侧的半导体衬底内形成第二浅掺杂区，第二浅掺杂区的深度大于第一浅掺杂区的深度，且第二浅掺杂区的边缘的离栅极结构边缘的垂直距离大于第一浅掺杂区离栅极结构的边缘的垂直距离，以使得栅极结构与后续形成的源漏区之间的电势呈阶梯分布，进一步防止热载流子注入的产生。在一实施例中，所述第二浅掺杂离子注入注入P型杂质离子时的能量为2KeV～5KeV，剂量为1e14～5e14atom/cm2，角度为15～30度。
在另一实施例中，第二浅掺杂离子注入注入的杂质离子除了P型杂质离子外，还包括C、N或F离子中一种或几种。C、N或F离子用于防止硅锗区206中第一浅掺杂离子注入和第二浅掺杂离子注入时注入的杂质离子在退火时向沟道区域的方向扩散过快，防止产生短沟道效应。
第二浅掺杂离子注入注入C、N或F离子中一种或几种时的能量为0.5～20kev，注入角度为0～40°，注入剂量为1E14～1E15atom/cm2，以使得C、N或F离子注入到侧墙207底部的硅锗区206中，并能有效的防止侧墙207底部的硅锗区206注入的杂质离子向沟道区域的方向扩散过快(C、N或F可以与半导体衬底中的缺陷进行复合(或者说它们的存在能形成缺陷聚合区域)从而形成难分解的缺陷团簇，从而降低缺陷辅助的杂质离子增强扩散)。
形成第二浅掺杂区后，进行第一退火工艺，使得第一浅掺杂区和第二浅掺杂区中的杂质离子扩散。在后续刻蚀半导体衬底形成凹槽时，侧墙底部剩余的硅锗区206仍会存在第一浅掺杂区和第二浅掺杂区，第二浅掺杂区的深度大于第一浅掺杂区的深度，且第二浅掺杂区的边缘的离栅极结构边缘的垂直距离大于第一浅掺杂区离栅极结构的边缘的垂直距离。
参考图6，以所述侧墙207和侧墙207底部剩余的锗硅区206为掩膜，刻蚀侧墙207和剩余的锗硅区206两侧的半导体衬底200，在侧墙207和侧墙207底部剩余的锗硅区206两侧的半导体衬底200内形成sigma形状的凹槽208。
所述sigma形状的凹槽形成过程：以所述侧墙和侧墙底部剩余的锗硅区为掩膜，采用干法刻蚀工艺刻蚀侧墙和剩余的锗硅区两侧的半导体衬底，在侧墙和侧墙底部剩余的锗硅区两侧的半导体衬底内形成矩形凹槽；采用湿法刻蚀工艺继续刻蚀矩形凹槽，形成sigma形状的凹槽。
在一实施例中，所述干法刻蚀工艺采用的气体包括：CF4、HBr、He和O2，CF4的气体流量为20-200sccm，HBr的气体流量为50-1000sccm，He的气体流量为200-1000sccm，O2的气体流量为5-20sccm，腔室温度为40-80℃，腔室压力为5-50mTorr，射频功率为400-750W，偏置功率为0-100W；刻蚀时间为20-80S，所述湿法刻蚀工艺采用刻蚀容易为TMAH溶液或NH3.H2O溶液，TMAH溶液或NH3.H2O溶液的质量百分比为1％-5％，刻蚀时间为20-80S，在形成形状规则的sigma形状的凹槽208的同时，减少对侧墙207底部的硅锗区206的刻蚀损伤。
参考图7，在sigma形状的凹槽208(参考图6)中填充压应力材料，形成源漏区209。
所述压应力材料为硅锗或锡锗硅。
压应力材料为硅锗时，压应力材料中锗原子的含量为20～50％，以使得压应力材料对沟道区域能施加较大的压应力。
所述压应力材料为锡锗硅时，压应力材料中锗原子的含量为20～50％，锡原子的含量为1～5％，以提高压应力材料对沟道区域施加的压应力。
压应力材料的填充工艺为选择性外延工艺。
所述压应力材料中掺杂有P型杂质离子，P型的杂质离子可以为硼离子、镓离子或铟离子中的一种或几种。
可以通过自掺杂工艺或离子注入工艺在压应力材料中掺杂P型杂质离子。
当所述压应力材料为硅锗时，在一实施例中，所述选择性外延工艺时的腔室温度为600～1100摄氏度，压强1～500托，硅源气体是SiH4或DCS，硅源气体流量为30-500sccm，锗源气体是GeH4，锗源气体的流量为5-400sccm，还包括HCl气体以及氢气，氢气作为载气，HCl气体作为选择性气体，用于增加沉积的选择性，所述选择性气体也可以为氯气，HCl的流量为50-200sccm，氢气的流量是0.1～50slm，以减小形成的压应力材料中的缺陷，并减小形成的压应力材料与侧墙207底部的硅锗区206之间层错，以保证源漏区和侧墙207底部的硅锗区206对沟道区域能施加较大的压应力。
当采用自掺杂工艺掺杂杂质离子时，所述选择性外延工艺还包括杂质源气体，在一实施例中，所述杂质源气体为PH3或AsH3。
当压应力材料为锡锗硅时，在一实施例中，所述选择性外延工艺时的腔室温度为600～1100摄氏度，压强1～500托，硅源气体是SiH4或DCS，硅源气体流量为30-500sccm，锗源气体是GeH4，锗源气体的流量为5-400sccm，锡源气体为SnCl4，锡源气体流量为1～300sccm，还包括HCl气体以及氢气，氢气作为载气，HCl气体作为选择性气体，用于增加沉积的选择性，所述选择性气体也可以为氯气，HCl的流量为50-200sccm，氢气的流量是0.1～50slm，并减小形成的压应力材料与侧墙207底部的硅锗区206之间层错，以保证源漏区和侧墙207底部的硅锗区206对沟道区域能施加较大的压应力。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种PMOS晶体管的形成方法，其特征在于，包括：
提供半导体衬底，在所述半导体衬底上形成栅极结构；
以所述栅极结构为掩膜，在栅极结构两侧的半导体衬底中注入锗离子，在栅极结构两侧的半导体衬底内形成锗硅区；
在所述栅极结构的侧壁表面以及与侧壁相邻的部分锗硅区表面形成侧墙；
以所述侧墙为掩膜，刻蚀去除侧墙两侧的锗硅区，暴露出锗硅区底部的半导体衬底；
以所述侧墙和侧墙底部剩余的锗硅区为掩膜，刻蚀侧墙和剩余的锗硅区两侧的半导体衬底，在侧墙和侧墙底部剩余的锗硅区两侧的半导体衬底内形成sigma形状的凹槽；
在sigma形状的凹槽中填充压应力材料，形成源漏区。
2.如权利要求1所述的PMOS晶体管的形成方法，其特征在于，在栅极结构两侧的半导体衬底中注入锗离子采用离子注入工艺。
3.如权利要求2所述的PMOS晶体管的形成方法，其特征在于，所述注入锗离子时的离子注入工艺的注入能量为10～100Kev，注入角度为0～40°，注入剂量为5E15～5E16atom/cm2。
4.如权利要求1所述的PMOS晶体管的形成方法，其特征在于，在半导体衬底中注入锗离子的同时或之后，还包括：以所述栅极结构为掩膜，对栅极结构两侧的半导体衬底进行第一浅掺杂离子注入，在栅极结构两侧的半导体衬底内形成第一浅掺杂区。
5.如权利要求1所述的PMOS晶体管的形成方法，其特征在于，在半导体衬底中注入锗离子之后，还包括：在栅极结构的侧壁表面形成偏移侧墙，以所述栅极结构和偏移侧墙为掩膜，对栅极结构和偏移侧墙两侧的半导体衬底进行第一浅掺杂离子注入，在栅极结构和偏移侧墙两侧的半导体衬底内形成第一浅掺杂区。
6.如权利要求4或5所述的PMOS晶体管的形成方法，其特征在于，刻蚀去除侧墙两侧的锗硅区，暴露出锗硅区底部的半导体衬底之后，还包括：以所述侧墙和侧墙底部剩余的锗硅区为掩膜，对所述侧墙和剩余的锗硅区两侧半导体衬底进行第二浅掺杂离子注入，在所述侧墙和剩余的锗硅区两侧的半导体衬底内形成第二浅掺杂区，第二浅掺杂区的深度大于第一浅掺杂区的深度，且第二浅掺杂区的边缘的离栅极结构边缘的垂直距离大于第一浅掺杂区离栅极结构的边缘的垂直距离。
7.如权利要求6所述的PMOS晶体管的形成方法，其特征在于，形成第二浅掺杂区后，进行第一退火工艺，使得第一浅掺杂区和第二浅掺杂区中的杂质离子扩散。
8.如权利要求6所述的PMOS晶体管的形成方法，其特征在于，第一浅掺杂离子注入和第二浅掺杂离子注入注入的杂质离子为P型杂质离子。
9.如权利要求8所述的PMOS晶体管的形成方法，其特征在于，所述第一浅掺杂离子注入注入P型杂质离子时的能量为2KeV～5KeV，剂量为5e14～2e15atom/cm2，角度为0～7度，所述第二浅掺杂离子注入注入P型杂质离子时的能量为2KeV～5KeV，剂量为1e14～5e14atom/cm2，角度为15～30度。
10.如权利要求8所述的PMOS晶体管的形成方法，其特征在于，第二浅掺杂离子注入注入的杂质离子除了P型杂质离子外，还包括C、N或F离子中一种或几种。
11.如权利要求10所述的PMOS晶体管的形成方法，其特征在于，第二浅掺杂离子注入注入C、N或F离子中一种或几种时的能量为0.5～20kev，注入角度为0～40°，注入剂量为1E14～1E15atom/cm2。
12.如权利要求1所述的PMOS晶体管的形成方法，其特征在于，sigma形状的凹槽形成过程：以所述侧墙和侧墙底部剩余的锗硅区为掩膜，采用干法刻蚀工艺刻蚀侧墙和剩余的锗硅区两侧的半导体衬底，在侧墙和侧墙底部剩余的锗硅区两侧的半导体衬底内形成矩形凹槽；采用湿法刻蚀工艺继续刻蚀矩形凹槽，形成sigma形状的凹槽。
13.如权利要求12所述的PMOS晶体管的形成方法，其特征在于，所述干法刻蚀工艺采用的气体包括：CF4、HBr、He和O2，CF4的气体流量为20-200sccm，HBr的气体流量为50-1000sccm，He的气体流量为200-1000sccm，O2的气体流量为5-20sccm，腔室温度为40-80℃，腔室压力为5-50mTorr，射频功率为400-750W，偏置功率为0-100W；刻蚀时间为20-80S。
14.如权利要求12所述的PMOS晶体管的形成方法，其特征在于，所述湿法刻蚀工艺采用刻蚀容易为TMAH溶液或NH3.H2O溶液，TMAH溶液或NH3.H2O溶液的质量百分比为1％-5％，刻蚀时间为20-80S。
15.如权利要求1所述的PMOS晶体管的形成方法，其特征在于，所述压应力材料为硅锗或锡锗硅。
16.如权利要求15所述的PMOS晶体管的形成方法，其特征在于，压应力材料为硅锗时，压应力材料中锗原子的含量为20～50％。
17.如权利要求15所述的PMOS晶体管的形成方法，其特征在于，所述压应力材料为锡锗硅时，压应力材料中锗原子的含量为20～50％，锡原子的含量为1～5％。
18.如权利要求1所述的PMOS晶体管的形成方法，其特征在于，压应力材料的填充工艺为选择性外延工艺。
19.如权利要求1所述的PMOS晶体管的形成方法，其特征在于，所述压应力材料中掺杂有P型杂质离子。
20.如权利要求19所述的PMOS晶体管的形成方法，其特征在于，通过自掺杂工艺或离子注入工艺在压应力材料中掺杂P型杂质离子。
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CN110310924A (zh) * 2018-03-20 2019-10-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制作方法
CN111627861A (zh) * 2019-02-28 2020-09-04 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
CN111627861B (zh) * 2019-02-28 2024-03-19 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
CN111081764A (zh) * 2019-12-30 2020-04-28 深圳第三代半导体研究院 一种具有嵌入式源漏的晶体管及其制备方法

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