CN106856194B - 半导体芯片及其制造方法 - Google Patents
半导体芯片及其制造方法 Download PDFInfo
- Publication number
- CN106856194B CN106856194B CN201610900692.4A CN201610900692A CN106856194B CN 106856194 B CN106856194 B CN 106856194B CN 201610900692 A CN201610900692 A CN 201610900692A CN 106856194 B CN106856194 B CN 106856194B
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- upper wiring
- semiconductor chip
- pad
- passivation layer
- wiring
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Abstract
提供了半导体芯片及其制造方法。可以提供一种半导体芯片,该半导体芯片包括:半导体器件层,包括焊盘区域和单元区域;多条最上布线,形成在半导体器件层上并以相等的距离布置在单元区域中;钝化层,形成在单元区域和焊盘区域中;多个热凸起,设置在钝化层上以与所述多条最上布线电绝缘。所述半导体器件层可以包括位于焊盘区域中的多个硅通孔(TSV)结构。所述多条最上布线可以沿一个方向平行延伸并具有相同的宽度。所述钝化层可以至少覆盖单元区域中的所述多条最上布线的顶表面并包括具有波浪形状的顶表面。
Description
本申请要求于2015年12月9日在韩国知识产权局提交的第10-2015-0175349号韩国专利申请的优先权,该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
发明构思涉及半导体芯片、包括所述半导体芯片的半导体封装件和/或制造所述半导体芯片的方法,更具体地讲,涉及具有硅通孔(TSV)结构的半导体芯片、包括所述半导体芯片的半导体封装件和/或制造具有TSV结构的半导体芯片的方法。
背景技术
随着电子工业的迅速发展和用户需求的提高,电子装置正在变得越来越小型化和轻量化。除了小型化和轻量化之外,应用于电子装置的半导体封装件还应该具有相对高的性能和相对大的容量。为实现这样的目标,正在对具有TSV结构的半导体芯片和包括该半导体芯片的半导体封装件进行不断地研究和开发。
发明内容
发明构思提供了半导体芯片、包括该半导体芯片的半导体封装件和/或制造该半导体芯片的方法,除了小型化和轻量化之外,还实现了相对高的性能和相对大的容量。
根据发明构思的示例实施例,一种半导体芯片包括:半导体器件层,包括焊盘区域和单元区域,半导体器件层包括位于焊盘区域中的多个硅通孔(TSV)结构;多条最上布线,位于半导体器件层上,所述多条最上布线以相等的距离布置在单元区域中,所述多条最上布线具有相同的宽度并且沿一个方向平行延伸;钝化层,位于单元区域和焊盘区域中,钝化层至少覆盖单元区域中的所述多条最上布线的顶表面,钝化层的位于单元区域中的顶表面具有波浪形状;多个热凸起,位于钝化层上,所述多个热凸起与所述多条最上布线电绝缘。
根据发明构思的示例实施例,一种半导体封装件包括:封装基底和顺序地堆叠在封装基底上的多个半导体芯片,所述多个半导体芯片中的每个包括焊盘区域和单元区域,其中,所述多个半导体芯片中的每个包括:半导体器件层,包括位于焊盘区域中的多个硅通孔(TSV)结构;多条最上布线,位于半导体器件层上,所述多条最上布线以相等的距离布置在单元区域中,所述多条最上布线具有相同的宽度并且沿一个方向平行延伸;多个焊盘,位于半导体器件层上,所述多个焊盘连接到位于焊盘区域中的所述多个TSV结构;钝化层,包括凸起孔,所述凸起孔暴露所述多个焊盘中的每个焊盘的顶表面的一部分,所述钝化层至少覆盖位于单元区域中的所述多条最上布线的顶表面;多个热凸起,位于单元区域中的钝化层上,所述多个热凸起与所述多条最上布线电绝缘;多个信号凸起,位于焊盘区域中的钝化层上,所述多个信号凸起通过凸起孔电连接到所述多个焊盘。
根据发明构思的示例实施例,一种制造半导体芯片的方法包括:制备包括焊盘区域和单元区域的半导体器件层,半导体器件层包括位于焊盘区域中的多个硅通孔(TSV)结构;在半导体器件层上形成多条最上布线,使得所述多条最上布线在单元区域中以相等的距离布置,所述多条最上布线沿一个方向平行延伸并且具有相同的宽度;在焊盘区域中形成多个焊盘,使得所述多个焊盘连接到位于焊盘区域中的所述多个TSV结构;形成钝化层以覆盖所述多个焊盘中的每个焊盘的顶表面的至少一部分和位于单元区域中的所述多条最上布线,钝化层包括具有台阶高度的顶表面;在钝化层上形成掩模图案,使得掩模图案暴露所述多个焊盘中的每个焊盘的顶表面的所述至少一部分和钝化层的一部分;在由掩模图案暴露的所述多个焊盘中的每个焊盘的顶表面的所述至少一部分和钝化层的所述部分上,形成柱层和初始焊料层。
根据发明构思的示例实施例,一种包括焊盘区域和单元区域的半导体芯片包括:多个硅通孔(TSV)结构,位于焊盘区域中;多条最上布线,位于单元区域中,所述多条最上布线形成半导体芯片的电路构造的一部分,所述多条最上布线中的邻近最上布线分隔开相同的距离,所述多条最上布线中的每条最上布线具有相同的宽度,所述多条最上布线沿一个方向平行延伸;钝化层,位于单元区域和焊盘区域中,所述钝化层至少覆盖位于单元区域中的所述多条最上布线的顶表面,钝化层的位于单元区域中的顶表面具有波浪形状;多个热凸起,位于钝化层上,所述多个热凸起与所述多条最上布线电绝缘;以及多个焊盘,位于焊盘区域中的半导体器件层上。
附图说明
通过下面结合附图进行的详细描述,将会更清楚地理解发明构思的示例实施例,在附图中:
图1是示意性示出根据示例实施例的半导体芯片的构造的布局图;
图2是示意性示出根据示例实施例的半导体芯片的主体的构造的平面图;
图3是示意性示出根据示例实施例的半导体芯片的主体的构造的剖视图;
图4是示意性示出根据示例实施例的半导体芯片的主体的构造的平面图;
图5是示意性示出根据示例实施例的半导体芯片的主体的构造的平面图;
图6是用于描述包括在根据示例实施例的半导体芯片中的两组布线的连接关系的概念图;
图7是示意性示出根据示例实施例的半导体芯片的构造的剖视图;
图8是示意性示出根据示例实施例的半导体芯片的构造的剖视图;
图9是示意性示出根据示例实施例的半导体芯片的构造的剖视图;
图10、图11、图12、图13、图14和图15是示出根据示例实施例的制造半导体芯片的方法的剖视图;
图16是示出包括根据示例实施例的半导体芯片的半导体封装件的剖视图;
图17是示出包括根据示例实施例的半导体芯片的半导体封装件的剖视图;
图18是示出包括根据示例实施例的半导体芯片的半导体封装件的剖视图;
图19是示出根据示例实施例的半导体模块的主体的构造的平面图;
图20是示意性示出根据示例实施例的半导体封装件的构造的示图;
图21是示出包括根据示例实施例的半导体封装件的电子系统的示图。
具体实施方式
图1是示意性示出根据示例实施例的半导体芯片10的构造的布局图。
参照图1,半导体芯片10可以包括焊盘区域PR和单元区域CR。例如,半导体芯片10可以是存储半导体芯片。例如,存储半导体芯片可以是易失性存储半导体芯片,诸如动态随机存取存储器(DRAM)或静态随机存取存储器(SRAM)等,或者非易失性存储半导体芯片,诸如相变随机存取存储器(PRAM)、磁阻随机存取存储器(MRAM)、铁电随机存取存储器(FRAM)或电阻随机存取存储器(RRAM)等。在一些示例实施例中,半导体芯片10可以是高带宽存储(HBM)DRAM。
当半导体芯片10是存储半导体芯片时,可以在单元区域CR中设置多个存储单元(未示出),所述单元区域CR是与焊盘区域PR不同的单独区域。
电连接到键合焊盘PAD的多个贯穿电极(未示出)可以设置在焊盘区域PR中。焊盘区域PR可以具有一定的宽度并且可以在半导体芯片10的相对的两个边缘之间延伸。例如,焊盘区域PR的宽度可以是大约几百μm。焊盘区域PR可以在长轴方向上沿半导体芯片10的中心轴设置,但不限于此。在一些实施例中,焊盘区域PR可以在短轴方向上沿半导体芯片10的中心轴设置或者可以沿半导体芯片10的边缘设置。
可以布置多个键合焊盘PAD,以在焊盘区域PR中形成具有列和行的矩阵。例如,几百至几千个键合焊盘PAD可以以矩阵的形式布置在焊盘区域PR中。在焊盘区域PR中,多个键合焊盘PAD可以按列方向上的几十μm的一定节距和行方向上的几十μm的一定节距来布置以形成矩阵。例如,多个键合焊盘PAD可以按列方向或行方向上的40μm至50μm的节距来布置以形成矩阵。例如,多个键合焊盘PAD可以具有边长为20μm至40μm的四边形状。
设置在焊盘区域PR中的多个键合焊盘PAD可以按图1中的焊盘区域PR中示出的一个矩形来形成矩阵,但不限于此。例如,设置在焊盘区域PR中的多个键合焊盘PAD可以按彼此分隔开的偶数个四边形(例如,两个四边形或者四个或更多个四边形)形成矩阵。
在一些示例实施例中,可以基于例如标准(诸如JEDEC标准)来限定半导体芯片10的焊盘区域PR的布置和/或焊盘区域PR中的多个键合焊盘PAD的布置。
图2是示意性示出根据示例实施例的半导体芯片10的主体的构造的平面图。
参照图2,半导体芯片10可以包括焊盘区域PR和单元区域CR。多个键合焊盘PAD和设置在多个键合焊盘PAD中的每个上的信号凸起BP-S可以设置在焊盘区域PR中。信号凸起BP-S可以从外部供应有用于对半导体芯片10进行操作的控制信号、电源信号和接地信号中的至少一种。信号凸起BP-S可以从外部供应有将被存储在半导体芯片10中的数据信号。信号凸起BP-S可以向外部供应存储在半导体芯片10中的数据。
最上布线M3和设置在最上布线M3上的多个热凸起BP-T可以设置在单元区域CR中。热凸起BP-T可以将半导体芯片10的操作期间产生的热量散发到外部。热凸起BP-T可以不电连接到设置在半导体芯片10中并构成半导体装置的多个单体器件(individual device)。在一些示例实施例中,热凸起BP-T可以与设置在半导体芯片10中的元件热接触以便被用作热量传递和散发的路径。
在本公开中,最上布线指的是多个水平面(level)中的布线之中的最上面的布线,最上布线形成半导体芯片10的电路构造的一部分。例如,形成在半导体芯片10上以用于调整信号凸起BP-S的布置和节距的重分配布线基本上不应用于半导体芯片10的电路构造。因此,重分配布线不与这里定义的最上布线对应。
在本公开中,描述了包括三层布线的半导体芯片,但不限于此。在其他示例实施例中,半导体装置可以包括两层或者四层或更多层布线。
在本公开中,描述了没有设置重分配布线的情况,但示例实施例不限于此。例如,当重分配布线未形成在半导体芯片10中时,多个键合焊盘PAD和最上布线M3可以一起形成并且可以设置在同一层上。例如,当重分配布线形成在半导体芯片10中时,重分配布线可以设置在与设置有多个键合焊盘PAD和最上布线M3的层分开的另一层上。在这样的情况下,信号凸起BP-S可以设置在通过多个键合焊盘PAD连接到重分配布线的连接焊盘上。在一些示例实施例中,如图2中所示,多个键合焊盘PAD的区域可以比信号凸起BP-S的区域宽。
多个键合焊盘PAD可以分别电连接到多个信号凸起BP-S。多个信号凸起BP-S均可以具有等于第一距离D1的水平宽度。多个信号凸起BP-S可以按第一节距P1布置。分别与多个信号凸起BP-S对应的多个键合焊盘PAD均可以具有四边形状,该四边形状的边长的值大于第一距离D1。例如,当第一距离D1为25μm时,多个键合焊盘PAD中的每个的边长可以是30μm。
最上布线M3可以与多个热凸起BP-T电绝缘。例如,可以在最上布线M3与多个热凸起BP-T之间设置钝化层(图3的150)以使最上布线M3与多个热凸起BP-T电绝缘。
多条最上布线M3可以沿一个方向(例如,图2的水平方向)平行地延伸。多条最上布线M3可以具有相同的宽度,即,第一宽度W1,并且可以按相等的距离布置。多条最上布线M3可以按等于第二宽度W2的节距布置。
多个热凸起BP-T均可以具有等于第二距离D2的水平宽度。多个热凸起BP-T可以按第二节距P2布置。第二距离D2可以具有等于或大于第一距离D1的值。第二节距P2可以具有等于或大于第一节距P1的值。在一些示例实施例中,第二距离D2和第一距离D1可以具有相同的值,第二节距P2可以具有近似第一节距P1的值的两倍的值。
多条最上布线M3均可以具有第一宽度W1,多条最上布线M3可以在单元区域CR中具有等于第二宽度W2的节距并且可以沿一个方向(例如,图2的水平方向)平行布置。在一些示例实施例中,多条最上布线M3均可以具有第一宽度W1,多条最上布线M3可以具有等于第二宽度W2的节距,多条最上布线M3可以设置在多个热凸起BP-T下面和/或与多个热凸起BP-T邻近的位置处,多个热凸起BP-T可以沿一个方向(例如,图2的水平方向)平行延伸。在单元区域CR中,多条最上布线M3可以在未设置有多个热凸起BP-T的位置处具有不同的宽度、不同的节距和/或不同的延伸方向。
多条最上布线M3中的一些可以从单元区域CR延伸到焊盘区域PR并且可以与邻近的键合焊盘PAD分隔开并在邻近的键合焊盘PAD之间延伸。
多条最上布线M3中的一些可以从单元区域CR延伸到焊盘区域PR。多条最上布线M3中的一些可以从单元区域CR延伸到焊盘区域PR并且可以连接到相应的键合焊盘PAD。多条最上布线M3之中的连接到相应键合焊盘PAD的布线可以被称为连接布线M3-1和M3-2。
多个键合焊盘PAD中的一些可以连接到一条最上布线M3或多条最上布线M3。与多个键合焊盘PAD中的第二焊盘PAD-2连接的最上布线M3的数量可以比连接到第一焊盘PAD-1的最上布线M3的数量更多。例如,第一焊盘PAD-1可以连接到一条第一连接布线M3-1,第二焊盘PAD-2可以连接到第二连接布线M3-2。第二连接布线M3-2可以包括两条或更多条最上布线M3。即,连接到第二焊盘PAD-2的两条或更多条邻近的最上布线M3(即,第二连接布线M3-2)可以彼此电连接以用作一条布线。彼此电连接以用作一条布线的第二连接布线M3-2中的至少一些可以在热凸起BP-T下面延伸。
多个键合焊盘PAD中的一些可以不连接到最上布线M3。
图3是示意性示出根据示例实施例的半导体芯片10的主体的构造的剖视图。
参照图3,半导体芯片10可以包括焊盘区域PR和单元区域CR。半导体芯片10可以包括半导体器件层100和设置在半导体器件层100上的多条最上布线M3。半导体芯片10的焊盘区域PR还可以包括设置在半导体器件层100上的键合焊盘PAD。
在本公开中,半导体器件层100可以包括:多个单体器件,在半导体芯片10中设置在多条最上布线M3的下面并且在半导体基底上构成半导体装置;多个元件,使多个单体器件电连接;层间绝缘层和布线间绝缘层,设置在多个元件之间。半导体器件层100还可以包括电连接到键合焊盘PAD的TSV结构。将参照图7至图9描述半导体器件层100的元件。
例如,半导体芯片10可以是存储半导体芯片。在一些示例实施例中,半导体芯片10可以是具有TSV结构的HBM DRAM。
键合焊盘PAD和多条最上布线M3可以一起形成并且可以设置在同一层上。在一些示例实施例中,键合焊盘PAD和多条最上布线M3可以形成为具有几百nm至几μm的厚度。
多条最上布线M3可以具有相同的宽度,即,第一宽度W1,并且可以按相等的距离布置。第一宽度W1可以是几百nm。在一些示例实施例中,第一宽度W1可以是200nm至500nm。多条最上布线M3可以按等于第二宽度W2的节距布置。第二宽度W2可以具有大于第一宽度W1的值,在一些示例实施例中,第二宽度W2可以等于或小于1μm。
钝化层150可以形成在键合焊盘PAD和多条最上布线M3上。钝化层150可以包括暴露键合焊盘PAD的顶部的至少一部分的凸起孔150H。例如,钝化层150可以由无机绝缘材料形成。在一些示例实施例中,钝化层150可以由氧化硅形成。
钝化层150可以具有几百nm至几μm的厚度。多条最上布线M3中的每条的形状可以部分地转移到钝化层150的顶部,钝化层150的顶部可以具有第一台阶高度R1。在一些示例实施例中,钝化层150的顶部可以具有像波浪形状的表面一样地不断重复的凹凸形状,第一台阶高度R1可以是钝化层150的顶部的波浪形状的顶部与底部之间的高度。
第一台阶高度R1可以具有比多条最上布线M3中的每条最上布线的厚度小的值。第一台阶高度R1可以具有等于或小于100nm的值。
信号凸起BP-S可以在焊盘区域PR中设置在键合焊盘PAD上。信号凸起BP-S可以从外部供应有用于对半导体芯片10进行操作的控制信号、电源信号或接地信号中的至少一种。信号凸起BP-S可以从外部供应有将存储在半导体芯片10中的数据信号。信号凸起BP-S可以向外部供应存储在半导体芯片10中的数据。信号凸起BP-S可以通过凸起孔150H而电连接到键合焊盘PAD。凸起孔150H的直径可以具有比信号凸起BP-S的宽度和键合焊盘PAD的宽度小的值。因此,信号凸起BP-S的底部的一部分可以与键合焊盘PAD接触,所述底部的其余部分可以与钝化层150接触。
以钝化层150位于最上布线M3上并且位于热凸起BP-T与最上布线M3之间的方式设置在最上布线M3上的热凸起BP-T可以设置在单元区域CR中。热凸起BP-T可以将半导体芯片10的操作期间产生的热量散发到外部。热凸起BP-T可以通过钝化层150来与最上布线M3电绝缘。热凸起BP-T可以不连接到被设置在半导体芯片10的半导体器件层100上并构成半导体装置的多个单体器件。在一些示例实施例中,热凸起BP-T可以与设置在半导体器件层100中的元件热接触以便被用作热量传递和散发的路径。
信号凸起BP-S和热凸起BP-T均可以包括柱层162和设置在柱层162上的焊料层164。柱层162可以由例如铜(Cu)、镍(Ni)和/或金(Au)等形成。柱层162可以由例如从Cu、Ni和Au或其合金之中选择的一种金属形成或者可以具有包括从Cu、Ni和Au之中选择的多种金属的多层结构。柱层162可以通过电镀工艺形成。
焊料层164可以包括锡(Sn)和银(Ag)的合金,并且根据情况,可以向焊料层164中添加铜(Cu)、钯(Pd)、铋(Bi)和/或锑(Sb)等。可以形成初始的焊料层,然后,可以通过热处理来使焊料层164形成为具有凸出的形状。可以通过电镀工艺来形成初始的焊料层。在一些示例实施例中,柱层162和初始的焊料层均可以通过单独的电镀工艺形成。
信号凸起BP-S和热凸起BP-T可以一起形成,并且信号凸起BP-S的上端和热凸起BP-T的上端可以具有同一水平面(level)。
热凸起BP-T的底部,即,构成热凸起BP-T的柱层的底部可以与钝化层150的顶部接触。因此,热凸起BP-T的底部可以具有与钝化层150的顶部对应的诸如波浪形状的表面的凹凸形状。
在形成信号凸起BP-S和热凸起BP-T的光刻工艺中,因为由最上布线M3造成的台阶高度和/或因为钝化层位于单元区域CR中的顶部的形状,导致在照相曝光(photoexposure)中会发生反射。这里,当多条最上布线M3中的至少一些最上布线具有不同的宽度或者以不同的间隔布置时,在钝化层150的顶部发生漫反射(diffuse reflection),由于该原因,热凸起BP-T的形状异常地形成。当热凸起BP-T的形状由于漫反射而异常地形成时,在信号凸起BP-S与热凸起BP-T之间出现高度差。当在信号凸起BP-S与热凸起BP-T之间出现高度差时,在信号凸起BP-S和热凸起BP-T的至少一部分中出现接触缺陷。因此,半导体芯片10不能正常地操作,或者从半导体芯片10产生的热量不能正常地散发。
例如,当在钝化层150上进一步形成用于抵消钝化层150的顶部的台阶高度的包括诸如光敏聚酰亚胺(PSPI)等的有机绝缘材料的保护层,以便防止在照相曝光中发生漫反射时,半导体芯片10的厚度增大,并且会由于保护层与半导体器件层100之间的热膨胀系数差异而在半导体芯片10中出现翘曲。即使在这种情况下,也会在信号凸起BP-S和热凸起BP-T的至少一些中出现接触缺陷,因此,半导体芯片10不会正常地操作,或者从半导体芯片10产生的热量不会正常地散发。
然而,在根据示例实施例的半导体芯片10中,多条最上布线M3可以在单元区域RC中具有相同的宽度并且可以按相等的距离布置,因此,钝化层150的顶部可以具有不断重复的波浪的表面形状,从而减轻或防止在照相曝光中发生漫反射。因此,正常地形成热凸起BP-T的形状,可以减轻或防止在半导体芯片10中出现翘曲。因此,信号凸起BP-S的上端和热凸起BP-T的上端可以具有同一水平面。因此,可以减轻或防止在信号凸起BP-S和热凸起BP-T中出现接触缺陷,从而确保半导体芯片10的可靠性和/或有效地散发从半导体芯片10产生的热量。
图4是示意性示出根据示例实施例的半导体芯片10a的主体的构造的平面图。在参照图4提供的描述中,可以省略与上面参照图1至图3描述的细节相似或相同的细节,并且同样的附图标记表示同样的元件。
参照图4,半导体芯片10a可以包括焊盘区域PR和单元区域CR。多个键合焊盘PAD以及设置在多个键合焊盘PAD上的信号凸起BP-S可以设置在焊盘区域PR中。最上布线M3和设置在最上布线M3上的多个热凸起BP-Ta可以设置在单元区域CR中。
多个键合焊盘PAD可以分别电连接到多个信号凸起BP-S。多个信号凸起BP-S均可以具有等于第一距离D1的水平宽度。多个信号凸起BP-S可以按第一节距P1布置。分别与多个信号凸起BP-S对应的多个键合焊盘PAD均可以具有边长的值大于第一距离D1的四边形状。
最上布线M3可以与多个热凸起BP-Ta电绝缘。例如,可以在最上布线M3与多个热凸起BP-Ta之间设置钝化层(图3的150)以使最上布线M3与多个热凸起BP-Ta电绝缘。
多条最上布线M3可以沿一个方向(例如,图4的水平方向)平行延伸。多条最上布线M3可以具有相同的宽度,即,第一宽度W1,并且可以按相等的距离布置。多条最上布线M3可以按等于第二宽度W2的节距布置。
多个热凸起BP-Ta均可以具有等于第二距离D2a的宽度。多个热凸起BP-Ta可以按第二节距P2a布置。第二距离D2a可以具有等于或大于第一距离D1的值。第二节距P2a可以具有等于或大于第一节距P1的值。在一些示例实施例中,第二距离D2a和第一距离D1可以具有相同的值,第二节距P2a可以具有与第一节距P1的值相同的值。
多条最上布线M3均可以具有相同的第一宽度W1,多条最上布线M3可以在单元区域CR中具有等于第二宽度W2的节距并可以沿一个方向(例如,图4的水平方向)平行布置。在一些示例实施例中,多条最上布线M3均可以具有第一宽度W1,多条最上布线M3可以具有等于第二宽度W2的节距,多条最上布线M3可以设置在多个热凸起BP-Ta下面和/或与多个热凸起BP-Ta邻近的位置处,多个热凸起BP-Ta可以沿一个方向(图4的水平方向)平行延伸。在单元区域CR中,多条最上布线M3可以在未设置有多个热凸起BP-Ta的位置处具有不同的宽度、不同的节距和/或不同的延伸方向。
多条最上布线M3中的一些可以从单元区域CR延伸到焊盘区域PR并且可以与邻近的键合焊盘PAD分隔开并在邻近的键合焊盘PAD之间延伸。
多条最上布线M3中的一些可以从单元区域CR延伸到焊盘区域PR。多条最上布线M3中的一些可以从单元区域CR延伸到焊盘区域PR并且可以连接到相应的键合焊盘PAD。多条最上布线M3之中的连接到相应键合焊盘PAD的布线可以被称为连接布线M3-1和M3-2。
多个键合焊盘PAD中的一些可以连接到一条最上布线M3或多条最上布线M3。与多个键合焊盘PAD中的第二焊盘PAD-2连接的最上布线M3的数量可以比连接到第一焊盘PAD-1的最上布线M3的数量更多。连接到第二焊盘PAD-2的两条或更多条邻近的最上布线M3(例如,第二连接布线M3-2)可以彼此电连接以用作一条布线。彼此电连接以用作一条布线的第二连接布线M3-2中的至少一些可以在热凸起BP-Ta下面延伸。
多个键合焊盘PAD中的一些可以不连接到最上布线M3。
图5是示意性示出根据示例实施例的半导体芯片10b的主体的构造的平面图。在参照图5提供的描述中,可以省略与上面参照图1至图4描述的细节相似或相同的细节,并且同样的附图标记表示同样的元件。
参照图5,半导体芯片10b可以包括焊盘区域PR和单元区域CR。多个键合焊盘PAD以及设置在多个键合焊盘PAD中的每个上的信号凸起BP-S可以设置在焊盘区域PR中。最上布线M3和设置在最上布线M3上的多个热凸起BP-Tb可以设置在单元区域CR中。
多个键合焊盘PAD可以分别电连接到多个信号凸起BP-S。多个信号凸起BP-S均可以具有等于第一距离D1的水平宽度。多个信号凸起BP-S可以按第一节距P1布置。分别与多个信号凸起BP-S对应的多个键合焊盘PAD均可以具有边长的值大于第一距离D1的四边形状。
最上布线M3可以与多个热凸起BP-Tb电绝缘。例如,可以在最上布线M3与多个热凸起BP-Tb之间设置钝化层(图3的150)以使最上布线M3与多个热凸起BP-Tb电绝缘。
多条最上布线M3可以沿一个方向(例如,图5的水平方向)平行地延伸。多条最上布线M3可以具有相同的宽度,即,第一宽度W1,并且可以按相等的距离布置。多条最上布线M3可以按等于第二宽度W2的节距布置。
多个热凸起BP-Tb均可以具有等于第二距离D2b的宽度。多个热凸起BP-Tb可以按第二节距P2b布置。第二距离D2b可以具有等于或大于第一距离D1的值。第二节距P2b可以具有等于或大于第一节距P1的值。在一些示例实施例中,第二距离D2b可以具有近似第一距离D1的值的两倍的值,第二节距P2b可以具有近似第一节距P1的值的两倍的值。
多条最上布线M3均可以具有第一宽度W1,多条最上布线M3可以在单元区域CR中具有等于第二宽度W2的节距并且可以沿一个方向(例如,图5的水平方向)平行布置。在一些示例实施例中,多条最上布线M3均可以具有第一宽度W1,多条最上布线M3可以具有等于第二宽度W2的节距,多条最上布线M3可以设置在多个热凸起BP-Tb下面和/或与多个热凸起BP-Tb邻近的位置处,多个热凸起BP-Tb可以沿一个方向(例如,图5的水平方向)平行延伸。在单元区域CR中,多条最上布线M3可以在未设置有多个热凸起BP-Tb的位置处具有不同的宽度、不同的节距和/或不同的延伸方向。
多条最上布线M3中的一些可以从单元区域CR延伸到焊盘区域PR并且可以与邻近的键合焊盘PAD分隔开并在邻近的键合焊盘PAD之间延伸。
多条最上布线M3中的一些可以从单元区域CR延伸到焊盘区域PR。多条最上布线M3中的一些可以从单元区域CR延伸到焊盘区域PR并且可以连接到相应的键合焊盘PAD。多条最上布线M3之中的连接到相应键合焊盘PAD的布线可以被称为连接布线M3-1和M3-2。
多个键合焊盘PAD中的一些可以连接到一条最上布线M3或多条最上布线M3。与多个键合焊盘PAD中的第二焊盘PAD-2连接的最上布线M3的数量可以比连接到第一焊盘PAD-1的最上布线M3的数量更多。连接到第二焊盘PAD-2的两条或更多条邻近的最上布线M3(例如,第二连接布线M3-2)可以彼此电连接以用作一条布线。彼此电连接以用作一条布线的第二连接布线M3-2中的至少一些可以在热凸起BP-Tb下面延伸。
多个键合焊盘PAD中的一些可以不连接到最上布线M3。
图6是用于描述包括在根据示例实施例的半导体芯片中的两组布线的连接关系的概念图。
参照图6,多条最上布线M3可以沿一个方向(图6的水平方向)平行延伸。多条最上布线M3可以具有相同的宽度,即,第一宽度W1,并且可以按相等的距离布置。多条最上布线M3可以按等于第二宽度W2的节距布置。
多条下布线M2可以在多条最上布线M3下面沿一个方向(图6的竖直方向)平行延伸。多条下布线M2中的至少一些可以具有不同的宽度。
多条最上布线M3中的一些均可以通过布线通孔MV电连接到下布线M2中的相应布线,所述布线通孔MV设置在最上布线M3中的相应布线与下布线M2中的相应布线之间。多条最上布线M3之中连接到下布线M2中的相应布线的布线可以被称为连接布线M3-1a和M3-2a。
多条下布线M2中的一些可以连接到最上布线M3中相应的一条或更多条最上布线。与多条下布线M2中的第二下布线M2-2连接的最上布线M3的数量可以比连接到第一下布线M2-1的最上布线M3的数量更多。例如,第一下布线M2-1可以连接到一条第一连接布线M3-1a,第二下布线M2-2可以连接到第二连接布线M3-2a。第二连接布线M3-2a可以由两条或更多条的最上布线M3构成。即,最上布线M3中的连接到第二下布线M2-2的两条或更多条邻近的布线(例如,第二连接布线M3-2a)可以彼此电连接,以用作一条布线。第二连接布线M3-2a中的彼此电连接以用作一条布线的至少一些布线可以在热凸起(图3至图5的BP-T、BP-Ta和BP-Tb)的下面延伸。
多条下布线M2中的一些可以不连接到最上布线M3。
参照图2、图4、图5和图6,多条最上布线M3中的一些布线可以电连接到一个键合焊盘PAD或者两个或更多个键合焊盘PAD,或者可以电连接到下布线M2中的一条布线或者下布线M2中的两条或更多条布线。在一些示例实施例中,多条最上布线M3中的一些可以电连接到键合焊盘PAD中的一个、两个或更多个,或者多条最上布线M3中的其他一些可以电连接到下布线M2中的一条或者下布线M2中的两条或更多条。
多条最上布线M3中一些可以是未电连接到键合焊盘PAD和下布线M2的虚设布线。
在一些示例实施例中,多条下布线M2可以具有相同的宽度,可以按相等的距离布置,可以按具有相同的节距的状态延伸,并且与多条最上布线M3相似,多条下布线M2中的两条或更多条可以彼此电连接以用作一条布线。
参照图2和图6,多条最上布线M3可以沿一个方向(图2至图6的水平方向)平行延伸。多条最上布线M3可以具有相同的宽度,即,第一宽度W1,并且可以按相等的距离布置。多条最上布线M3可以按与第二宽度W2相等的节距布置。
在一些示例实施例中,最上布线M3中的一些邻近的布线可以电连接到一个键合焊盘PAD和/或一条下布线M2以用作一条布线。最上布线M3中的彼此电连接以用作一条布线的一些邻近布线可以在热凸起BP-T、BP-Ta和BP-Tb的下面延伸。在一些示例实施例中,可以改变与一个键合焊盘PAD和/或一条下布线M2电连接的最上布线M3的数量。与一个键合焊盘PAD和/或一条下布线M2电连接的最上布线M3的数量可以是二、三或更多条。多条最上布线M3中的一些可以是与一个键合焊盘PAD和/或一条下布线M2电绝缘的虚设布线。
例如,在多条最上布线M3之中的用于传递电源信号和/或接地信号的第一组最上布线M3中,第一组可以包括数量相对多的最上布线M3,包括在第一组中的最上布线M3可以电连接到一个键合焊盘PAD和/或一条下布线M2以用作一条布线。例如,在多条最上布线M3之中的用于传递控制信号和/或数据信号的第二组最上布线M3中,第二组可以包括数量相对少的最上布线M3,包括在第二组中的最上布线M3可以电连接到一个键合焊盘PAD和/或一条下布线M2以用作一条布线。
即,在根据示例实施例的半导体芯片10、10a或10b中,多条最上布线M3均具有相同的宽度W1,并且多条最上布线被布置为具有第二宽度W2的节距。此外,可以通过不同地改变电连接到一个键合焊盘PAD和/或一条下布线M2的最上布线M3的数量来提供各种信号期望的电特性。
图7是示意性示出根据示例实施例的半导体芯片10-1的构造的剖视图。
参照图7,半导体芯片10-1可以包括焊盘区域PR和器件区域(或者可选择地,单元区域)CR。半导体芯片10-1可以包括半导体基底120、前端制程(front-end-of-line,FEOL)结构130和后端制程(back-end-of-line,BEOL)结构140。
设置在半导体芯片10-1的焊盘区域PR中的TSV结构30可以设置在穿过FEOL 130和半导体基底120的通孔30H中。通孔绝缘层40可以设置在半导体基底120与TSV结构30之间以及FEOL结构130与TSV结构30之间。
TSV结构30可以包括导电塞32和导电阻挡层34,导电塞32穿过半导体基底120和FEOL结构130,导电阻挡层34围绕导电塞32。例如,导电塞32可以包括Cu或钨(W)。例如,导电塞32可以包括Cu、CuSn、CuMg、CuNi、CuZn、CuPd、CuAu、CuRe、CuW、W或W合金,但不限于此。例如,导电塞32可以包括铝(Al)、金(Au)、铍(Be)、铋(Bi)、钴(Co)、Cu、铪(HF)、铟(IN)、锰(Mn)、钼(Mo)、Ni、铅(Pb)、钯(Pd)、铂(Pt)、铑(Rh)、铼(Re)、钌(Ru)、钽(Ta)、碲(Te)、钛(Ti)、W、锌(Zn)和锆(Zr)中的一种或更多种,并且可以包括一层或更多层的堆叠结构。导电阻挡层34可以包括从W、WN、WC、Ti、TiN、Ta、TaN、Ru、Co、Mn、WN、Ni和NiB之中选择的至少一种材料,并且可以由单层或多层形成。然而,TSV结构30的材料不限于此。导电塞32和导电阻挡层34可以通过物理气相沉积(PVD)工艺或化学气相沉积(CVD)工艺形成,但不限于此。
通孔绝缘层40可以包括氧化物、氮化物、碳化物、聚合物或其组合。在示例实施例中,CVD工艺可以用于形成通孔绝缘层40。通孔绝缘层40可以由基于通过亚大气CVD工艺形成的臭氧/四乙基原硅酸酯(O3/TEOS)的高深宽比工艺(HARP)氧化物形成。
半导体基底120可以是半导体晶圆。例如,半导体基底120可以包括硅(Si)。例如,半导体基底120可以包括诸如锗(Ge)等的半导体元素,或者诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)和/或磷化铟(InP)等的化合物半导体。例如,半导体基底120可以具有绝缘体上硅(SOI)结构。例如,半导体基底120可以包括掩埋氧化物层(BOX)。半导体基底120可以包括导电区域,例如,掺杂有杂质的阱或者杂质掺杂的结构。另外,半导体基底120可以具有各种隔离结构,诸如浅沟槽隔离(STI)结构。
FEOL结构130可以包括多个各种单体器件132和层间绝缘层134。单体器件132可以设置在器件区域CR中。
多个单体器件132可以包括各种微电子器件,例如,诸如金属-氧化物-半导体场效应(MOSFET)、系统大规模集成(LSI)和CMOS图像传感器(CIS)的图像传感器、微电子机械系统(MEMS)、有源器件和无源器件。多个单体器件132可以电连接到半导体基底120的导电区域。另外,多个单体器件132中的每个可以通过层间绝缘层134来与邻近的其他单体器件电隔离,并且可以通过导线和接触塞来电连接到其他单体器件。在一些示例实施例中,多个单体器件132可以构成动态随机存取存储器(DRAM)单元。
BEOL结构140可以包括具有多个金属布线层142和多个通孔塞144的多层布线结构146。多层布线结构146的一部分可以连接到TSV结构30。多个金属布线层142可以包括第一布线M1、第二布线M2和第三布线M3。当多个金属布线层142包括分别具有第一布线M1至第三布线M3的三个布线层时,构成最上布线层的第三布线M3可以被称为最上布线M3,构成恰好在最上布线M3下面的布线层的第二布线M2可以被称为下布线M2。
图6中示出的布线通孔MV可以与将第二布线M2连接到第三布线M3的通孔塞144对应。
多层布线结构146的一部分可以连接到多个单体器件132以构成半导体装置。连接包括在FEOL结构130中的多个单体器件132并包括第一布线M1至第三布线M3的多层布线结构146可以设置在BEOL结构140的器件区域CR中。多条第三布线M3可以沿一个方向平行延伸。多条第三布线M3可以具有相同的宽度并且可以按相等的距离布置。多条第三布线M3可以按相同的节距布置。
包括在BEOL结构140中的多个多层布线结构146可以通过布线间绝缘层148来彼此绝缘。BEOL结构140还可以包括用于保护多层布线结构146及其下面的其他结构免受外部冲击或湿气的影响的密封圈(未示出)。
在本公开中,位于布线间绝缘层148的顶部下面的元件均可以被称为半导体器件层(100-1、图8的100-2和图9的100-3)。键合焊盘PAD和第三布线M3可以设置在半导体器件层100-1上。在一些示例实施例中,键合焊盘PAD可以是第三布线M3的一部分。
被半导体基底120和FEOL结构130暴露的TSV结构30的顶部30T可以连接到BEOL结构140中包括的多层布线结构146的金属布线层142。在一些示例实施例中,TSV结构30的顶部30T可以连接到第一布线M1。
键合焊盘PAD的至少一部分和覆盖第三布线M3的钝化层150可以设置在布线间绝缘层148上。钝化层150可以由无机绝缘材料形成。在一些示例实施例中,钝化层150可以由氮化物形成。暴露键合焊盘PAD的顶部的至少一部分的孔150H可以形成在钝化层150中。键合焊盘PAD可以通过孔150H来连接到信号凸起BP-S。
在器件区域CR中,钝化层150可以覆盖第三布线M3的所有顶部和侧面。在器件区域CR中,钝化层150的顶部可以具有像波浪的表面形状一样地不断重复的凹凸形状。
设置在钝化层150上并覆盖第三布线M3的热凸起BP-T可以设置在器件区域CR中。多个热凸起BP-T可以通过钝化层150来与第三布线M3电绝缘。
信号凸起BP-S和热凸起BP-T均可以包括柱层162和设置在柱层162上的焊料层164。
TSV结构30的底部30B可以被种子层64覆盖。连接端子70可以通过种子层64来连接到TSV结构30。连接端子70的顶表面70T和侧壁70S的至少一部分可以被金属覆盖层80覆盖。
连接端子70不限于图7中示出的形状。在其他示例实施例中,连接端子70可以具有导电焊盘、焊料球、焊料凸起或重分配布线导电层的形式。
可以在形成TSV结构30之后执行形成BEOL结构140的工艺、形成种子层64的工艺和形成连接端子70的工艺。
图8是示意性示出根据示例实施例的半导体芯片10-2的构造的剖视图。在参照图8提供的描述中,可以省略与上面参照图7描述的细节相似或相同的细节,并且同样的附图标记表示同样的元件。
参照图8,半导体芯片10-2可以包括焊盘区域PR和器件区域CR。在半导体芯片10-2中,可以形成FEOL结构130和BEOL结构140,然后可以形成TSV结构30。因此,TSV结构30可以形成为穿过半导体基底120、FEOL结构130的层间绝缘层134和BEOL结构140的布线间绝缘层148。TSV结构30的导电阻挡层34可以包括被半导体基底120围绕的第一外壁部分、被层间绝缘层134围绕的第二外壁部分和被布线间绝缘层148围绕的第三外壁部分。
为了将TSV结构30电连接到信号凸起BP-S,键合焊盘PAD可以设置在TSV结构30与BEOL结构140上的信号凸起BP-S之间。
TSV结构30的底部30B可以被种子层64覆盖。连接端子70可以通过种子层64来连接到TSV结构30。连接端子70的顶部70T和侧壁70S中每个的一部分可以被金属覆盖层80覆盖。
图9是示意性示出根据示例实施例的半导体芯片10-3的构造的剖视图。在参照图9提供的描述中,可以省略与上面参照图7和图8描述的细节相似或相同的细节,并且同样的附图标记表示同样的元件。
参照图9,半导体芯片10-3可以包括焊盘区域PR和器件区域CR。在半导体芯片10-3中,TSV结构30可以穿过半导体基底120延伸。可以形成TSV结构30,然后可以在TSV结构30和半导体基底120上形成FEOL结构130和BEOL结构140。TSV结构30可以通过包括在FEOL结构130中的导线136和接触塞138来连接到BEOL结构140的多层布线结构146。
TSV结构30的底部30B可以被种子层64覆盖。连接端子70可以通过种子层64来连接到TSV结构30。连接端子70的顶部70T和侧壁70S中每个的一部分可以被金属覆盖层80覆盖。
在图7至图9中示出的半导体芯片10-1、10-2和10-3中,TSV结构30和信号凸起BP-S示出为在竖直方向上布置,但不限于此。在其他示例实施例中,信号凸起BP-S可以设置为在水平方向上移动。
图10至图15是示出根据示例实施例的制造半导体芯片的方法的剖视图。
参照图10,可以制备半导体器件层100。例如,可以像图7至图9中示出的半导体芯片10-1、10-2和10-3的半导体器件100-1、100-2和100-3那样形成半导体器件层100。
可以在半导体器件层100上的焊盘区域PR和单元区域CR中分别形成键合焊盘PAD和最上布线M3。键合焊盘PAD和最上布线M3可以一起形成并可以构成同一层。在其他示例实施例中,键合焊盘PAD和最上布线M3可以形成为具有几百nm至几μm的厚度。键合焊盘PAD和最上布线M3均可由金属形成。例如,键合焊盘PAD和最上布线M3均可以由Al、Cu、Ta、Ti或W中的一种或更多种形成。
如图1中所示,可以布置几百至几千个键合焊盘PAD以在焊盘区域PR中形成矩阵。可以按列方向上的几十μm的一定节距和在行方向上的几十μm的一定节距来布置键合焊盘PAD以形成矩阵。例如,可以按列方向或行方向上的40μm至50μm的节距布置键合焊盘PAD以形成矩阵。例如,键合焊盘PAD可以具有边长为20μm至40μm的四边形状。
多条最上布线M3可以在单元区域CR中沿一个方向平行延伸。多条最上布线M3可以具有相同的宽度,即,第一宽度W1,并且可以按相等的距离布置。可以按等于第二宽度W2的节距布置多条最上布线M3。
例如,可以形成布线材料层,然后可以通过照相工艺和蚀刻工艺来使布线材料层图案化,从而形成键合焊盘PAD和最上布线M3。
参照图11,可以形成覆盖键合焊盘PAD和最上布线M3的初始钝化层150a。初始钝化层150a可以由无机绝缘材料形成。在一些示例实施例中,初始钝化层150a可以由氮化硅形成。
初始钝化层150a可以具有几百nm至几μm的厚度。多条最上布线M3中的每条的形状可以部分地转移到初始钝化层150a的顶部,并且初始钝化层150a的顶部可以具有第一台阶高度R1。在一些示例实施例中,初始钝化层150a的顶部可以具有像波浪形状的表面一样不断重复的凹凸形状,并且第一台阶高度R1可以是初始钝化层150a的顶部的波浪形状的顶部和底部之间的高度。第一台阶高度R1可以具有等于或小于100nm的值。
参照图11和图12,可以通过去除初始钝化层150a的一部分来形成包括暴露键合焊盘PAD的顶部的至少一部分的凸起孔150H的钝化层150。钝化层150可以完全覆盖单元区域CR中的多条最上布线M3中的每条的顶表面和侧表面。
参照图13,可以在钝化层150上形成掩模图案200。
掩模图案200可以在焊盘区域PR中暴露凸起孔150H和钝化层150的与凸起孔150H相邻的部分。即,掩模图案200可以暴露焊盘区域PR中的键合焊盘PAD的顶部的至少一部分。掩模图案200可以暴露单元区域CR中的钝化层150的一部分。
应用于形成掩模图案200的光刻工艺的光的波长可以具有如下值,该值是第一台阶高度R1的四倍或更多倍大,其中,所述第一台阶高度R1是钝化层150在单元区域CR中的顶表面的凹凸形状的台阶高度。
另一方面,可以使钝化层150的顶表面形成为具有台阶高度,该台阶高度具有如下值,该值与应用于形成掩模图案200的光刻工艺的光的波长的四分之一或更小对应。
在一些示例实施例中,可以通过具有435nm(g线)或405nm(h线)的波长的光的曝光来执行形成掩模图案200的光刻工艺,并且第一台阶高度R1可以具有等于或小于100nm的值。
当钝化层150的顶部的第一台阶高度R1具有与应用于形成掩模图案200的光刻工艺的光的波长的四分之一或更小对应的值时,减轻或防止在用于形成掩模图案200的照相曝光中发生漫反射。因此,减轻或防止掩模图案200的形状在单元区域CR中异常地形成。这里,掩模图案200的形状异常是指下列情形:例如,钝化层150的由掩模图案200暴露的宽度或区域形成为具有非计划中的形状,或者在掩模图案200的暴露钝化层150的内壁上形成曲线。
因此,当钝化层150的顶表面的第一台阶高度R1具有与应用于形成掩模图案200的光刻工艺的光的波长的四分之一或更小对应的值时,钝化层150的由掩模图案200暴露的宽度或区域形成为具有计划中的形状,并且未在掩模图案200的暴露钝化层150的内壁上形成曲线。
参照图14,可以在键合焊盘PAD的一部分以及钝化层150的由掩模图案200暴露的部分上顺序地形成柱层162和初始焊料层164a。
例如,柱层162可以由Cu、Ni和/或Au等形成。例如,柱层162可以由从Cu、Ni和Au之中选择的一种金属或其合金形成或者可以具有包括从Cu、Ni和Au之中选择的多种金属的多层结构。可以通过电镀工艺形成柱层162。
在形成柱层162之后,可以在柱层162上形成初始焊料层164a。初始焊料层164a可以包括锡(Sn)和银(Ag)的合金,并且根据情况,可以向初始焊料层164a中添加Cu、钯(Pd)、铋(Bi)和/或锑(Sb)等。可以通过电镀工艺形成初始焊料层164a。
参照图14和图15,可以形成柱层162和初始焊料层164a,然后可以去除掩模图案200。随后,可以通过热处理来使初始焊料层164a回流从而形成如图3所示的包括具有凸出形状的焊料层164的半导体芯片10。
参照图3和图10至图15,在根据示例实施例的制造半导体芯片的方法中,可以在单元区域CR中形成具有相同宽度并以相等距离布置的多个最上布线M3,从而减小覆盖多个最上布线M3的钝化层150的顶部的第一台阶高度R1。因此,减轻或防止在照相曝光中发生漫反射,从而半导体芯片10中包括的信号凸起BP-S和热凸起BP-T的上端可以具有同一水平面。因此,可以减轻或防止在信号凸起BP-S和热凸起BP-T中发生接触缺陷,从而保证半导体芯片10的可靠性并有效地散发从半导体芯片10产生的热量。
图16是示出根据示例实施例的包括半导体芯片的半导体封装件1的剖视图。
参照图16,半导体封装件1可以包括顺序地堆叠在封装基底20上的多个半导体芯片10。多个半导体芯片10可堆叠在竖直方向上。在图16中,半导体封装件1示出为包括五个半导体芯片10,但不限于此。在其他示例实施例中,半导体封装件1可以包括两个至四个半导体芯片10或者六个或更多个半导体芯片10。
多个半导体芯片10中的每个可以包括多个TSV结构30。多个TSV结构30可以设置在焊盘区域PR中。多个半导体芯片10可以通过使相应的TSV结构30连接而彼此电连接。多个半导体芯片10可以通过多个TSV结构30来电连接到封装基底20。
例如,封装基底20可以是印刷电路板、陶瓷基底或中介层。当封装基底20为印刷电路板时,封装基底20可以包括:基底基体、设置在基底基体的顶部上的顶焊盘(未示出)以及设置在基底基体的底部上的底焊盘(未示出)。顶焊盘和底焊盘可以被覆盖基底基体的顶部和底部的阻焊层(未示出)所暴露。基底基体可以由苯酚树脂、环氧树脂和聚酰亚胺中的至少一种形成。例如,基底基体可以包括从FR4、四官能环氧树脂(tetrafunctional epoxy)、聚苯醚(polyphenylene ether)、环氧树脂/聚苯醚(epoxy/polyphenylene oxide)、双马来酰亚胺三嗪(BT)、聚酰胺短纤席材(thermount)、氰酸酯(cyanate ester)、聚酰亚胺和液晶聚合物之中选择的至少一种材料。顶焊盘和底焊盘均可以由Cu、Ni、不锈钢和/或铍铜等形成。电连接到顶焊盘和底焊盘的内置布线(未示出)可以设置在基底基体中。顶焊盘和底焊盘可以是电路布线的由阻焊层暴露的部分,其中,所述电路布线通过使涂覆在基底基体的顶部和底部的Cu箔图案化来形成。
当封装基底20为中介层时,封装基底20可以包括由半导体材料形成的基底基体、设置在基底基体的顶部上的顶焊盘(未示出)以及设置在基底基体的底部上的底焊盘(未示出)。例如,基底基体可由硅晶圆形成。另外,内置布线(未示出)可形成在基底基体的顶部、底部或内部上。另外,将顶焊盘电连接到底焊盘的贯穿通路(未示出)可形成在基底基体的内部中。
外部连接端子26可以附于封装基底20的底部。例如,外部连接端子26可以附于底焊盘。例如,外部连接端子26可以是焊球或凸起。外部连接端子26可以使半导体封装件1电连接到外部装置。
围绕多个半导体芯片10中的一些或所有半导体芯片的模塑层300可以形成在封装基底20上。例如,模塑层300可以由环氧树脂模化合物(EMC)形成。
在一些示例实施例中,模塑层300可以暴露多个半导体芯片10之中的最上半导体芯片10的顶部,并且散热构件(未示出)可以附于模塑层300和多个半导体芯片10,所述多个半导体芯片10之间具有热界面材料(TIM)。
TIM可以由绝缘材料形成,或者可以由绝缘材料和用于保持电绝缘性能的材料形成。例如,TIM可以包括环氧树脂。例如,TIM可以是矿物油、油脂、间隙填充胶、相变凝胶、相变材料焊盘和/或颗粒填充环氧树脂等。
例如,散热构件可以是散热片、散热器、导热管或液体冷却板。
连接到TSV结构30的信号凸起BP-S可以在焊盘区域PR中设置在多个半导体芯片10中的每个的底部上。热凸起BP-T可以在单元区域CR中设置在多个半导体芯片10中的每个的底部上。多个半导体芯片10可以由信号凸起BP-S和热凸起BP-T支撑。热凸起BP-T可以与构成包括在半导体芯片10中的半导体装置的多个单体器件电绝缘。
多个半导体芯片10中的每个半导体芯片可以是图1至图15的半导体芯片10、10a、10b、10c、10-1、10-2和10-3或其组合中的至少一个。
在根据示例实施例的半导体封装件1中,信号凸起BP-S和热凸起BP-T的上端可以具有同一水平面,可以减轻或防止半导体芯片10中出现翘曲。因此,可以减轻或防止在信号凸起BP-S和热凸起BP-T中出现接触缺陷,从而保证半导体封装件1的可靠性并有效地散发从半导体芯片10产生的热量。
图17是示出根据示例实施例的包括半导体芯片的半导体封装件2的剖视图。
参照图17,半导体封装件2可以包括附于封装基底20的主半导体芯片500以及顺序地堆叠在主半导体芯片500上的多个半导体芯片10。
图17中示出的半导体封装件2可以按如下形式构造,即,图16中示出的半导体封装件1中还包括主半导体芯片500,因此,不描述与上面参照图16描述的细节相似或相同的细节。
主半导体芯片500可以是处理器单元。例如,主半导体芯片500可以是微处理器单元(MPU)或图形处理器单元(GPU)。在一些示例实施例中,主半导体芯片500可以是已经被验证正常操作的封装件(即,已知良好的封装件(KGP))。主半导体芯片500可以包括主TSV结构530。主TSV结构530可以具有与包括在半导体芯片10中的TSV结构30相似的结构,因此,不提供其详细的描述。
多个半导体芯片10中的每个半导体芯片的TSV结构30可以电连接到主半导体芯片500的与其对应的主TSV结构530。
主连接端子510可以附于主半导体芯片500的底部。多个半导体芯片10和主半导体芯片500可以通过主连接端子510电连接到封装基底20。在一些示例实施例中,还可以在主半导体芯片500与封装基底20之间形成围绕主连接端子510的底部填充材料层520。例如,底部填充材料层520可以由环氧树脂形成。在一些示例实施例中,底部填充材料层520可以是模塑层300的以模塑底部填充(MUF)方法形成的部分。
多个半导体芯片10中的每个半导体芯片可以是图1至图15的半导体芯片10、10a、10b、10c、10-1、10-2和10-3或其组合中的至少一个。
在根据示例实施例的半导体封装件2中,信号凸起BP-S和热凸起BP-T的上端可以具有同一水平面,可以减轻或防止在半导体芯片10中出现翘曲。因此,可以减轻或防止在信号凸起BP-S和热凸起BP-T中出现接触缺陷,从而保证半导体封装件2的可靠性并有效地散发从包括在半导体封装件2中的半导体芯片10产生的热量。
图18是示出根据示例实施例的包括半导体芯片的半导体封装件3的剖视图。
参照图18,半导体封装件3可以包括附于封装基底20的主半导体芯片500a以及顺序地堆叠在封装基底20上的多个半导体芯片10。
除了主半导体芯片500a和顺序地堆叠的多个半导体芯片10附于封装基底20的不同部分之外,图18中示出的半导体封装件3可以与图17中示出的半导体封装件2相似,因此,不提供其详细的描述。
在根据示例实施例的半导体封装件3中,信号凸起BP-S和热凸起BP-T的上端可以具有同一水平面,可以减轻或防止半导体芯片10中出现翘曲。因此,可以减轻或防止在信号凸起BP-S和热凸起BP-T中出现接触缺陷,从而保证半导体封装件3的可靠性并且有效地散发从包括在半导体封装件3中的半导体芯片10产生的热量。
图19是示出根据示例实施例的半导体模块1000的主体的构造的平面图。
参照图19,半导体模块1000可以包括模块基底1010、控制芯片1020和多个半导体封装件1030。控制芯片1020和多个半导体封装件1030可以安装在模块基底1010上。多个输入/输出(I/O)端子1050可以设置在模块基底1010上。
多个半导体封装件1030中的每个可以包括图1至图15的半导体芯片10、10a、10b、10c、10-1、10-2和10-3或其组合中的至少一个。
图20是示意性示出根据示例实施例的半导体封装件1100的构造的示图。
参照图20,半导体封装件1100可以包括MPU 1100、存储器1120、接口1130、GPU1140、多个功能块1150和使元件连接的总线1160。半导体封装件1100可以包括MPU 1110和GPU 1140两者,或者可以仅包括MPU 1110和GPU 1140中的一者。
MPU 1110可以包括核和L2高速缓存。例如,MPU 1110可以包括多个核。所述多个核中的各核可以具有相同的性能或不同的性能。另外,所述多个核中的各核可以在相同时间或不同时间被激活。存储器1120可以根据MPU 1110的控制而存储由每个功能块1150所执行的处理的结果。例如,当存储在MPU 1110的L2高速缓存中的细节被刷新时,处理结果可以存储在存储器1120中。接口1130可以执行与外部装置的交互。例如,接口1130可以执行与相机、液晶显示器(LCD)和/或扬声器等的交互。
GPU 1140可以执行图形功能。例如,GPU 1140可以执行视频编解码器或者可以处理三维(3D)图形。
功能块1150可以执行各种功能。例如,当半导体封装件1100是应用于移动装置的AP时,功能块1150中的一些可以执行通信功能。
多个半导体封装件1100中的每个半导体封装件可以包括图1至图15的半导体芯片10、10a、10b、10c、10-1、10-2和10-3或其组合中的至少一个或者可以是图16至图18的半导体封装件1、2和3中的一种。
图21是示出根据示例实施例的包括半导体封装件的电子系统1200的示图。
参照图21,电子系统1200可以配备有MPU/GPU 1210。例如,电子系统1200可以是移动装置、台式计算机或服务器等。另外,电子系统1200还可以包括存储装置1220、输入/输出(I/O)装置1230和显示装置1240,并且元件可以电连接到总线1250。MPU/GPU 1210和存储装置1220可以包括图1至图15的半导体芯片10、10a、10b、10c、10-1、10-2和10-3或其组合中的至少一个,或者可以是图16至图18的半导体封装件1、2和3中的一种。
在根据描述的示例实施例的半导体芯片、包括半导体芯片的半导体封装件及制造半导体芯片的方法中,多条最上布线可以具有相同的宽度并且可以按相等的距离布置,钝化层的顶部可以具有像波浪形状的表面一样地不断重复的凹凸形状,从而减轻或防止在形成凸起(包括信号凸起和热凸起)的光刻工艺中发生漫反射。因此,可以减轻或防止形成凸起的形状。
此外,根据描述的示例实施例,半导体芯片可以避免另行使用保护层来抵消钝化层的顶部的台阶高度。因此,可以减轻或防止在半导体芯片中发生翘曲。此外,信号凸起的上端和热凸起的上端可以具有同一水平面,从而减轻或防止在信号凸起和热凸起中出现接触缺陷。因此,半导体芯片和包括该半导体芯片的半导体封装件的可靠性得到保证,并且从半导体芯片产生的热量得以有效地散发。
尽管已经参照本发明构思的一些示例实施例来具体示出并描述了本发明构思,但将理解的是,在不脱离权利要求的精神和范围的情况下,在这里可以做出形式上和细节上的各种改变。
Claims (25)
1.一种半导体芯片,所述半导体芯片包括:
半导体器件层,包括焊盘区域和单元区域,半导体器件层包括位于焊盘区域中的多个硅通孔结构;
多条最上布线,位于半导体器件层上,所述多条最上布线在单元区域中以相等的距离布置,所述多条最上布线具有相同的宽度并且沿一个方向平行延伸;
钝化层,位于单元区域和焊盘区域中,钝化层至少覆盖单元区域中的所述多条最上布线的顶表面,钝化层的位于单元区域中的顶表面具有波浪形状;以及
多个热凸起,位于钝化层上,所述多个热凸起与所述多条最上布线电绝缘。
2.根据权利要求1所述的半导体芯片,所述半导体芯片还包括:
多个焊盘,位于半导体器件层上,所述多个焊盘连接到位于焊盘区域中的所述多个硅通孔结构;以及
多个信号凸起,位于所述多个焊盘上,所述多个信号凸起电连接到所述多个焊盘。
3.根据权利要求2所述的半导体芯片,其中,
钝化层还覆盖位于焊盘区域中的所述多条最上布线的顶表面,并且包括暴露所述多个焊盘中的每个焊盘的顶表面的一部分的凸起孔,以及
所述多个信号凸起中的每个信号凸起通过凸起孔连接到所述多个焊盘中的相应的一个焊盘。
4.根据权利要求2所述的半导体芯片,其中,所述多个信号凸起中的每个信号凸起的上端和所述多个热凸起中的每个热凸起的上端具有同一水平面。
5.根据权利要求2所述的半导体芯片,其中,所述多个信号凸起和所述多个热凸起具有相同的水平宽度。
6.根据权利要求2所述的半导体芯片,其中,
所述多个信号凸起以第一节距布置,以及
所述多个热凸起以比第一节距大的第二节距布置。
7.根据权利要求1所述的半导体芯片,其中,所述多条最上布线中的至少两条邻近的最上布线彼此电连接以用作一条布线。
8.根据权利要求7所述的半导体芯片,其中,所述至少两条邻近的最上布线中的每条最上布线的至少一部分在所述多个热凸起中的至少一个热凸起的下面延伸。
9.根据权利要求1所述的半导体芯片,其中,钝化层的位于单元区域中的所述顶表面的台阶高度为100nm或更小。
10.根据权利要求9所述的半导体芯片,其中,位于单元区域中的所述多条最上布线中的每条最上布线的宽度为200nm至500nm。
11.根据权利要求1所述的半导体芯片,其中,所述多个热凸起中的每个热凸起的底表面具有与钝化层的所述顶表面对应的波浪形状。
12.一种制造半导体芯片的方法,所述方法包括:
制备包括焊盘区域和单元区域的半导体器件层,半导体器件层包括位于焊盘区域中的多个硅通孔结构;
在半导体器件层上形成多条最上布线,使得所述多条最上布线在单元区域中以相等的距离布置,所述多条最上布线沿一个方向平行延伸并且具有相同的宽度;
在焊盘区域中形成多个焊盘,使得所述多个焊盘连接到位于焊盘区域中的所述多个硅通孔结构;
形成钝化层以覆盖所述多个焊盘中的每个焊盘的顶表面的至少一部分和位于单元区域中的所述多条最上布线,钝化层包括具有台阶高度的顶表面;
在钝化层上形成掩模图案,使得掩模图案暴露所述多个焊盘中的每个焊盘的顶表面的所述至少一部分和钝化层的一部分;以及
在由掩模图案暴露的所述多个焊盘中的每个焊盘的顶表面的所述至少一部分和钝化层的所述部分上形成柱层和初始焊料层。
13.根据权利要求12所述的方法,所述方法还包括:
去除掩模图案;以及
使初始焊料层回流以形成焊料层,
其中,焊料层提供位于焊盘区域中的信号凸起和位于单元区域中的热凸起。
14.根据权利要求13所述的方法,其中,信号凸起的上端和热凸起的上端具有同一水平面。
15.根据权利要求14所述的方法,其中,热凸起通过钝化层来与所述多条最上布线电绝缘。
16.根据权利要求13所述的方法,其中,形成掩模图案的步骤包括使钝化层和所述多个焊盘中的每个焊盘的顶表面的所述至少一部分曝光,所述曝光用光的波长是钝化层的所述顶表面的台阶高度的至少四倍。
17.根据权利要求16所述的方法,其中,钝化层的位于单元区域中的所述顶表面的台阶高度为100nm或更小。
18.根据权利要求17所述的方法,其中,形成多条最上布线的步骤将所述多条最上布线中的每条最上布线形成为具有比钝化层的所述顶表面的台阶高度大的厚度。
19.一种半导体芯片,所述半导体芯片包括焊盘区域和单元区域,所述半导体芯片包括:
多个硅通孔结构,位于焊盘区域中;
多条最上布线,位于单元区域中,所述多条最上布线形成半导体芯片的电路构造的一部分,所述多条最上布线中的邻近的最上布线分隔开相同的距离,所述多条最上布线中的每条最上布线具有相同的宽度,所述多条最上布线沿一个方向平行延伸;
钝化层,位于单元区域和焊盘区域中,钝化层至少覆盖位于单元区域中的所述多条最上布线的顶表面,钝化层的位于单元区域中的顶表面具有波浪形状;以及
多个热凸起,位于钝化层上,所述多个热凸起与所述多条最上布线电绝缘。
20.根据权利要求19所述的半导体芯片,其中,所述多条最上布线不包括被设置为使多个焊盘中的至少一些焊盘在其他位置可用的重分配布线。
21.根据权利要求19所述的半导体芯片,所述半导体芯片还包括:
多个焊盘,位于焊盘区域中的半导体器件层上,所述多个焊盘连接到焊盘区域中的所述多个硅通孔结构;以及
多个信号凸起,位于所述多个焊盘上,所述多个信号凸起电连接到所述多个焊盘。
22.根据权利要求21所述的半导体芯片,其中,所述多个信号凸起中的每个信号凸起的上端和所述多个热凸起中的每个热凸起的上端具有同一水平面。
23.根据权利要求21所述的半导体芯片,其中,
钝化层还覆盖位于焊盘区域中的所述多条最上布线的顶表面,并且包括暴露多个焊盘中的每个焊盘的顶表面的一部分的凸起孔,以及
所述多个信号凸起中的每个信号凸起通过凸起孔连接到所述多个焊盘中的相应的一个焊盘。
24.根据权利要求19所述的半导体芯片,其中,所述多条最上布线中的至少两条邻近的最上布线彼此电连接以用作一条布线。
25.根据权利要求24所述的半导体芯片,其中,所述至少两条邻近的最上布线中的每条最上布线的至少一部分在所述多个热凸起中的至少一个热凸起的下面延伸。
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