CN106558533A - 导电插塞结构的形成方法 - Google Patents
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Abstract
一种导电插塞结构的形成方法,包括:提供基底;在所述基底上形成具有开口的掩膜层;以所述掩膜层为掩膜刻蚀所述基底,在所述基底中形成接触孔;刻蚀所述掩膜层,使所述开口的线宽尺寸增大;在刻蚀后的所述掩膜层表面、所述接触孔内壁和所述开口内壁形成绝缘层,且所述绝缘层的厚度大于等于刻蚀后的所述掩膜层的厚度;在所述绝缘层表面形成填充满所述接触孔的导电层;平坦化所述导电层和绝缘层直至暴露出所述掩膜层的表面。所述方法提高了导电插塞结构的性能。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种导电插塞结构的形成方法。
背景技术
随着半导体技术的不断发展,半导体器件的特征尺寸越来越小,在二维的封装结构中增加半导体器件的数量变得越来越困难,而三维封装成为一种能够有效提高半导体器件集成度的方法。目前的三维封装包括:基于金线键合的芯片堆叠(die Stacking)、分装堆叠(Package Stacking)和基于硅通孔(Through Silicon Via,TSV)的三维堆叠。其中,利用硅通孔的三维堆叠技术具有以下优点:高密度集成;电互连长度大幅度缩短,有效解决出现在二维系统极半导体器件中信号延迟等问题;利用硅通孔技术,能够把具有不同功能的模块,如射频模块、内存模块、逻辑模块和微机电系统模块集成在一起实现封装。因此,利用硅通孔结构的三维堆叠技术日益成为一种重要的半导体器件封装技术。
基于硅通孔结构技术的导电插塞结构的形成方法为:提供基底;刻蚀所述基底在基底中形成接触孔;在接触孔内壁和基底表面形成绝缘层,所述绝缘层用于电学隔离后续填充的导电层;采用物理气相沉积工艺或电镀工艺在所述绝缘层表面形成填充满所述接触孔的导电层;采用化学机械研磨去除位于基底表面的导电层,形成导电插塞结构。
然而,现有技术中形成的导电插塞结构的性能较差。
发明内容
本发明解决的问题是提供一种导电插塞结构的形成方法,避免接触孔顶部与绝缘层之间形成缺口,提高导电插塞结构的性能。
为解决上述问题,本发明提供一种导电插塞结构的形成方法,包括:提供基底;在所述基底上形成具有开口的掩膜层;以所述掩膜层为掩膜刻蚀所述基底,在所述基底中形成接触孔;刻蚀所述掩膜层,使所述开口的线宽尺寸增大;在刻蚀后的所述掩膜层表面、所述接触孔内壁和所述开口内壁形成绝缘层,且所述绝缘层的厚度大于等于刻蚀后的所述掩膜层的厚度;在所述绝缘层表面形成填充满所述接触孔的导电层;平坦化所述导电层和绝缘层直至暴露出所述掩膜层的表面。
可选的,刻蚀所述掩膜层后的开口的线宽尺寸与所述接触孔的线宽尺寸比为1.02~1.1。
可选的,所述掩膜层的材料为氮化硅或氮氧化硅。
可选的,刻蚀所述掩膜层的工艺为湿刻工艺,采用的刻蚀溶液为磷酸溶液,磷酸的质量百分比浓度为80%~90%,刻蚀温度为120摄氏度~180摄氏度。
可选的,刻蚀后的所述掩膜层的厚度为800埃~1200埃。
可选的,所述导电层的材料为钽、氮化钽或铜。
可选的,形成所述导电层的工艺为电镀工艺。
可选的,平坦化所述导电层和绝缘层的工艺为化学机械研磨工艺。
可选的,所述绝缘层的材料为氧化硅。
可选的,形成所述绝缘层的工艺为原子层沉积工艺。
可选的,还包括:在形成所述导电层之前,在所述绝缘层表面形成阻挡层;平坦化所述导电层和绝缘层的同时平坦化所述阻挡层直至暴露出所述掩膜层的表面。
与现有技术相比,本发明的技术方案具有以下优点:
(1)由于对所述掩膜层进行刻蚀,增大了所述开口的线宽尺寸,使得所述开口的线宽尺寸大于所述接触孔的线宽尺寸,从而使得所述开口暴露出所述接触孔外周的基底上表面,当形成所述绝缘层后,所述绝缘层不仅覆盖所述接触孔的内壁和刻蚀后的所述掩膜层的表面,也覆盖被暴露出的所述接触孔外周的基底上表面,使得位于刻蚀后的所述掩膜层的表面的绝缘层表面高于覆盖所述接触孔外周基底上表面的绝缘层表面,使得在绝缘层中增加了边角的数量,使得在开始形成所述导电层时,电镀溶液中的抑制剂分散分布于多个边角位置,避免了在所述接触孔顶部的边角位置分布的抑制剂过多,减弱了对所述接触孔侧壁顶部导电层的纵向生长的抑制作用,使得在导电层中形成的凹陷向所述开口的侧壁推移,同时,由于所述绝缘层的厚度大于等于刻蚀后的所述掩膜层的厚度,使得当平坦化所述导电层和绝缘层后,所述凹陷随形下落产生的缺陷均被研磨去除,避免了导电层与绝缘层之间形成缺口,后续在导电层表面形成金属层时,一方面,能够避免导电层和金属层接触不良,提高导电插塞结构的导电性,另一方面,避免导电层中的原子扩散,从而避免导电层出现电迁移和应力迁移,提高导电插塞结构的可靠性。从而提高了导电插塞结构的性能。
(2)进一步的,刻蚀所述掩膜层后的开口的线宽尺寸与所述接触孔的线宽尺寸比为1.02~1.1,使得在形成导电层的过程中,导电层中凹陷位置离位于接触孔的水平距离较远,使得在平坦化所述导电层和绝缘层的过程中,所述凹陷随形下落产生的缺口离接触孔的水平距离较远,当进行所述平坦化工艺直至暴露出所述掩膜层的表面时,对接触孔顶部的导电层的影响大大减小,导电层表面周边与相邻接触的绝缘层表面更加齐平。同时,所述开口的线宽尺寸不至于太大,使得在平坦化所述导电层和绝缘层的过程中,不会减弱所述掩膜层作为停止层的作用。
(3)进一步的,在形成所述导电层之前,在所述绝缘层表面形成阻挡层;平坦化所述导电层和绝缘层的同时平坦化所述阻挡层直至暴露出所述掩膜层的表面。所述阻挡层能够阻挡导电层中的原子扩散至基底中,且在形成导电层的过程中,提高导电层的附着力。
附图说
图1至图4是现有技术中导电插塞结构形成过程的结构示意图;
图5至图10为本发明第一实施例中导电插塞结构形成过程的结构示意图;
图11至图12为本发明第二实施例中导电插塞结构形成过程的结构示意图。
具体实施方式
正如背景技术所述,现有技术中形成的导电插塞结构的性能较差。
图1至图4是现有技术中导电插塞结构形成过程的结构示意图。
参考图1,提供基底100;在所述基底100表面形成具有开口111的掩膜层110。
所述基底100包括半导体衬底101和位于半导体衬底101表面的层间介质层102。所述层间介质层102中可以形成有晶体管103。
参考图2,以所述掩膜层110为掩膜刻蚀所述基底100,在所述基底100中形成接触孔120。
为了清楚的表示开口111和接触孔120的位置,图2中采用虚线表示开口111和接触孔120的边界。
参考图3,在接触孔120内壁和掩膜层110表面形成绝缘层130;在所述绝缘层130表面形成填充满所述接触孔120(参考图2)的导电层140。
所述导电层140的材料为铜。形成所述导电层140的工艺为电镀工艺,采用的电镀溶液中包含硫酸铜、硫酸和抑制剂等。
参考图4,平坦化导电层140和绝缘层130,直至暴露出掩膜层110的表面。
研究发现,现有技术中形成的导电插塞结构存在性能较差的原因在于:
在开始形成所述导电层时,为了使得接触孔顶部不至于提早封闭而在导电层中形成孔隙,需要在电镀溶液中使用抑制剂,所述抑制剂为高分子量的化合物,所述抑制剂在高电流区域(接触孔的边角处)的吸附能力较强,在铜的表面阻挡铜离子的扩散,进而抑制铜在边角处的生长,包括横向生长和纵向生长,但是,所述抑制剂在抑制铜在横向生长的同时抑制铜的纵向生长,使得在通过所述接触孔边角处的纵向方向上,使得最终形成的导电层中存在凹陷150(参考图3),在平坦化导电层和绝缘层的过程中,同时向下研磨所述凹陷的表面和导电层的顶部表面,使得进行所述平坦化直至暴露出所述掩膜层表面时,导电层外周表面低于导电层的中心区域的表面,从而在导电层的外周形成缺口160(参照图4)。后续在导电层表面形成金属层,一方面导致导电层与金属层接触不良,从而使得导电插塞结构的导电性下降,另一方面,使得导电层中的原子容易扩散,所述导电层容易出现电迁移和应力迁移,导致导电插塞结构的可靠性下降。
在此基础上,本发明一实施例提供一种导电插塞结构的形成方法,通过刻蚀所述掩膜层,增大所述掩膜层中开口的线宽尺寸,使得在形成导电层的过程中,将导电层中产生的凹陷的位置向外围推移,使得平坦化所述导电层后,避免了凹陷随形下落产生的界面缺陷,提高了导电插塞结构的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
第一实施例
图5至图10为本发明第一实施例中导电插塞结构形成过程的结构示意图。
参考图5,提供基底200;在基底200上形成具有开口211的掩膜层210。
所述基底200包括半导体衬底201和位于半导体衬底201表面的层间介质层202。
所述半导体衬底201可以是单晶硅,多晶硅或非晶硅;半导体衬底201也可以是硅、锗、锗化硅、砷化镓等半导体材料;本实施例中,所述半导体衬底201的材料为硅。
所述层间介质层202中可以形成有晶体管203,所述晶体管203可通过插塞与后续在层间介质层202上形成的其它器件连接。本实施例中,所述层间介质层202的材料为氧化硅或碳氧化硅。
所述掩膜层的210的材料为氮化硅或氮氧化硅。
所述掩膜层210的作用为:在后续平坦化导电层和绝缘层的过程中,作为停止层;所述掩膜层210为硬质的掩膜层,在后续形成接触孔的过程中,减小对基底200顶部的横向刻蚀。
由于后续需要对掩膜层210进行刻蚀,在刻蚀掩膜层210的过程中会减薄掩膜层210的厚度,故需要将掩膜层210的厚度设置为大于预定的厚度,本实施例中,所述掩膜层210的厚度为4000埃~6000埃。
参考图6,以所述掩膜层210为掩膜,刻蚀所述基底200,在基底200中形成接触孔220。
为了清楚的表示开口211和接触孔220的位置,图6中采用虚线表示开口211和接触孔220的边界。
可以采用深反应性离子刻蚀工艺在半导体衬底中形成接触孔220。所述深反应性离子刻蚀可以是Bosch深反应性离子刻蚀(Bosch Deep Reactive IonEtching,Bosch DRIE)工艺,或者是低温型深反应性离子刻蚀(Cryogenic DeepReactive Ion Etching,DRIE)工艺。
本实施例中,采用Bosch深反应性离子刻蚀工艺形成所述接触孔220,具体的步骤为:以所述掩膜层210为掩膜,交替地引入刻蚀性气体和保护性气体,交替地对基底200进行刻蚀和对刻蚀后形成的侧壁进行保护,直至形成预定尺寸的接触孔220。
本实施例中,所述接触孔220的底部位于半导体衬底201中;在其它的实施例中,所述接触孔220的底部可以和层间介质层202的下表面齐平。
参考图7,刻蚀所述掩膜层210,使所述开口211的线宽尺寸增大,以暴露出所述接触孔220外周的基底200上表面。
所述开口211的线宽尺寸指的是平行于基底200表面的线宽尺寸。
本实施例中,刻蚀所述掩膜层210的工艺为湿刻工艺。
由于所述湿刻工艺对所述掩膜层210的刻蚀为各向同性的刻蚀,所以在刻蚀掩膜层210的过程中,在增大所述开口211的线宽尺寸的同时,也会减薄所述掩膜层210的厚度,本实施例中,刻蚀后的掩膜层210的厚度为800埃~1200埃。
在一个具体的实施例中,所述湿刻工艺采用的刻蚀溶液为磷酸溶液。
若磷酸溶液的质量百分比浓度过低,若所述磷酸的浓度过高,使得对所述掩膜层210的刻蚀的速率过高,不能准确的控制刻蚀后的掩膜层210的厚度和开口211的线宽尺寸,使得刻蚀后的掩膜层210的厚度和开口211的线宽尺寸波动较大,若磷酸的浓度过低,使得对所述掩膜层210的刻蚀的速率过低,会降低工艺效率,故本实施例中,所述磷酸的质量百分比浓度为80%~90%,优选的,所述磷酸的质量百分比浓度为85%。
若刻蚀温度过高,使得对所述掩膜层210的刻蚀的速率过高,不能准确的控制刻蚀后的掩膜层210的厚度和开口211的线宽尺寸,使得刻蚀后的掩膜层210的厚度和开口211的线宽尺寸波动较大,若刻蚀温度过低,使得对所述掩膜层210的刻蚀的速率过低,会降低工艺效率,故本实施例中,刻蚀温度选择为120摄氏度~180摄氏度,优选的,所述刻蚀温度为160摄氏度。
需要说明的是,在其它实施例中,可以采用干刻工艺刻蚀所述掩膜层210,需要在所述掩膜层210表面形成图形化的光刻胶,所述图形化的光刻胶定义待形成的线宽尺寸增大的开口211的位置,然后以所述图形化的光刻胶为掩膜,刻蚀所述掩膜层210,使所述开口211的线宽尺寸增大。
刻蚀所述掩膜层210后,增大了所述开口211的线宽尺寸,若所述开口211的线宽尺寸过大,会使得在后续平坦化导电层和绝缘层的过程中,减弱所述掩膜层210作为停止层的作用,若所述开口211的线宽尺寸过小,使得后续在形成导电层的过程中,导电层中产生的凹陷位置离接触孔220的水平距离较近,使得后续在平坦化所述导电层和绝缘层的过程中,所述凹陷随形下落产生的缺口离接触孔220的水平距离较近,后续当进行所述平坦化工艺直至暴露出所述掩膜层的表面时,所述缺口不能完全消除,故本实施例中,刻蚀所述掩膜层210后,使得所述开口211的线宽尺寸与所述接触孔220的线宽尺寸比为1.02~1.1。
参考图8,在所述接触孔220内壁、刻蚀后的所述掩膜层210表面和所述开口211的内壁形成绝缘层230,且所述绝缘层230的厚度大于等于刻蚀后的所述掩膜层210的厚度。
本实施例中,所述绝缘层230的厚度等于刻蚀后的掩膜层210的厚度。由于在实际工艺中,难以精准的控制绝缘层230的厚度等于刻蚀后的掩膜层210的厚度,故在其它实施例中,所述绝缘层230的厚度大于刻蚀后的掩膜层210的厚度,简化了工艺实现的难度。
所述绝缘层230的作用为:电学隔离后续形成的导电层和基底200;覆盖在刻蚀后的所述掩膜层210表面、所述接触孔220内壁和所述开口211的内壁,使得刻蚀后的所述掩膜层210的表面的绝缘层230表面高于覆盖所述接触孔220外周基底200上表面的绝缘层230表面。
所述绝缘层230的材料为氧化物,本实施例中,所述绝缘层230的材料为氧化硅。
本实施例中,形成绝缘层230的方法可以为常压化学气相沉积(Atmospheric Pressure Chemical Vapor Deposition,APCVD)工艺、等离子体辅助化学气相沉积(Plasma Enhance Chemical Vapor Deposition,PECVD)工艺、低压化学气相沉积(Low Pressure Chemical Vapor Deposition,LPCVD)工艺或原子层沉积工艺。本实施例中,形成所述绝缘层230的工艺为原子层沉积工艺。
由于刻蚀后的所述掩膜层210的表面的绝缘层230表面高于覆盖所述接触孔220外周基底200上表面的绝缘层230表面,使得在绝缘层230中增加了边角的数量,即绝缘层230不仅在接触孔220顶部的位置具有边角,而且刻蚀后的所述掩膜层210表面的绝缘层230与位于暴露出的基底200上表面的绝缘层230之间形成边角。
本实施例中,所述绝缘层230的厚度大于等于刻蚀后的掩膜层210的厚度,具体的,所述绝缘层230的厚度为2000埃~5000埃。
参考图9,在所述绝缘层230表面形成填充满所述接触孔220的导电层240。
所述导电层240的材料为钽、氮化钽或铜。本实施例中,所述导电层240的材料为铜。
本实施例中,采用电镀工艺形成所述导电层240,具体的,首先在绝缘层230表面形成铜籽晶层(未图示),然后将所述基底200转移至电镀反应池中,所述电镀反应池中包括有电镀溶液、金属铜阳极和电源正负极。所述电镀溶液主要由硫酸铜、硫酸和水组成,所述电镀溶液中还包含有催化剂、抑制剂、调整剂等多种添加剂。所述抑制剂为聚乙二醇、聚丙烯二醇和聚乙二醇中的一种或几种。
本实施例中,所述电镀工艺的过程为:所述籽晶层连接电源的负极,所述金属铜阳极连接电源的正极,位于所述金属铜阳极上的铜原子发生氧化反应形成金属铜离子,位于所述籽晶层表面附近的金属铜离子发生还原反应,生成的铜原子沉积在所述籽晶层表面,形成导电层240。
由于在开始形成所述导电层240时,为了使得所述接触孔220顶部不会提早封闭而在导电层240中形成孔隙,需要在电镀溶液中使用抑制剂,所述抑制剂为高分子量的化合物,所述抑制剂在高电流区域的吸附能力较强,由于绝缘层230中形成的边角处为高电流区域,所以所述抑制剂会吸附在所述边角处,进而抑制导电层240在边角处的生长。但是,在所述边角处,所述抑制剂抑制导电层240在横向生长的同时也会抑制导电层240的纵向生长,使得最终形成的导电层240中存在凹陷250。
尽管在导电层240中存在凹陷250,但是所述凹陷250具有以下特点:所述凹陷250的最低端距离所述接触孔220的水平距离较远。具体的原因为:由于在绝缘层230中边角的位置并不只有接触孔220侧壁的顶部,且刻蚀后的所述掩膜层210表面的绝缘层230与位于暴露出的基底200上表面的绝缘层230之间也形成边角,使得在开始形成所述导电层240时,电镀溶液中的抑制剂分散分布于多个边角位置,避免了在所述接触孔220侧壁顶部的边角位置分布的抑制剂过多,减弱了对所述接触孔220侧壁顶部导电层240的纵向生长的抑制作用,使得在导电层240中形成的凹陷250向所述开口211的侧壁推移。
参考图10,平坦化所述导电层240和绝缘层230直至暴露出所述掩膜层210的表面。
平坦化所述导电层240和绝缘层230后,形成导电插塞结构。
平坦化所述导电层240和绝缘层230的工艺为化学机械掩膜工艺。
在平坦化所述导电层240和绝缘层230的过程中,所述掩膜层210起到停止层的作用。
由于导电层240中凹陷250的最低端距离所述接触孔220的水平距离较远,且所述绝缘层230的厚度大于等于刻蚀后的所述掩膜层210的厚度,尽管在平坦化所述导电层240和绝缘层230的过程中,所述凹陷250会随形下落,但是当平坦化所述导电层240和绝缘层230直至暴露出所述掩膜层210的表面时,所述凹陷250随形下落产生的缺陷均被研磨去除,避免了导电层240与绝缘层230之间形成缺口。
后续在导电层240表面形成金属层时,一方面,能够避免导电层240和金属层接触不良,提高导电插塞结构的导电性,另一方面,避免导电层240中的原子扩散,从而避免导电层240出现电迁移和应力迁移,提高导电插塞结构的可靠性,从而提高了导电插塞结构的性能。
第二实施例
图11至图12为本发明第二实施例中导电插塞结构形成过程的结构示意图。
第二实施例与第一实施例的区别在于:在第一实施例的基础上,在绝缘层和导电层之间形成阻挡层。关于第二实施例中与第一实施例相同的部分,不再详述。
参考图11,图11为在图8基础上形成的示意图,在绝缘层230表面形成阻挡层330;在所述绝缘层230表面形成填充满所述接触孔220(参考图8)的导电层340。
所述阻挡层330的作用为:防止导电层340中的原子发生扩散。
所述阻挡层330的材料为氮化钛或氮化钽。
若所述阻挡层330的厚度较厚,会使得导电层340填充的空间较小,影响导电层340的填充;若所述阻挡层330的厚度较薄,使得阻碍导电层340中的原子扩散的能力较弱,故本实施例中,所述阻挡层330的厚度选择为800埃~1500埃。
形成所述阻挡层330的工艺为沉积工艺,如物理气相沉积工艺或原子层沉积工艺。本实施例中,形成所述阻挡层330的工艺为物理气相沉积工艺。
导电层340的形成方法参照第一实施例中导电层240的形成方法,不再详述。
形成的导电层340中存在凹陷350,形成凹陷350的过程和原因参照第一实施例,不再详述。
参考图12,平坦化所述导电层340、阻挡层330和绝缘层230,直至暴露出所述掩膜层210表面。
平坦化所述导电层340、阻挡层330和绝缘层230的工艺为化学机械掩膜工艺。
平坦化后,所述凹陷350随形下落产生的缺陷被研磨去除,避免了所述导电层340在所述接触孔220侧壁顶部的位置产生缺口。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (11)
1.一种导电插塞结构的形成方法,其特征在于,包括:
提供基底;
在所述基底上形成具有开口的掩膜层;
以所述掩膜层为掩膜刻蚀所述基底,在所述基底中形成接触孔;
刻蚀所述掩膜层,使所述开口的线宽尺寸增大;
在刻蚀后的所述掩膜层表面、所述接触孔内壁和所述开口内壁形成绝缘层,
且所述绝缘层的厚度大于等于刻蚀后的所述掩膜层的厚度;
在所述绝缘层表面形成填充满所述接触孔的导电层;
平坦化所述导电层和绝缘层直至暴露出所述掩膜层的表面。
2.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,刻蚀所述掩膜层后的开口的线宽尺寸与所述接触孔的线宽尺寸比为1.02~1.1。
3.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,所述掩膜层的材料为氮化硅或氮氧化硅。
4.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,刻蚀所述掩膜层的工艺为湿刻工艺,采用的刻蚀溶液为磷酸溶液,磷酸的质量百分比浓度为80%~90%,刻蚀温度为120摄氏度~180摄氏度。
5.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,刻蚀后的所述掩膜层的厚度为800埃~1200埃。
6.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,所述导电层的材料为钽、氮化钽或铜。
7.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,形成所述导电层的工艺为电镀工艺。
8.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,平坦化所述导电层和绝缘层的工艺为化学机械研磨工艺。
9.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,所述绝缘层的材料为氧化硅。
10.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,形成所述绝缘层的工艺为原子层沉积工艺。
11.根据权利要求1所述的导电插塞结构的形成方法,其特征在于,还包括:在形成所述导电层之前,在所述绝缘层表面形成阻挡层;平坦化所述导电层和绝缘层的同时平坦化所述阻挡层直至暴露出所述掩膜层的表面。
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