CN106463447B - 基板和形成基板的方法 - Google Patents

基板和形成基板的方法 Download PDF

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Publication number
CN106463447B
CN106463447B CN201580024484.6A CN201580024484A CN106463447B CN 106463447 B CN106463447 B CN 106463447B CN 201580024484 A CN201580024484 A CN 201580024484A CN 106463447 B CN106463447 B CN 106463447B
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China
Prior art keywords
dielectric layer
trace
hole
substrate
photoimageable
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Expired - Fee Related
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CN201580024484.6A
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English (en)
Chinese (zh)
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CN106463447A (zh
Inventor
H·W·乔玛
O·J·比奇厄
K·康
C-K·金
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN106463447A publication Critical patent/CN106463447A/zh
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Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
CN201580024484.6A 2014-05-13 2015-04-27 基板和形成基板的方法 Expired - Fee Related CN106463447B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/276,763 US9679841B2 (en) 2014-05-13 2014-05-13 Substrate and method of forming the same
US14/276,763 2014-05-13
PCT/US2015/027806 WO2015175197A1 (en) 2014-05-13 2015-04-27 Substrate and method of forming the same

Publications (2)

Publication Number Publication Date
CN106463447A CN106463447A (zh) 2017-02-22
CN106463447B true CN106463447B (zh) 2018-06-29

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580024484.6A Expired - Fee Related CN106463447B (zh) 2014-05-13 2015-04-27 基板和形成基板的方法

Country Status (5)

Country Link
US (1) US9679841B2 (enExample)
EP (1) EP3143640B1 (enExample)
JP (1) JP6306743B2 (enExample)
CN (1) CN106463447B (enExample)
WO (1) WO2015175197A1 (enExample)

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US10340251B2 (en) 2017-04-26 2019-07-02 Nxp Usa, Inc. Method for making an electronic component package
US10157833B1 (en) * 2017-05-23 2018-12-18 Globalfoundries Inc. Via and skip via structures
US20180350630A1 (en) * 2017-06-01 2018-12-06 Qualcomm Incorporated Symmetric embedded trace substrate
US10325842B2 (en) * 2017-09-08 2019-06-18 Advanced Semiconductor Engineering, Inc. Substrate for packaging a semiconductor device package and a method of manufacturing the same
US11116084B2 (en) 2017-09-27 2021-09-07 Intel Corporation Method, device and system for providing etched metallization structures
US11387187B2 (en) * 2018-06-28 2022-07-12 Intel Corporation Embedded very high density (VHD) layer
US20200083154A1 (en) 2018-09-10 2020-03-12 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation
US10517167B1 (en) * 2018-10-19 2019-12-24 Eagle Technology, Llc Systems and methods for providing a high speed interconnect system with reduced crosstalk
US10615027B1 (en) 2018-10-25 2020-04-07 International Business Machines Corporation Stack viabar structures
EP3723459A1 (en) 2019-04-10 2020-10-14 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with high passive intermodulation (pim) performance
US11056850B2 (en) 2019-07-26 2021-07-06 Eagle Technology, Llc Systems and methods for providing a soldered interface on a printed circuit board having a blind feature
US11602800B2 (en) 2019-10-10 2023-03-14 Eagle Technology, Llc Systems and methods for providing an interface on a printed circuit board using pin solder enhancement
US11283204B1 (en) 2020-11-19 2022-03-22 Eagle Technology, Llc Systems and methods for providing a composite connector for high speed interconnect systems
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate
KR20230055561A (ko) 2021-10-19 2023-04-26 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 전자부품 패키지
US12412822B2 (en) * 2021-12-31 2025-09-09 Samsung Electro-Mechanics Co., Ltd. Semiconductor chip and semiconductor package including the same
US12035482B2 (en) * 2022-02-07 2024-07-09 Eagle Technology, Llc Electronic device with multi-diameter female contacts and related methods

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EP1519414A1 (en) * 2002-07-03 2005-03-30 Sony Corporation Multilayer wiring circuit module and method for fabricating the same
CN102405524A (zh) * 2009-02-20 2012-04-04 国家半导体公司 集成电路微模块

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JP4701506B2 (ja) * 2000-09-14 2011-06-15 ソニー株式会社 回路ブロック体の製造方法、配線回路装置の製造方法並びに半導体装置の製造方法
JP3861669B2 (ja) 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
TW561803B (en) 2002-10-24 2003-11-11 Advanced Semiconductor Eng Circuit substrate and manufacturing method thereof
TWI295550B (en) * 2005-12-20 2008-04-01 Phoenix Prec Technology Corp Structure of circuit board and method for fabricating the same
US20080169124A1 (en) 2007-01-12 2008-07-17 Tonglong Zhang Padless via and method for making same
KR20100065691A (ko) 2008-12-08 2010-06-17 삼성전기주식회사 금속범프를 갖는 인쇄회로기판 및 그 제조방법
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Also Published As

Publication number Publication date
JP2017516308A (ja) 2017-06-15
US9679841B2 (en) 2017-06-13
JP6306743B2 (ja) 2018-04-04
EP3143640B1 (en) 2020-01-08
US20150333004A1 (en) 2015-11-19
WO2015175197A1 (en) 2015-11-19
CN106463447A (zh) 2017-02-22
EP3143640A1 (en) 2017-03-22

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Granted publication date: 20180629

Termination date: 20210427