JP2017516308A - 基板および基板を形成する方法 - Google Patents
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
110 活性ダイ、第1のダイ
120 活性ダイ、第2のダイ
130 基板
131 第1の誘電体層
132 第2の誘電体層
140 埋込型トレース
150 ビアトレース
160 パッドレススキップビア
161 パッドレススキップビア本体
162 上部分
163 底部分
164 カバーパッド
170 パッドレススキップビア
200 テンポラリコア
202 第1の銅層
204 第2の銅層
210 第1の誘電体層
212 第2の誘電体層
214 トレースパターン
216 銅トレース
220 第3の誘電体層
222 第4の誘電体層
230 第1のビア
232 第2のビア
240 第1のパッドレススキップビア
241 カバーパッド
242 第2のパッドレスビア
243 カバーパッド
244 底部トレース
245 SR層
246 SR層
Claims (30)
- 基板構造を製造するための方法であって、
コア材料の銅層上に光活性誘電体層を積層するステップと、
前記光活性誘電体層上に複数のトレースパターンを形成するステップと、
複数のトレースを形成するために前記複数のトレースパターンをめっきするステップと、
前記光活性誘電体層上に絶縁性誘電体層を形成するステップと、
前記絶縁性誘電体層および前記光活性誘電体層を通るビアを形成するステップと、
前記絶縁性誘電体層上に追加のルーティングパターンを形成するステップと、
前記コア材料を除去するステップと、
はんだマスクを施すステップと
を含む、方法。 - 前記複数のトレースが、5μm/5μm未満のラインアンドスペース寸法を有する、請求項1に記載の方法。
- 前記複数のトレースが、2μm/2μmのラインアンドスペース寸法を有する、請求項1に記載の方法。
- 前記ビアがスキップビアである、請求項1に記載の方法。
- 前記ビアがパッドレススキップビアである、請求項1に記載の方法。
- 前記光活性誘電体層が10μm未満である、請求項1に記載の方法。
- 前記光活性誘電体層が約5μmである、請求項1に記載の方法。
- 前記絶縁性誘電体層が約15μmである、請求項1に記載の方法。
- 前記絶縁性誘電体層が、前記光活性誘電体層とは異なる組成物である、請求項1に記載の方法。
- コア材料の銅層上に光活性誘電体層を積層するステップと、
前記光活性誘電体層内に複数のトレースパターンを形成するステップと、
複数のトレースを形成するために前記複数のトレースパターンをめっきするステップと、
前記光活性誘電体層上に絶縁性誘電体層を形成するステップと、
前記絶縁性誘電体層および前記光活性誘電体層を通るビアを形成するステップと、
前記絶縁性誘電体層上に追加のルーティングパターンを形成するステップと、
前記コア材料を除去するステップと、
はんだマスクを施すステップと
を含むプロセスによって用意される基板。 - 前記複数のトレースが、5μm/5μm未満のラインアンドスペース寸法を有する、請求項10に記載のプロセスの製品。
- 前記複数のトレースが、2μm/2μmのラインアンドスペース寸法を有する、請求項10に記載のプロセスの製品。
- 前記ビアがスキップビアである、請求項10に記載のプロセスの製品。
- 前記ビアがパッドレススキップビアである、請求項10に記載のプロセスの製品。
- 前記光活性誘電体層が10μm未満である、請求項10に記載のプロセスの製品。
- 前記光活性誘電体層が約5μmである、請求項10に記載のプロセスの製品。
- 前記絶縁性誘電体層が約15μmである、請求項10に記載のプロセスの製品。
- 前記絶縁性誘電体層が、前記光活性誘電体層とは異なる組成物である、請求項10に記載のプロセスの製品。
- 永続的光活性誘電体層および絶縁性誘電体層を有するコアレス基板と、
前記永続的光活性誘電体層に埋め込まれた複数のトレースと、
前記絶縁性誘電体層および前記永続的光画像形成可能誘電体層を通って延在するビアと
を含む、半導体構造。 - 前記複数のトレースが、5μm/5μm未満のラインアンドスペース寸法を有する、請求項19に記載の半導体構造。
- 前記複数のトレースが、2μm/2μmのラインアンドスペース寸法を有する、請求項19に記載の半導体構造。
- 前記ビアがスキップビアである、請求項19に記載の半導体構造。
- 前記ビアがパッドレススキップビアである、請求項19に記載の半導体構造。
- 前記光活性誘電体層が10μm未満である、請求項19に記載の半導体構造。
- 前記光活性誘電体層が約5μmである、請求項19に記載の半導体構造。
- 前記絶縁性誘電体層が約15μmである、請求項19に記載の半導体構造。
- 前記絶縁性誘電体層が、前記光活性誘電体層とは異なる組成物である、請求項19に記載の半導体構造。
- 永続的光活性誘電体層および絶縁性誘電体層を有するコアレス基板と、
前記永続的光活性誘電体層に埋め込まれた複数のトレースと、
前記絶縁性誘電体層および前記永続的光画像形成可能誘電体層を通って延在する、導通させるための手段と
を含む、半導体構造。 - 前記複数のトレースが、5μm/5μm未満のラインアンドスペース寸法を有する、請求項28に記載の半導体構造。
- 前記複数のトレースが、2μm/2μmのラインアンドスペース寸法を有する、請求項28に記載の半導体構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/276,763 US9679841B2 (en) | 2014-05-13 | 2014-05-13 | Substrate and method of forming the same |
US14/276,763 | 2014-05-13 | ||
PCT/US2015/027806 WO2015175197A1 (en) | 2014-05-13 | 2015-04-27 | Substrate and method of forming the same |
Publications (3)
Publication Number | Publication Date |
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JP2017516308A true JP2017516308A (ja) | 2017-06-15 |
JP2017516308A5 JP2017516308A5 (ja) | 2017-09-14 |
JP6306743B2 JP6306743B2 (ja) | 2018-04-04 |
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Application Number | Title | Priority Date | Filing Date |
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JP2016567193A Expired - Fee Related JP6306743B2 (ja) | 2014-05-13 | 2015-04-27 | 基板および基板を形成する方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9679841B2 (ja) |
EP (1) | EP3143640B1 (ja) |
JP (1) | JP6306743B2 (ja) |
CN (1) | CN106463447B (ja) |
WO (1) | WO2015175197A1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107680942B (zh) * | 2016-08-01 | 2019-10-11 | 欣兴电子股份有限公司 | 线路载板及其制作方法 |
US10340251B2 (en) | 2017-04-26 | 2019-07-02 | Nxp Usa, Inc. | Method for making an electronic component package |
US10157833B1 (en) * | 2017-05-23 | 2018-12-18 | Globalfoundries Inc. | Via and skip via structures |
US20180350630A1 (en) * | 2017-06-01 | 2018-12-06 | Qualcomm Incorporated | Symmetric embedded trace substrate |
US10325842B2 (en) * | 2017-09-08 | 2019-06-18 | Advanced Semiconductor Engineering, Inc. | Substrate for packaging a semiconductor device package and a method of manufacturing the same |
US11116084B2 (en) | 2017-09-27 | 2021-09-07 | Intel Corporation | Method, device and system for providing etched metallization structures |
US11387187B2 (en) * | 2018-06-28 | 2022-07-12 | Intel Corporation | Embedded very high density (VHD) layer |
US10517167B1 (en) * | 2018-10-19 | 2019-12-24 | Eagle Technology, Llc | Systems and methods for providing a high speed interconnect system with reduced crosstalk |
US10615027B1 (en) | 2018-10-25 | 2020-04-07 | International Business Machines Corporation | Stack viabar structures |
EP3723459A1 (en) | 2019-04-10 | 2020-10-14 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with high passive intermodulation (pim) performance |
US11056850B2 (en) | 2019-07-26 | 2021-07-06 | Eagle Technology, Llc | Systems and methods for providing a soldered interface on a printed circuit board having a blind feature |
US11602800B2 (en) | 2019-10-10 | 2023-03-14 | Eagle Technology, Llc | Systems and methods for providing an interface on a printed circuit board using pin solder enhancement |
US11283204B1 (en) | 2020-11-19 | 2022-03-22 | Eagle Technology, Llc | Systems and methods for providing a composite connector for high speed interconnect systems |
US20230254980A1 (en) * | 2022-02-07 | 2023-08-10 | Eagle Technology, Llc | Electronic device with multi-diameter female contacts and related methods |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001036238A (ja) * | 1999-07-19 | 2001-02-09 | Nitto Denko Corp | 回路基板の製造方法および回路基板 |
JP2002164467A (ja) * | 2000-09-14 | 2002-06-07 | Sony Corp | 回路ブロック体及びその製造方法、配線回路装置及びその製造方法並びに半導体装置及びその製造方法 |
JP2004039867A (ja) * | 2002-07-03 | 2004-02-05 | Sony Corp | 多層配線回路モジュール及びその製造方法 |
JP2007173775A (ja) * | 2005-12-20 | 2007-07-05 | Phoenix Precision Technology Corp | 回路基板構造及びその製法 |
US20100213601A1 (en) * | 2009-02-20 | 2010-08-26 | National Semiconductor Corporation | Integrated circuit micro-module |
JP2013214579A (ja) * | 2012-03-30 | 2013-10-17 | Ibiden Co Ltd | 配線板及びその製造方法 |
JP2014093330A (ja) * | 2012-10-31 | 2014-05-19 | Ibiden Co Ltd | 配線板及びその製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3861669B2 (ja) | 2001-11-22 | 2006-12-20 | ソニー株式会社 | マルチチップ回路モジュールの製造方法 |
TW561803B (en) | 2002-10-24 | 2003-11-11 | Advanced Semiconductor Eng | Circuit substrate and manufacturing method thereof |
US20080169124A1 (en) | 2007-01-12 | 2008-07-17 | Tonglong Zhang | Padless via and method for making same |
KR20100065691A (ko) | 2008-12-08 | 2010-06-17 | 삼성전기주식회사 | 금속범프를 갖는 인쇄회로기판 및 그 제조방법 |
EP2399288B1 (en) * | 2009-02-20 | 2018-08-15 | National Semiconductor Corporation | Integrated circuit micro-module |
US8187920B2 (en) | 2009-02-20 | 2012-05-29 | Texas Instruments Incorporated | Integrated circuit micro-module |
JP5603600B2 (ja) * | 2010-01-13 | 2014-10-08 | 新光電気工業株式会社 | 配線基板及びその製造方法、並びに半導体パッケージ |
JP5570855B2 (ja) * | 2010-03-18 | 2014-08-13 | 新光電気工業株式会社 | 配線基板及びその製造方法並びに半導体装置及びその製造方法 |
US20110272780A1 (en) | 2010-05-05 | 2011-11-10 | Peter Smeys | Method and structure for improving the qualilty factor of rf inductors |
JP5711472B2 (ja) * | 2010-06-09 | 2015-04-30 | 新光電気工業株式会社 | 配線基板及びその製造方法並びに半導体装置 |
US8648277B2 (en) | 2011-03-31 | 2014-02-11 | Electro Scientific Industries, Inc. | Laser direct ablation with picosecond laser pulses at high pulse repetition frequencies |
JP5851211B2 (ja) * | 2011-11-11 | 2016-02-03 | 新光電気工業株式会社 | 半導体パッケージ、半導体パッケージの製造方法及び半導体装置 |
-
2014
- 2014-05-13 US US14/276,763 patent/US9679841B2/en active Active
-
2015
- 2015-04-27 WO PCT/US2015/027806 patent/WO2015175197A1/en active Application Filing
- 2015-04-27 JP JP2016567193A patent/JP6306743B2/ja not_active Expired - Fee Related
- 2015-04-27 EP EP15722828.9A patent/EP3143640B1/en active Active
- 2015-04-27 CN CN201580024484.6A patent/CN106463447B/zh not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001036238A (ja) * | 1999-07-19 | 2001-02-09 | Nitto Denko Corp | 回路基板の製造方法および回路基板 |
JP2002164467A (ja) * | 2000-09-14 | 2002-06-07 | Sony Corp | 回路ブロック体及びその製造方法、配線回路装置及びその製造方法並びに半導体装置及びその製造方法 |
JP2004039867A (ja) * | 2002-07-03 | 2004-02-05 | Sony Corp | 多層配線回路モジュール及びその製造方法 |
JP2007173775A (ja) * | 2005-12-20 | 2007-07-05 | Phoenix Precision Technology Corp | 回路基板構造及びその製法 |
US20100213601A1 (en) * | 2009-02-20 | 2010-08-26 | National Semiconductor Corporation | Integrated circuit micro-module |
JP2013214579A (ja) * | 2012-03-30 | 2013-10-17 | Ibiden Co Ltd | 配線板及びその製造方法 |
JP2014093330A (ja) * | 2012-10-31 | 2014-05-19 | Ibiden Co Ltd | 配線板及びその製造方法 |
Also Published As
Publication number | Publication date |
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US20150333004A1 (en) | 2015-11-19 |
US9679841B2 (en) | 2017-06-13 |
CN106463447B (zh) | 2018-06-29 |
JP6306743B2 (ja) | 2018-04-04 |
EP3143640A1 (en) | 2017-03-22 |
EP3143640B1 (en) | 2020-01-08 |
CN106463447A (zh) | 2017-02-22 |
WO2015175197A1 (en) | 2015-11-19 |
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