US20080169124A1 - Padless via and method for making same - Google Patents
Padless via and method for making same Download PDFInfo
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- US20080169124A1 US20080169124A1 US11/652,735 US65273507A US2008169124A1 US 20080169124 A1 US20080169124 A1 US 20080169124A1 US 65273507 A US65273507 A US 65273507A US 2008169124 A1 US2008169124 A1 US 2008169124A1
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- via hole
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09545—Plated through-holes or blind vias without lands
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention is generally in the field of electronic arts. More specifically, the invention is in the field of packaging of electronic components and devices.
- die package substrates and circuit boards each phrase “die package substrate” and “circuit board” is also generally referred to as a “substrate” in the present application
- substrate each phrase “die package substrate” and “circuit board” is also generally referred to as a “substrate” in the present application
- the density of interconnects used in die package substrates and circuit boards has increased as well.
- Progress towards greater circuit density and higher performance has been achieved in part through the introduction of multi-layered die package substrates and circuit boards and the use of vias in these die package substrates and circuit boards.
- Vias are electrically conductive structures extending through a die package substrate or a circuit board.
- a via provides a conductive path for a signal traveling from one surface to another surface of a dielectric layer, or between different surfaces in a multi-layered die package substrate or circuit board. Such a path is typically established by depositing a layer of conductive material onto the inner wall of a via hole.
- the conductive material on the inner wall of the via is protected during later patterning of the die package substrate or circuit board surface, by introduction of a photoresist plug over the via hole.
- Reliance on a photoresist plug during patterning results in retention on the die package substrate or circuit board surface of a perimeter region made up of a conductive material that surrounds the opening of each via hole.
- These perimeter regions also referred to as via pads, are undesirable for a number of reasons. For example, via pads occupy space otherwise allocable to interconnect traces which connect circuit components, and they also present an obstacle to flexibility in designing and patterning the interconnect traces and make signal routing less efficient.
- the via pad may represent a large percentage, for example more than 60%, of the total lateral area consumed by a via. Elimination of the via pad represents a substantial decrease in the surface footprint of the via, with corresponding enhancements in both available surface space and interconnect routing flexibility and efficiency. Simply stated, reduction or elimination of via pads makes possible significant improvements in the functionality and performance of existing die package substrates and circuit boards. Moreover, smaller die package substrates and circuit boards are possible, which result in flexibility in system design and substantial cost savings.
- FIGS. 1A and 1B show top and cross-sectional views of a conventional padded via.
- FIG. 2 is a flow chart of an exemplary method to implement an embodiment of the present invention.
- FIG. 3 shows an exemplary structure corresponding to an initial step in the flow chart of FIG. 2 .
- FIGS. 4A and 4B show top and cross-sectional views of an exemplary structure corresponding to an intermediate step in the flow chart of FIG. 2 .
- FIG. 5 shows an exemplary structure corresponding to an intermediate step in the flow chart of FIG. 2 .
- FIG. 6 shows an exemplary structure corresponding to an intermediate step in the flow chart of FIG. 2 .
- FIGS. 7A and 7B show top and cross-sectional views of an exemplary structure corresponding to a final step in the flow chart of FIG. 2 .
- the present invention is directed to a padless via and method for making same.
- the following description contains specific information pertaining to the implementation of the present invention.
- One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art.
- a via is an electrically conductive structure extending through a die package substrate or a circuit board. It may be thermally as well as electrically conductive. As known in the art, a via provides a conductive path for a signal traveling from one surface to another surface of a dielectric layer, or between different surfaces in a multi-layered die package substrate or circuit board. Such a path is typically established by depositing a layer of conductive material onto the inner wall of a via hole. The conductive material applied to the inner wall may be deposited electrically, chemically, or by some other means. Suitable materials include but are not limited to, copper, aluminum, gold, molybdenum, tungsten, other metals, or combinations/alloys of those metals.
- a number of via holes are drilled through the circuit board. Electrical contact between the blanket metal layer and other conductive layers within or on the opposing side of the circuit board is established by application of a thin seed layer of conductive material to the inner wall of each via hole.
- the seed layer may be copper, applied electrolessly in a plating bath, in such a way that the seed layer is deposited over the entire substrate surface as well as along each via inner wall.
- a more robust layer of conducting material is applied, typically through electrolytic plating.
- the plating layer is applied in roughly equal thickness to the inner wall of each via, and to the lateral surface of the circuit board.
- the inner wall of each via carries an accumulated layer of conductive material composed of the nominal seed layer plus the plating layer applied electrolytically.
- the circuit board's lateral surface carries the accumulation of its own blanket layer (i.e. the metal laminate) in addition to the two layers applied to the inner wall of each via.
- the circuit board lateral surface carries a thicker conductive layer than that present on the inner wall of each via hole, at the time surface patterning occurs.
- each via hole is covered, or plugged, with a mask such as photoresist.
- a mask such as photoresist.
- its plug must completely overlap it, and consequently the plug extends to a surface perimeter beyond the boundary established by the via hole. In so doing, it defines an overlay perimeter region, or via pad, in which region the surface conductive layer is protected and retained during the patterning step, and the via pad will thus remain in the final trace pattern on the circuit board.
- the conventional via formation process described results in a via surrounded by a perimeter region of excess conducting material, or a padded via.
- the surface area of the pad itself may be responsible for a large percentage, for example more than 60%, of the total lateral surface area occupied by the via (the total lateral space being also referred to as “total via footprint” in the present application).
- Structure 170 A in FIG. 1A illustrates a top view of a single conventional padded via and the resulting surface area occupied by it on substrate surface 122 a , which can be a surface of a circuit board or a die package substrate.
- Distance 180 represents the diameter of the circular area occupied on substrate surface 122 a by the circular boundary of via hole 102 .
- the via hole may be entirely filled with conductive material. In others, as is the case in structure 170 A, a portion of the via hole remains unfilled.
- the conductive material deposited on inner wall 114 of via hole 102 during the seeding and plating processes accumulates to form conductive lining 116 , which has thickness 112 .
- a plug of patterning mask such as photoresist is applied to overlay via hole 102 , as well as to form an extension region beyond via hole 102 , leaving a total via footprint with diameter 190 .
- substrate surface 122 a is unmasked to reveal conductive tracings 110 , and via pad 138 resulting from the extended overlay region masked during patterning, and enclosed by perimeter 118 .
- via pad 138 together with via hole 102 result in a padded via with a total via footprint with a total diameter 190 .
- Structure 170 B in FIG. 1B illustrates a cross-sectional view of the conventional padded via of FIG. 1A , comprising via hole 102 and via pad 138 .
- FIG. 1B provides additional perspective on the excess substrate surface area occupied by the pad in a conventional padded via.
- distance 180 represents the diameter of via hole 102 , a portion of which is filled as a result of the presence of conductive lining 116 having thickness 112 .
- conductive lining 116 defines an inner conductive ring of thickness 112 .
- via pad 138 Surrounding the inner conductive ring defined by conductive lining 116 , via pad 138 defines an outer conductive ring bounded by perimeter 118 .
- via pad 138 occupies a conductive buffer region connecting conductive tracings 110 to the inner conductive ring defined by conductive lining 116 .
- the total substrate surface area occupied by a padded via that is the sum of the surface area corresponding to the via hole and the area occupied by the via pad, is referred to as the total via footprint in the present application.
- the total via footprint of the padded via shown in FIGS. 1A and 1B is proportional to the square of diameter 190 .
- the substrate area occupied by via hole 102 including the area occupied by the inner conductive ring defined by conductive lining 116 , is proportional to the square of diameter 180 .
- diameter 180 may be as great as 200 microns, with via pad overlay tolerances as liberal as 75 microns or more, resulting in a footprint diameter 190 of as much as 350 microns or more.
- FIG. 2 shows flow chart 200 , which describes the steps, according to one embodiment of the present invention, in the formation of a padless via. Certain details and features have been left out of flow chart 200 that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art. While steps 230 through 270 indicated in flow chart 200 are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown in flow chart 200 .
- Substrate bulk 322 b can comprise, for example, a multi-layer organic laminate such as polytetrafluoroethylene, other organic materials such as FR-4 based laminate, and/or ceramic materials.
- Structure 330 of FIG. 3 is a cross sectional view of a substrate on which blanket metal layer 332 is formed on substrate surface 322 a according to preliminary step 230 of flow chart 200 in FIG. 2 .
- Blanket metal layer 332 may comprise copper, and may have thickness 362 of, for example, 12 microns in some embodiments. However, blanket metal layer 332 may comprise other metals and have other thicknesses.
- via holes are drilled through blanket metal layer 432 and into substrate surface 422 a and substrate bulk 422 b .
- Structure 440 A of FIG. 4A illustrates a top view of a circuit board in which a number of via holes, such as via holes 402 , 404 , 406 , and 408 , have been formed according to step 240 of the flow chart of FIG. 2 .
- structure 440 B shows a portion of structure 440 A of FIG. 4A , including via hole 402 having diameter 480 .
- Structure 440 B thus shows the portion of substrate surface 422 a and substrate bulk 422 b which includes via hole 402 having via inner wall 414 , and sections of substrate surface 422 a on which blanket metal layer 432 having thickness 462 has been formed.
- a seed layer of conductive material such as copper or a copper alloy, is applied to via inner wall 514 and blanketed substrate surface 522 a .
- the seed layer may be applied electrolessly, through deposition of a metal layer by means of a reducing chemical bath.
- structure 550 represents structure 440 B in FIG. 4B , after application of a seed layer.
- seed layer 534 having thickness 564 has been applied to blanket metal layer 532 and inner via wall 514 of via hole 502 .
- differential plating of a conductive material is performed over seed layer 634 situated over blanket metal layer 632 and via inner wall 614 of via hole 602 .
- differential plating is achieved through addition of an organic suppressant to an electrolytic plating bath.
- a plating differential rate may be adjusted by changing the bias used during the electrolytic plating process.
- conductive material is preferentially plated onto the portion of the seed layer situated over via inner wall 614 , relative to the portion of the seed layer situated over blanket metal layer 632 such that a thicker layer of the conductive plating material is formed on via inner wall 614 and a thinner layer is formed over substrate surface 622 a .
- Structure 660 in FIG. 6 illustrates via hole 602 after differential plating has occurred according to step 260 of flow chart 200 .
- plating layer 636 is formed over both blanket metal layer 632 and via inner wall 614 , but plating layer 636 accumulates an inner wall plating thickness 668 greater than thickness 666 deposited over substrate surface 622 a .
- differential plating is performed to such a degree and effect that it is akin to anisotropic plating.
- differential plating may be performed such that the conductive material is plated in one direction only, i.e. only on via inner wall 614 , and not on substrate surface 622 a.
- patterning of substrate surface 622 a in FIG. 6 proceeds without use of a protective plug overlaying via hole 602 .
- Unprotected patterning may occur during practice of the present invention, without risk of complete removal of plating layer 636 on via inner wall 614 .
- conductive plated material is completely etched away from unmasked regions of plating layer 636 situated over substrate surface 622 a .
- plating layer 636 has a greater thickness 668 over via inner wall 614 than thickness 666 over substrate surface 622 a , thickness 668 of plating layer 636 over via inner wall 614 is merely reduced during etching, but conductive plating 636 is not eliminated from, and remains on, via inner wall 614 , while the accumulated layers 632 , 634 and 636 are completely removed from unprotected regions of substrate surface 622 a . In other words, the accumulated blanket metal layer 632 , seed layer 634 , and plating layer 636 are completely removed from unprotected regions of substrate surface 622 a.
- structure 770 A of FIG. 7A illustrates a top view of a region on the circuit board surrounding via hole 702 after patterning has occurred.
- Structure 770 B of FIG. 7B illustrates the cross-sectional view of via hole 702 corresponding to the top view of FIG. 7A .
- substrate surface 722 a , substrate bulk 722 b , conductive tracings 710 , inner wall 714 of via hole 702 , conductive lining 716 of via hole 702 , distance 780 representing the diameter of via hole 702 , and thickness 712 of conductive lining 716 correspond respectively to substrate surface 122 a , substrate bulk 122 b , conductive tracings 110 , inner wall 114 of via hole 102 , conductive lining 116 of via hole 102 , distance 180 representing the diameter of via hole 102 , and thickness 112 of conductive lining 116 of structures 170 A and 170 B of FIGS. 1A and 1B .
- the inner conductive ring defined by conductive lining 716 of via hole 702 in FIG. 7A corresponds to the inner conductive ring defined by conductive lining 116 of via hole 102 in FIG. 1A .
- conductive tracings 710 are directly connected to conductive lining 716 of the padless via of the present invention.
- Comparison of exemplary structures 770 A and 770 B of the invention's padless via with corresponding structures 170 A and 170 B of a conventional padded via illustrates the reduction in the total via footprint that is achieved by the present invention.
- via pad 138 that is present in the conventional padded via of FIGS. 1A and 1B , is entirely eliminated by the present invention. Referring to FIGS.
- plating layer 636 is not eliminated from via inner wall 614 , and remains on conductive lining 716 of via hole 702 in the final structures 770 A and 770 B shown in FIGS. 7A and 7B .
- the total via footprint in the present invention is advantageously limited to distance 780 representing the diameter of via hole 702 .
- the total via footprint in the conventional padded via is expanded by the dimensions of via pad 138 shown in FIG. 1A , which undesirably results in a much greater total via footprint as discussed above.
- the present invention makes possible formation of vias occupying substantially less surface area of a circuit board or a die package substrate than conventional practices allow.
- absence of via pads permits greater signal routing flexibility and efficiency on the surface of the circuit board or die package substrate.
- greater device, component, and/or die densities can be achieved on comparable surface areas.
- existing device, component, and/or die densities and their corresponding connection densities can be achieved on smaller surfaces, resulting in scalable reductions in packaging size and space, with substantial associated cost savings.
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Abstract
Description
- 1. Field of the Invention
- The present invention is generally in the field of electronic arts. More specifically, the invention is in the field of packaging of electronic components and devices.
- 2. Background Art
- As electronic devices become more integrated with increased functionality and higher levels of performance, the complexity of the packaging structures, for example, die package substrates and circuit boards (each phrase “die package substrate” and “circuit board” is also generally referred to as a “substrate” in the present application), that are used to effectuate signal transmission has grown. As a further result of the increase in functionality and performance, the density of interconnects used in die package substrates and circuit boards has increased as well. Progress towards greater circuit density and higher performance has been achieved in part through the introduction of multi-layered die package substrates and circuit boards and the use of vias in these die package substrates and circuit boards.
- Vias are electrically conductive structures extending through a die package substrate or a circuit board. As known in the art, a via provides a conductive path for a signal traveling from one surface to another surface of a dielectric layer, or between different surfaces in a multi-layered die package substrate or circuit board. Such a path is typically established by depositing a layer of conductive material onto the inner wall of a via hole.
- In conventional techniques, the conductive material on the inner wall of the via is protected during later patterning of the die package substrate or circuit board surface, by introduction of a photoresist plug over the via hole. Reliance on a photoresist plug during patterning results in retention on the die package substrate or circuit board surface of a perimeter region made up of a conductive material that surrounds the opening of each via hole. These perimeter regions, also referred to as via pads, are undesirable for a number of reasons. For example, via pads occupy space otherwise allocable to interconnect traces which connect circuit components, and they also present an obstacle to flexibility in designing and patterning the interconnect traces and make signal routing less efficient.
- In a conventional padded via, the via pad may represent a large percentage, for example more than 60%, of the total lateral area consumed by a via. Elimination of the via pad represents a substantial decrease in the surface footprint of the via, with corresponding enhancements in both available surface space and interconnect routing flexibility and efficiency. Simply stated, reduction or elimination of via pads makes possible significant improvements in the functionality and performance of existing die package substrates and circuit boards. Moreover, smaller die package substrates and circuit boards are possible, which result in flexibility in system design and substantial cost savings.
- A padless via and method for making same substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
-
FIGS. 1A and 1B show top and cross-sectional views of a conventional padded via. -
FIG. 2 is a flow chart of an exemplary method to implement an embodiment of the present invention. -
FIG. 3 shows an exemplary structure corresponding to an initial step in the flow chart ofFIG. 2 . -
FIGS. 4A and 4B show top and cross-sectional views of an exemplary structure corresponding to an intermediate step in the flow chart ofFIG. 2 . -
FIG. 5 shows an exemplary structure corresponding to an intermediate step in the flow chart ofFIG. 2 . -
FIG. 6 shows an exemplary structure corresponding to an intermediate step in the flow chart ofFIG. 2 . -
FIGS. 7A and 7B show top and cross-sectional views of an exemplary structure corresponding to a final step in the flow chart ofFIG. 2 . - The present invention is directed to a padless via and method for making same. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art.
- The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the invention which use the principles of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings.
- A via is an electrically conductive structure extending through a die package substrate or a circuit board. It may be thermally as well as electrically conductive. As known in the art, a via provides a conductive path for a signal traveling from one surface to another surface of a dielectric layer, or between different surfaces in a multi-layered die package substrate or circuit board. Such a path is typically established by depositing a layer of conductive material onto the inner wall of a via hole. The conductive material applied to the inner wall may be deposited electrically, chemically, or by some other means. Suitable materials include but are not limited to, copper, aluminum, gold, molybdenum, tungsten, other metals, or combinations/alloys of those metals.
- In conventional techniques for making vias, for example on a circuit board comprising a substrate and a metal laminate (i.e. a blanket metal layer), a number of via holes are drilled through the circuit board. Electrical contact between the blanket metal layer and other conductive layers within or on the opposing side of the circuit board is established by application of a thin seed layer of conductive material to the inner wall of each via hole. In a typical process, the seed layer may be copper, applied electrolessly in a plating bath, in such a way that the seed layer is deposited over the entire substrate surface as well as along each via inner wall.
- Following establishment of electrical connection between the conductive layers of a circuit board, a more robust layer of conducting material is applied, typically through electrolytic plating. As was true for application of the seed layer, the plating layer is applied in roughly equal thickness to the inner wall of each via, and to the lateral surface of the circuit board. Thus, upon completion of the plating process, the inner wall of each via carries an accumulated layer of conductive material composed of the nominal seed layer plus the plating layer applied electrolytically. By contrast, the circuit board's lateral surface carries the accumulation of its own blanket layer (i.e. the metal laminate) in addition to the two layers applied to the inner wall of each via. As a result, in conventional techniques for via formation, the circuit board lateral surface carries a thicker conductive layer than that present on the inner wall of each via hole, at the time surface patterning occurs.
- In order to preserve the conductive lining on the walls of each via hole during application of etchant(s) to pattern the surface of the circuit board, each via hole is covered, or plugged, with a mask such as photoresist. For a via hole to be adequately protected, its plug must completely overlap it, and consequently the plug extends to a surface perimeter beyond the boundary established by the via hole. In so doing, it defines an overlay perimeter region, or via pad, in which region the surface conductive layer is protected and retained during the patterning step, and the via pad will thus remain in the final trace pattern on the circuit board.
- The conventional via formation process described results in a via surrounded by a perimeter region of excess conducting material, or a padded via. For each such padded via, the surface area of the pad itself may be responsible for a large percentage, for example more than 60%, of the total lateral surface area occupied by the via (the total lateral space being also referred to as “total via footprint” in the present application).
-
Structure 170A inFIG. 1A illustrates a top view of a single conventional padded via and the resulting surface area occupied by it onsubstrate surface 122 a, which can be a surface of a circuit board or a die package substrate.Distance 180 represents the diameter of the circular area occupied onsubstrate surface 122 a by the circular boundary ofvia hole 102. In some cases, the via hole may be entirely filled with conductive material. In others, as is the case instructure 170A, a portion of the via hole remains unfilled. The conductive material deposited oninner wall 114 of viahole 102 during the seeding and plating processes accumulates to formconductive lining 116, which hasthickness 112. Prior to patterning ofsubstrate surface 122 a on which viahole 102 opens, a plug of patterning mask such as photoresist is applied to overlay viahole 102, as well as to form an extension region beyond viahole 102, leaving a total via footprint withdiameter 190. Following the patterning step,substrate surface 122 a is unmasked to revealconductive tracings 110, and viapad 138 resulting from the extended overlay region masked during patterning, and enclosed byperimeter 118. As stated above, viapad 138 together with viahole 102 result in a padded via with a total via footprint with atotal diameter 190. -
Structure 170B inFIG. 1B illustrates a cross-sectional view of the conventional padded via ofFIG. 1A , comprising viahole 102 and viapad 138.FIG. 1B provides additional perspective on the excess substrate surface area occupied by the pad in a conventional padded via. As in previousFIG. 1A ,distance 180 represents the diameter of viahole 102, a portion of which is filled as a result of the presence ofconductive lining 116 havingthickness 112. Atsubstrate surface 122 a ofsubstrate bulk 122 b,conductive lining 116 defines an inner conductive ring ofthickness 112. Surrounding the inner conductive ring defined byconductive lining 116, viapad 138 defines an outer conductive ring bounded byperimeter 118. Thus, as shown inFIGS. 1A and 1B , viapad 138 occupies a conductive buffer region connectingconductive tracings 110 to the inner conductive ring defined byconductive lining 116. - As stated above, the total substrate surface area occupied by a padded via, that is the sum of the surface area corresponding to the via hole and the area occupied by the via pad, is referred to as the total via footprint in the present application. Thus, the total via footprint of the padded via shown in
FIGS. 1A and 1B is proportional to the square ofdiameter 190. By comparison, the substrate area occupied by viahole 102, including the area occupied by the inner conductive ring defined byconductive lining 116, is proportional to the square ofdiameter 180. In conventional methods of via formation,diameter 180 may be as great as 200 microns, with via pad overlay tolerances as liberal as 75 microns or more, resulting in afootprint diameter 190 of as much as 350 microns or more. Under these circumstances, comparison of the substrate surface area occupied by the total padded via footprint with that occupied by a “padless via,” i.e. a via comprising only viahole 102 withconductive lining 116 and without viapad 138, reveals that only about ⅓ of the total footprint is occupied by viahole 102 andconductive lining 116, while roughly ⅔ of the total footprint is merely due to the presence of viapad 138. Thus, the presence of viapad 138 causes the total via footprint of the conventional padded via to be three times greater than the total via footprint of the same via, if it were padless. -
FIG. 2 showsflow chart 200, which describes the steps, according to one embodiment of the present invention, in the formation of a padless via. Certain details and features have been left out offlow chart 200 that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art. While steps 230 through 270 indicated inflow chart 200 are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown inflow chart 200. - The steps shown in
flow chart 200 are performed on a substrate which initially includesonly substrate surface 322 a andsubstrate bulk 322 b shown inFIG. 3 (whereblanket metal layer 332 is formed after step 230 is completed).Substrate bulk 322 b can comprise, for example, a multi-layer organic laminate such as polytetrafluoroethylene, other organic materials such as FR-4 based laminate, and/or ceramic materials. -
Structure 330 ofFIG. 3 is a cross sectional view of a substrate on whichblanket metal layer 332 is formed onsubstrate surface 322 a according to preliminary step 230 offlow chart 200 inFIG. 2 .Blanket metal layer 332 may comprise copper, and may havethickness 362 of, for example, 12 microns in some embodiments. However,blanket metal layer 332 may comprise other metals and have other thicknesses. - Continuing with
step 240 inFIG. 2 andstructures 440A inFIGS. 4A and 440B inFIG. 4B , via holes are drilled throughblanket metal layer 432 and intosubstrate surface 422 a andsubstrate bulk 422 b.Structure 440A ofFIG. 4A illustrates a top view of a circuit board in which a number of via holes, such as viaholes FIG. 2 . - Referring now to
FIG. 4B ,structure 440B shows a portion ofstructure 440A ofFIG. 4A , including viahole 402 havingdiameter 480. For ease of illustration, other via holes are not shown instructure 440B.Structure 440B thus shows the portion ofsubstrate surface 422 a andsubstrate bulk 422 b which includes viahole 402 having viainner wall 414, and sections ofsubstrate surface 422 a on whichblanket metal layer 432 havingthickness 462 has been formed. - Continuing with step 250 in
FIG. 2 andstructure 550 inFIG. 5 , a seed layer of conductive material, such as copper or a copper alloy, is applied to viainner wall 514 and blanketedsubstrate surface 522 a. For example, the seed layer may be applied electrolessly, through deposition of a metal layer by means of a reducing chemical bath. Alternatively, it is possible to form the seed layer electrolytically in a manner known in the art. Thus,structure 550 representsstructure 440B inFIG. 4B , after application of a seed layer. As shown inFIG. 5 ,seed layer 534 havingthickness 564 has been applied toblanket metal layer 532 and inner viawall 514 of viahole 502. - Continuing with step 260 in
FIG. 2 andstructure 660 inFIG. 6 , differential plating of a conductive material, such as copper or a copper alloy, is performed overseed layer 634 situated overblanket metal layer 632 and viainner wall 614 of viahole 602. In one embodiment, differential plating is achieved through addition of an organic suppressant to an electrolytic plating bath. In one exemplary implementation, a plating differential rate may be adjusted by changing the bias used during the electrolytic plating process. As a result, conductive material is preferentially plated onto the portion of the seed layer situated over viainner wall 614, relative to the portion of the seed layer situated overblanket metal layer 632 such that a thicker layer of the conductive plating material is formed on viainner wall 614 and a thinner layer is formed oversubstrate surface 622 a.Structure 660 inFIG. 6 illustrates viahole 602 after differential plating has occurred according to step 260 offlow chart 200. Thus, platinglayer 636 is formed over bothblanket metal layer 632 and viainner wall 614, butplating layer 636 accumulates an innerwall plating thickness 668 greater thanthickness 666 deposited oversubstrate surface 622 a. It is noted that in one embodiment the differential plating is performed to such a degree and effect that it is akin to anisotropic plating. In other words, differential plating may be performed such that the conductive material is plated in one direction only, i.e. only on viainner wall 614, and not onsubstrate surface 622 a. - Unlike conventional methods for via formation, patterning of
substrate surface 622 a inFIG. 6 proceeds without use of a protective plug overlaying viahole 602. Unprotected patterning may occur during practice of the present invention, without risk of complete removal of platinglayer 636 on viainner wall 614. During unprotected patterning, conductive plated material is completely etched away from unmasked regions of platinglayer 636 situated oversubstrate surface 622 a. However, since platinglayer 636 has agreater thickness 668 over viainner wall 614 thanthickness 666 oversubstrate surface 622 a,thickness 668 of platinglayer 636 over viainner wall 614 is merely reduced during etching, butconductive plating 636 is not eliminated from, and remains on, viainner wall 614, while the accumulatedlayers substrate surface 622 a. In other words, the accumulatedblanket metal layer 632,seed layer 634, andplating layer 636 are completely removed from unprotected regions ofsubstrate surface 622 a. - Continuing with step 270 in
FIG. 2 ,structure 770A ofFIG. 7A illustrates a top view of a region on the circuit board surrounding viahole 702 after patterning has occurred.Structure 770B ofFIG. 7B illustrates the cross-sectional view of viahole 702 corresponding to the top view ofFIG. 7A . Instructures substrate surface 722 a, substrate bulk 722 b,conductive tracings 710,inner wall 714 of viahole 702,conductive lining 716 of viahole 702,distance 780 representing the diameter of viahole 702, andthickness 712 ofconductive lining 716 correspond respectively tosubstrate surface 122 a,substrate bulk 122 b,conductive tracings 110,inner wall 114 of viahole 102,conductive lining 116 of viahole 102,distance 180 representing the diameter of viahole 102, andthickness 112 ofconductive lining 116 ofstructures FIGS. 1A and 1B . Moreover, the inner conductive ring defined byconductive lining 716 of viahole 702 inFIG. 7A corresponds to the inner conductive ring defined byconductive lining 116 of viahole 102 inFIG. 1A . As shown inFIGS. 7A and 7B , due to the absence of viapad 138 ofFIGS. 1A and 1B ,conductive tracings 710 are directly connected toconductive lining 716 of the padless via of the present invention. - Comparison of
exemplary structures structures FIGS. 7A and 7B , viapad 138, that is present in the conventional padded via ofFIGS. 1A and 1B , is entirely eliminated by the present invention. Referring toFIGS. 6 , 7A, and 7B, due to the differential plating technique resulting in platinglayer 636 having agreater thickness 668 over viainner wall 614 thanthickness 666 oversubstrate surface 622 a, platinglayer 636 is not eliminated from viainner wall 614, and remains onconductive lining 716 of viahole 702 in thefinal structures FIGS. 7A and 7B . - Thus, since there is no need for protecting the conductive via
inner wall 614 from being eliminated, protective viapad 138, which was a necessary result of the conventional scheme for protection of the conductive via inner walls, is not needed and does not exist in thefinal structures hole 702. By contrast, the total via footprint in the conventional padded via is expanded by the dimensions of viapad 138 shown inFIG. 1A , which undesirably results in a much greater total via footprint as discussed above. - As described above, the present invention makes possible formation of vias occupying substantially less surface area of a circuit board or a die package substrate than conventional practices allow. In addition, absence of via pads permits greater signal routing flexibility and efficiency on the surface of the circuit board or die package substrate. As a result of the present invention, greater device, component, and/or die densities can be achieved on comparable surface areas. Alternatively, existing device, component, and/or die densities and their corresponding connection densities can be achieved on smaller surfaces, resulting in scalable reductions in packaging size and space, with substantial associated cost savings. Although the invention is described to apply to formation of padless vias in a circuit board, it will be readily apparent to one of ordinary skill in the art how to apply the invention in similar situations, for example to a substrate of an individual die, i.e. to a “die package substrate,” where reductions in surface area consumption and greater routing flexibility are desirable.
- From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skills in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. As such, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.
- Thus, a padless via and method for making same have been described.
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/652,735 US20080169124A1 (en) | 2007-01-12 | 2007-01-12 | Padless via and method for making same |
US14/565,383 US9237651B2 (en) | 2007-01-12 | 2014-12-09 | Padless via |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/652,735 US20080169124A1 (en) | 2007-01-12 | 2007-01-12 | Padless via and method for making same |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US14/565,383 Division US9237651B2 (en) | 2007-01-12 | 2014-12-09 | Padless via |
Publications (1)
Publication Number | Publication Date |
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US20080169124A1 true US20080169124A1 (en) | 2008-07-17 |
Family
ID=39616892
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US11/652,735 Abandoned US20080169124A1 (en) | 2007-01-12 | 2007-01-12 | Padless via and method for making same |
US14/565,383 Expired - Fee Related US9237651B2 (en) | 2007-01-12 | 2014-12-09 | Padless via |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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US14/565,383 Expired - Fee Related US9237651B2 (en) | 2007-01-12 | 2014-12-09 | Padless via |
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US (2) | US20080169124A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090183905A1 (en) * | 2008-01-22 | 2009-07-23 | Conesys, Inc. | Circuit board configuration |
US20160073492A1 (en) * | 2014-09-05 | 2016-03-10 | Inventec (Pudong) Technology Corporation | Method of forming an anti-corrosion protective film |
US9679841B2 (en) | 2014-05-13 | 2017-06-13 | Qualcomm Incorporated | Substrate and method of forming the same |
US10490348B2 (en) * | 2016-06-24 | 2019-11-26 | Qualcomm Incorporated | Two-dimensional structure to form an embedded three-dimensional structure |
US11895772B2 (en) | 2021-06-01 | 2024-02-06 | Unimicron Technology Corp. | Interlayer connective structure of wiring board and method of manufacturing the same |
Families Citing this family (3)
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US9403674B2 (en) * | 2014-08-12 | 2016-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for packaging a microelectromechanical system (MEMS) wafer and application-specific integrated circuit (ASIC) dies using through mold vias (TMVs) |
CN108235568A (en) * | 2018-01-19 | 2018-06-29 | 华南理工大学 | A kind of pcb board by the non-functional PAD of PTH through-holes removal internal layer |
US10727120B2 (en) * | 2018-08-23 | 2020-07-28 | Globalfoundries Inc. | Controlling back-end-of-line dimensions of semiconductor devices |
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US9679841B2 (en) | 2014-05-13 | 2017-06-13 | Qualcomm Incorporated | Substrate and method of forming the same |
US20160073492A1 (en) * | 2014-09-05 | 2016-03-10 | Inventec (Pudong) Technology Corporation | Method of forming an anti-corrosion protective film |
US10490348B2 (en) * | 2016-06-24 | 2019-11-26 | Qualcomm Incorporated | Two-dimensional structure to form an embedded three-dimensional structure |
US11895772B2 (en) | 2021-06-01 | 2024-02-06 | Unimicron Technology Corp. | Interlayer connective structure of wiring board and method of manufacturing the same |
Also Published As
Publication number | Publication date |
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US20150092381A1 (en) | 2015-04-02 |
US9237651B2 (en) | 2016-01-12 |
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