JP6306743B2 - 基板および基板を形成する方法 - Google Patents
基板および基板を形成する方法 Download PDFInfo
- Publication number
- JP6306743B2 JP6306743B2 JP2016567193A JP2016567193A JP6306743B2 JP 6306743 B2 JP6306743 B2 JP 6306743B2 JP 2016567193 A JP2016567193 A JP 2016567193A JP 2016567193 A JP2016567193 A JP 2016567193A JP 6306743 B2 JP6306743 B2 JP 6306743B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric layer
- traces
- photoactive
- insulating
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
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- H10W20/42—
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- H10P72/74—
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- H10W20/056—
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- H10W20/0698—
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- H10W70/05—
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- H10W70/611—
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- H10W70/685—
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- H10P72/7424—
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- H10W70/095—
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- H10W70/635—
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Ceramic Engineering (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/276,763 | 2014-05-13 | ||
| US14/276,763 US9679841B2 (en) | 2014-05-13 | 2014-05-13 | Substrate and method of forming the same |
| PCT/US2015/027806 WO2015175197A1 (en) | 2014-05-13 | 2015-04-27 | Substrate and method of forming the same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017516308A JP2017516308A (ja) | 2017-06-15 |
| JP2017516308A5 JP2017516308A5 (enExample) | 2017-09-14 |
| JP6306743B2 true JP6306743B2 (ja) | 2018-04-04 |
Family
ID=53180818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016567193A Expired - Fee Related JP6306743B2 (ja) | 2014-05-13 | 2015-04-27 | 基板および基板を形成する方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9679841B2 (enExample) |
| EP (1) | EP3143640B1 (enExample) |
| JP (1) | JP6306743B2 (enExample) |
| CN (1) | CN106463447B (enExample) |
| WO (1) | WO2015175197A1 (enExample) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680942B (zh) * | 2016-08-01 | 2019-10-11 | 欣兴电子股份有限公司 | 线路载板及其制作方法 |
| US10340251B2 (en) | 2017-04-26 | 2019-07-02 | Nxp Usa, Inc. | Method for making an electronic component package |
| US10157833B1 (en) | 2017-05-23 | 2018-12-18 | Globalfoundries Inc. | Via and skip via structures |
| US20180350630A1 (en) * | 2017-06-01 | 2018-12-06 | Qualcomm Incorporated | Symmetric embedded trace substrate |
| US10325842B2 (en) * | 2017-09-08 | 2019-06-18 | Advanced Semiconductor Engineering, Inc. | Substrate for packaging a semiconductor device package and a method of manufacturing the same |
| WO2019066813A1 (en) * | 2017-09-27 | 2019-04-04 | Intel Corporation | METHOD, DEVICE AND SYSTEM FOR PROVIDING GRAZED METALLIZATION STRUCTURES |
| US11387187B2 (en) * | 2018-06-28 | 2022-07-12 | Intel Corporation | Embedded very high density (VHD) layer |
| US20200083154A1 (en) | 2018-09-10 | 2020-03-12 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation |
| US10517167B1 (en) * | 2018-10-19 | 2019-12-24 | Eagle Technology, Llc | Systems and methods for providing a high speed interconnect system with reduced crosstalk |
| US10615027B1 (en) | 2018-10-25 | 2020-04-07 | International Business Machines Corporation | Stack viabar structures |
| EP3723459A1 (en) | 2019-04-10 | 2020-10-14 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with high passive intermodulation (pim) performance |
| US11056850B2 (en) | 2019-07-26 | 2021-07-06 | Eagle Technology, Llc | Systems and methods for providing a soldered interface on a printed circuit board having a blind feature |
| US11602800B2 (en) | 2019-10-10 | 2023-03-14 | Eagle Technology, Llc | Systems and methods for providing an interface on a printed circuit board using pin solder enhancement |
| US11283204B1 (en) | 2020-11-19 | 2022-03-22 | Eagle Technology, Llc | Systems and methods for providing a composite connector for high speed interconnect systems |
| US11682607B2 (en) * | 2021-02-01 | 2023-06-20 | Qualcomm Incorporated | Package having a substrate comprising surface interconnects aligned with a surface of the substrate |
| KR20230055561A (ko) | 2021-10-19 | 2023-04-26 | 삼성전기주식회사 | 인쇄회로기판 및 이를 포함하는 전자부품 패키지 |
| US12412822B2 (en) * | 2021-12-31 | 2025-09-09 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor chip and semiconductor package including the same |
| US12035482B2 (en) * | 2022-02-07 | 2024-07-09 | Eagle Technology, Llc | Electronic device with multi-diameter female contacts and related methods |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3949849B2 (ja) * | 1999-07-19 | 2007-07-25 | 日東電工株式会社 | チップサイズパッケージ用インターポーザーの製造方法およびチップサイズパッケージ用インターポーザー |
| JP4701506B2 (ja) * | 2000-09-14 | 2011-06-15 | ソニー株式会社 | 回路ブロック体の製造方法、配線回路装置の製造方法並びに半導体装置の製造方法 |
| JP3861669B2 (ja) | 2001-11-22 | 2006-12-20 | ソニー株式会社 | マルチチップ回路モジュールの製造方法 |
| JP2004039867A (ja) * | 2002-07-03 | 2004-02-05 | Sony Corp | 多層配線回路モジュール及びその製造方法 |
| TW561803B (en) | 2002-10-24 | 2003-11-11 | Advanced Semiconductor Eng | Circuit substrate and manufacturing method thereof |
| TWI295550B (en) * | 2005-12-20 | 2008-04-01 | Phoenix Prec Technology Corp | Structure of circuit board and method for fabricating the same |
| US20080169124A1 (en) | 2007-01-12 | 2008-07-17 | Tonglong Zhang | Padless via and method for making same |
| KR20100065691A (ko) | 2008-12-08 | 2010-06-17 | 삼성전기주식회사 | 금속범프를 갖는 인쇄회로기판 및 그 제조방법 |
| US8187920B2 (en) | 2009-02-20 | 2012-05-29 | Texas Instruments Incorporated | Integrated circuit micro-module |
| US7843056B2 (en) * | 2009-02-20 | 2010-11-30 | National Semiconductor Corporation | Integrated circuit micro-module |
| EP2399288B1 (en) * | 2009-02-20 | 2018-08-15 | National Semiconductor Corporation | Integrated circuit micro-module |
| JP5603600B2 (ja) * | 2010-01-13 | 2014-10-08 | 新光電気工業株式会社 | 配線基板及びその製造方法、並びに半導体パッケージ |
| JP5570855B2 (ja) * | 2010-03-18 | 2014-08-13 | 新光電気工業株式会社 | 配線基板及びその製造方法並びに半導体装置及びその製造方法 |
| US20110272780A1 (en) | 2010-05-05 | 2011-11-10 | Peter Smeys | Method and structure for improving the qualilty factor of rf inductors |
| JP5711472B2 (ja) * | 2010-06-09 | 2015-04-30 | 新光電気工業株式会社 | 配線基板及びその製造方法並びに半導体装置 |
| US8648277B2 (en) | 2011-03-31 | 2014-02-11 | Electro Scientific Industries, Inc. | Laser direct ablation with picosecond laser pulses at high pulse repetition frequencies |
| JP5851211B2 (ja) * | 2011-11-11 | 2016-02-03 | 新光電気工業株式会社 | 半導体パッケージ、半導体パッケージの製造方法及び半導体装置 |
| JP5931547B2 (ja) * | 2012-03-30 | 2016-06-08 | イビデン株式会社 | 配線板及びその製造方法 |
| JP6082233B2 (ja) * | 2012-10-31 | 2017-02-15 | イビデン株式会社 | 配線板及びその製造方法 |
-
2014
- 2014-05-13 US US14/276,763 patent/US9679841B2/en active Active
-
2015
- 2015-04-27 JP JP2016567193A patent/JP6306743B2/ja not_active Expired - Fee Related
- 2015-04-27 WO PCT/US2015/027806 patent/WO2015175197A1/en not_active Ceased
- 2015-04-27 CN CN201580024484.6A patent/CN106463447B/zh not_active Expired - Fee Related
- 2015-04-27 EP EP15722828.9A patent/EP3143640B1/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106463447B (zh) | 2018-06-29 |
| US20150333004A1 (en) | 2015-11-19 |
| JP2017516308A (ja) | 2017-06-15 |
| US9679841B2 (en) | 2017-06-13 |
| EP3143640A1 (en) | 2017-03-22 |
| EP3143640B1 (en) | 2020-01-08 |
| WO2015175197A1 (en) | 2015-11-19 |
| CN106463447A (zh) | 2017-02-22 |
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