JP6306743B2 - 基板および基板を形成する方法 - Google Patents

基板および基板を形成する方法 Download PDF

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Publication number
JP6306743B2
JP6306743B2 JP2016567193A JP2016567193A JP6306743B2 JP 6306743 B2 JP6306743 B2 JP 6306743B2 JP 2016567193 A JP2016567193 A JP 2016567193A JP 2016567193 A JP2016567193 A JP 2016567193A JP 6306743 B2 JP6306743 B2 JP 6306743B2
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Prior art keywords
dielectric layer
traces
photoactive
insulating
semiconductor structure
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Expired - Fee Related
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JP2016567193A
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English (en)
Japanese (ja)
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JP2017516308A (ja
JP2017516308A5 (enExample
Inventor
ホウサム・ワフィク・ジョマ
オマー・ジェームズ・ブチール
クイウォン・カン
チン−クァン・キム
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
JP2016567193A 2014-05-13 2015-04-27 基板および基板を形成する方法 Expired - Fee Related JP6306743B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/276,763 2014-05-13
US14/276,763 US9679841B2 (en) 2014-05-13 2014-05-13 Substrate and method of forming the same
PCT/US2015/027806 WO2015175197A1 (en) 2014-05-13 2015-04-27 Substrate and method of forming the same

Publications (3)

Publication Number Publication Date
JP2017516308A JP2017516308A (ja) 2017-06-15
JP2017516308A5 JP2017516308A5 (enExample) 2017-09-14
JP6306743B2 true JP6306743B2 (ja) 2018-04-04

Family

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JP2016567193A Expired - Fee Related JP6306743B2 (ja) 2014-05-13 2015-04-27 基板および基板を形成する方法

Country Status (5)

Country Link
US (1) US9679841B2 (enExample)
EP (1) EP3143640B1 (enExample)
JP (1) JP6306743B2 (enExample)
CN (1) CN106463447B (enExample)
WO (1) WO2015175197A1 (enExample)

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US10340251B2 (en) 2017-04-26 2019-07-02 Nxp Usa, Inc. Method for making an electronic component package
US10157833B1 (en) * 2017-05-23 2018-12-18 Globalfoundries Inc. Via and skip via structures
US20180350630A1 (en) * 2017-06-01 2018-12-06 Qualcomm Incorporated Symmetric embedded trace substrate
US10325842B2 (en) * 2017-09-08 2019-06-18 Advanced Semiconductor Engineering, Inc. Substrate for packaging a semiconductor device package and a method of manufacturing the same
WO2019066813A1 (en) * 2017-09-27 2019-04-04 Intel Corporation METHOD, DEVICE AND SYSTEM FOR PROVIDING GRAZED METALLIZATION STRUCTURES
US11387187B2 (en) * 2018-06-28 2022-07-12 Intel Corporation Embedded very high density (VHD) layer
US20200083154A1 (en) 2018-09-10 2020-03-12 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation
US10517167B1 (en) * 2018-10-19 2019-12-24 Eagle Technology, Llc Systems and methods for providing a high speed interconnect system with reduced crosstalk
US10615027B1 (en) 2018-10-25 2020-04-07 International Business Machines Corporation Stack viabar structures
EP3723459A1 (en) 2019-04-10 2020-10-14 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with high passive intermodulation (pim) performance
US11056850B2 (en) 2019-07-26 2021-07-06 Eagle Technology, Llc Systems and methods for providing a soldered interface on a printed circuit board having a blind feature
US11602800B2 (en) 2019-10-10 2023-03-14 Eagle Technology, Llc Systems and methods for providing an interface on a printed circuit board using pin solder enhancement
US11283204B1 (en) 2020-11-19 2022-03-22 Eagle Technology, Llc Systems and methods for providing a composite connector for high speed interconnect systems
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate
KR20230055561A (ko) 2021-10-19 2023-04-26 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 전자부품 패키지
US12412822B2 (en) * 2021-12-31 2025-09-09 Samsung Electro-Mechanics Co., Ltd. Semiconductor chip and semiconductor package including the same
US12035482B2 (en) * 2022-02-07 2024-07-09 Eagle Technology, Llc Electronic device with multi-diameter female contacts and related methods

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JP3949849B2 (ja) * 1999-07-19 2007-07-25 日東電工株式会社 チップサイズパッケージ用インターポーザーの製造方法およびチップサイズパッケージ用インターポーザー
JP4701506B2 (ja) * 2000-09-14 2011-06-15 ソニー株式会社 回路ブロック体の製造方法、配線回路装置の製造方法並びに半導体装置の製造方法
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JP5570855B2 (ja) * 2010-03-18 2014-08-13 新光電気工業株式会社 配線基板及びその製造方法並びに半導体装置及びその製造方法
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JP5711472B2 (ja) * 2010-06-09 2015-04-30 新光電気工業株式会社 配線基板及びその製造方法並びに半導体装置
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JP5931547B2 (ja) * 2012-03-30 2016-06-08 イビデン株式会社 配線板及びその製造方法
JP6082233B2 (ja) * 2012-10-31 2017-02-15 イビデン株式会社 配線板及びその製造方法

Also Published As

Publication number Publication date
EP3143640A1 (en) 2017-03-22
CN106463447A (zh) 2017-02-22
US9679841B2 (en) 2017-06-13
WO2015175197A1 (en) 2015-11-19
EP3143640B1 (en) 2020-01-08
JP2017516308A (ja) 2017-06-15
US20150333004A1 (en) 2015-11-19
CN106463447B (zh) 2018-06-29

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