CN106463411A - 场效应晶体管 - Google Patents

场效应晶体管 Download PDF

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CN106463411A
CN106463411A CN201580025928.8A CN201580025928A CN106463411A CN 106463411 A CN106463411 A CN 106463411A CN 201580025928 A CN201580025928 A CN 201580025928A CN 106463411 A CN106463411 A CN 106463411A
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铃木贵光
矶部雅哉
久保胜
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Roma Co Ltd
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Abstract

场效应晶体管(GaN类HFET)包括:栅极电极(13);栅极电极焊盘(16);连接栅极电极(13)的一端部与栅极电极焊盘(16)的第一配线(22);连接栅极电极(13)的另一端部与栅极电极焊盘(16)的第二配线(23);和与第一配线(22)连接,能够调节第一配线(22)的阻抗的电阻元件(17)。

Description

场效应晶体管
技术领域
本发明涉及GaN类的场效应晶体管。
背景技术
现有技术中,作为GaN类的场效应晶体管,具有专利文献1(日本特开2010-186925号公报)中记载的场效应晶体管。该场效应晶体管如图5所示,包括漏极电极51、源极电极52、栅极电极53、栅极电极焊盘54、栅极配线55和电阻元件56。栅极电极53呈指状地设置有多个,与各栅极电极53的一端侧连接的栅极配线55经由电阻元件56与栅极电极焊盘54连接。而且,在将场效应晶体管用作开关器件时,利用电阻元件56抑制振铃现象(ringing)和电涌电压的发生。
另外,现有技术中,作为场效应晶体管,具有专利文献2(日本特公平6-87505号公报)中记载的场效应晶体管。该场效应晶体管如图6所示,包括:呈指状地形成的多个栅极电极61;与各栅极电极61的一端侧连接的栅极引出电极部62;和与该栅极引出电极部62连接的栅极电极焊盘63。在各栅极电极61的栅极引出电极部62侧插入稳定化电阻64。利用该稳定化电阻64实现场效应晶体管的均匀动作。
现有技术文献
专利文献
专利文献1:日本特开2010-186925号公报
专利文献2:日本特公平6-87505号公报
发明要解决的技术问题
但是,专利文献1和专利文献2的场效应晶体管中,仅在栅极电极的一端侧连接栅极电极焊盘。因此,在将场效应晶体管用作开关器件时,会在场效应晶体管产生信号延迟,不能均匀地工作。因此,存在不能充分抑制振铃现象和电涌电压,无法实现场效应晶体管的稳定工作的问题。
发明内容
于是,本发明的目的在于提供一种能够充分抑制振铃现象和电涌电压,能够实现稳定工作的场效应晶体管。
用于解决问题的技术手段
为了解决上述问题,本发明的场效应晶体管包括:具有异质结的GaN类层叠体;以在第一方向上延伸的方式形成在上述GaN类层叠体上的漏极电极;源极电极,其以在上述第一方向上延伸的方式形成在上述GaN类层叠体上,并且形成为在与上述第一方向交叉的第二方向上与上述漏极电极隔开预定的间隔;俯视时形成在上述漏极电极与上述源极电极之间的栅极电极;在上述GaN类层叠体上以覆盖上述栅极电极的方式形成的绝缘层;形成在上述绝缘层上的栅极电极焊盘;连接上述栅极电极的一端部与上述栅极电极焊盘的第一配线;连接上述栅极电极的另一端部与上述栅极电极焊盘的第二配线;和能够调节上述第一配线和上述第二配线中的至少一个配线的阻抗的阻抗调节部。
另外,在一个实施方式的场效应晶体管中,上述阻抗调节部是设置于上述第一配线和上述第二配线中的至少一个配线的电阻元件。
另外,在一个实施方式的场效应晶体管中,上述漏极电极、上述源极电极和上述阻抗调节部由欧姆金属构成。
另外,在一个实施方式的场效应晶体管中,上述阻抗调节部由上述第一配线和上述第二配线中的至少一个配线的一部分构成。
另外,在一个实施方式的场效应晶体管中,上述漏极电极和上述源极电极在上述第二方向上彼此隔开间隔大致平行地交替配置有多个,并且在上述第一方向上呈指状地延伸。
发明效果
根据本发明的场效应晶体管,能够均匀地工作,能够充分抑制振铃现象和电涌电压,并且能够实现场效应晶体管的稳定工作。
附图说明
图1是本发明的第一实施方式GaN类的场效应晶体管的平面示意图。
图2是表示图1的A-A线截面的截面图。
图3是本发明的第二实施方式的GaN类的场效应晶体管的平面示意图。
图4是本发明的第三实施方式的GaN类的场效应晶体管的平面示意图。
图5是现有的GaN类的场效应晶体管的平面示意图。
图6是另一现有的GaN类的场效应晶体管的平面示意图。
具体实施方式
以下,用图示的实施方式对本发明进行详细说明。
(第一实施方式)
图1是本发明的第一实施方式的GaN类HFET(异质结场效应晶体管)的平面示意图。图2是表示图1的A-A线截面的截面图。
如图2所示,本第一实施方式在Si衬底1上依次形成缓冲层2、GaN层3和AlGaN层4。该GaN层3和AlGaN层4构成具有异质结的GaN类层叠体5。在GaN层3与AlGaN层4的界面产生2DEG(二维电子气体)而形成沟道。另外,上述衬底不限于Si衬底,也可以使用蓝宝石衬底或SiC衬底,也可以在蓝宝石衬底或SiC衬底上使GaN类层叠体5生长,也可以如在GaN衬底上使AlGaN层生长等那样,在由氮化物半导体构成的衬底上使GaN类层叠体5生长。另外,也可以不在Si衬底1上形成缓冲层2。
在GaN类层叠体5上依次形成保护膜7和层间绝缘膜8。作为保护膜7的材料,例如此处使用了SiN,但也可以使用SiO2、Al2O3等。另外,作为层间绝缘膜8的材料,例如此处使用了基于CVD的SiO2膜,但也可以使用SOG(Spin On Glass:旋涂玻璃)、BPSG(BoronPhosphorous Silicate Glass:硼磷硅玻璃)等绝缘材料。另外,SiN保护膜7的膜厚,此处作为一例设定为150nm,但也可以在20nm~250nm的范围进行设定。
在保护膜7和层间绝缘膜8形成有贯通保护膜7和层间绝缘膜8到达AlGaN层4的凹槽,在该凹槽形成有漏极欧姆电极11和源极欧姆电极12。漏极欧姆电极11和源极欧姆电极12是由欧姆金属(ohmic metal)构成的欧姆电极,具体而言,是依次层叠有Ti层、Al层、TiN层的Ti/Al/TiN电极。在此,Al膜厚为10nm~300nm。
漏极欧姆电极11经由形成于层间绝缘膜8的导通孔与漏极电极部14连接。源极欧姆电极12经由形成于层间绝缘膜8的导通孔与源极电极部15连接。漏极电极部14和源极电极部15为依次层叠有Ti层、AlCu层、TiN层的Ti/AlCu/TiN电极。在此,AlCu膜厚为1000nm~3000nm。
在漏极欧姆电极11与源极欧姆电极12之间的保护膜7形成有开口。在该开口及其附近形成有栅极绝缘膜9和栅极电极13。层间绝缘膜8覆盖该栅极电极13。在层间绝缘膜8上形成有栅极电极焊盘(未图示)。栅极绝缘膜9为SiN膜。栅极电极13由TiN构成。
如图1所示,漏极欧姆电极11和源极欧姆电极12在第一方向上呈指状地延伸,并且在与上述第一方向大致正交的第二方向上彼此隔开预定的间隔大致平行地交替配置有多个。另外,图1中省略描绘了层间绝缘膜8、漏极电极部14和源极电极部15。
栅极电极13俯视时,在指状的漏极欧姆电极11与指状的源极电极12之间在上述第一方向上延伸,并且以包围漏极欧姆电极11的周围的方式环状地延伸。
栅极电极13的上述第一方向的两端部,分别经由栅极电极连接配线21与栅极电极焊盘16连接。栅极电极焊盘16配置于栅极电极13的上述第一方向的一端侧。栅极电极连接配线21具有第一配线22和第二配线23。栅极电极连接配线21,作为一例,为依次层叠有Ti层、AlCu层、TiN层的Ti/AlCu/TiN电极。
漏极欧姆电极11、包围该漏极欧姆电极11的栅极电极13、第一配线22的一部分和第二配线23的一部分,构成指形栅19。GaN类HFET具有在上述第二方向上配置有多个的指形栅19。
第一配线22与各栅极电极13的上述第一方向的一端部分别连接,并与栅极电极焊盘16连接,将各栅极电极13的一端部与栅极电极焊盘16电连接。在第一配线22连接有作为阻抗调节部的一例的电阻元件17。
第二配线23与各栅极电极13的上述第一方向的另一端部分别连接,并与栅极电极焊盘16连接,将各栅极电极13的另一端部与栅极电极焊盘16电连接。
电阻元件17位于各栅极电极13的一端部与栅极电极焊盘16之间。电阻元件17由欧姆金属构成,具体而言,是与漏极欧姆电极11和源极欧姆电极12同一层的依次层叠有Ti层、Al层、TiN层的Ti/Al/TiN电极。电阻元件17是能够调节电阻值的可变电阻,能够调节包含电阻元件17的第一配线22的阻抗。具体而言,电阻元件17的薄膜电阻值设定成使包含电阻元件17的第一配线22的CR时间常数与第二配线23的CR时间常数大致相同。电阻元件17的薄膜电阻值,例如为栅极电极连接配线21的薄膜电阻值的约10倍。
根据本实施方式的GaN类HFET,电阻元件17构成为能够调节包含电阻元件17的第一配线22的阻抗。因此,利用电阻元件17调节第一配线22对于栅极信号的阻抗,能够使第一配线22的CR时间常数与第二配线23的CR时间常数大致相同。由此,能够防止在GaN类HFET发生信号延迟。
因此,仅通过由电阻元件17来调节第一配线22的阻抗的简单结构,就能够使GaN类HFET均匀地工作,能够充分抑制振铃现象和电涌电压,并且能够实现GaN类HFET的稳定工作。
另外,本实施方式中,漏极欧姆电极11、源极欧姆电极12和电阻元件17由相同的欧姆金属构成,所以能够在相同的工序中形成漏极电极11、源极电极12和电阻元件17。因此,不需要追加用于设置电阻元件17的另外的工序或进行掩模工艺,能够降低制作成本。
另外,本实施方式中,具有上述指状延伸的多个漏极欧姆电极11和源极欧姆电极12。因此,能够在GaN类HFET流动大电流,并且即使流动大电流也能够均匀地工作,能够充分抑制振铃现象和电涌电压,且能够实现GaN类HFET的稳定工作。
(第二实施方式)
图3是上述第二实施方式的GaN类HFET的平面示意图。对于上述第一实施方式不同的点进行说明,本第二实施方式中,在栅极电极连接配线221的第一配线222连接有电阻元件217、217。另外,本第二实施方式中,与上述第一实施方式相同的附图标记,是与上述第一实施方式相同的结构,省略其说明。
如图3所示,栅极电极连接配线221的第一配线222的两端分别经由栅极电极连接配线221的第二配线223的一部分与栅极电极焊盘16连接。在第一配线222的两端部222A、222B分别连接有电阻元件217、217。电阻元件217、217薄膜电阻值设定成使第一配线222的CR时间常数与第二配线223的CR时间常数大致相同。
根据本实施方式的GaN类HFET,第一配线222的一部分和第二配线223的一部分重复。因此,与第一配线222和第二配线223不重复的情况相比,能够进一步缩小第一配线222的CR时间常数与第二配线223的CR时间常数之差,能够更可靠地防止GaN类HFET的信号延迟。因此,能够使GaN类HFET更均匀地工作,能够抑制振铃现象和电涌电压。
(第三实施方式)
图4是上述第三实施方式的GaN类HFET的平面示意图。对与上述第一实施方式不同的点进行说明,本第三实施方式中,在栅极电极连接配线321的第一配线322不连接电阻元件217、217,第一配线322的两端部322A、322B构成阻抗调节部。另外,本第三实施方式中,与上述第一实施方式相同的附图标记,是与上述第一实施方式相同的结构,省略其说明。
如图4所示,栅极电极连接配线321的第一配线322的两端分别与栅极电极连接配线321的第二配线323连接。第一配线322的两端部322A、322B弯折而以蛇行蜿蜒的方式形成。利用这些第一配线322的两端部322A、322B的电阻等进行设定,以使得第一配线322的CR时间常数与第二配线323的CR时间常数大致相同。即,第一配线322的两端部322A、322B构成阻抗调节部317。
根据本实施方式的GaN类HFET,第一配线322的两端部322A、322B构成阻抗调节部317,所以不需要另外设置电阻元件来构成阻抗调节部。因此,不需要追加用于设置电阻元件等的另外的工序、或增大芯片的面积、或进行掩模工艺,所以能够降低GaN类HFET的制作成本。
另外,上述第一~第三实施方式中,具有多个指状的漏极欧姆电极和多个指状的源极欧姆电极,但并不限定于此,也可以具有梳形的漏极欧姆电极和梳形的源极欧姆电极。
另外,上述第一、第二实施方式中,在第一配线22、222连接有电阻元件17、217,但并不限定于此,在第二配线也可以连接电阻元件,也可以不在第一配线连接电阻元件而仅在第二配线连接电阻元件。
另外,上述第三实施方式中,第一配线322的两端部322A、322B构成阻抗调节部317,但并不限定于此,也可以使第二配线的一部分构成阻抗调节部,也可以使第一配线的一部分不构成阻抗调节部而仅使第二配线的一部分构成阻抗调节部。
另外,上述第一、第二实施方式中,在第一配线22、222连接有电阻元件17、217,但并不限定于此,也可以连接电容器等能够调节配线的CR时间常数的受动元件。
另外,上述第一~第三实施方式中,GaN类HFET具有在上述第二方向上配置有多个的指形栅19,但并不限定于此,也可以具有1个指形栅19。
对本发明的优选的实施方式的进行了说明,但本发明并不限定于上述实施方式,能够在本发明的范围内进行各种变更。
对本发明和实施方式进行总结如下。
本发明的场效应晶体管包括:具有异质结的GaN类层叠体5;以在第一方向上延伸的方式形成在上述GaN类层叠体5上的漏极电极11;以在上述第一方向上延伸的方式形成在上述GaN类层叠体5上,并且形成为在与上述第一方向交叉的第二方向上与上述漏极电极11隔开预定的间隔的源极电极12;俯视时形成在上述漏极电极11与上述源极电极12之间的栅极电极13;以覆盖上述栅极电极13的方式形成在上述GaN类层叠体5上的绝缘层8;形成在上述绝缘层8上的栅极电极焊盘16;连接上述栅极电极13的一端部与上述栅极电极焊盘16的第一配线22、222、322;连接上述栅极电极13的另一端部与上述栅极电极焊盘16的第二配线22、222、322;和能够调节上述第一配线22、222、322和上述第二配线23、223、323中的至少一个配线的阻抗的阻抗调节部17、217、317。
根据本发明的场效应晶体管,上述阻抗调节部17、217、317能够调节上述第一配线22、222、322和上述第二配线23、223、323中的至少一个配线的阻抗。因此,利用阻抗调节部17、217、317调节由于第一配线22、222、322和第二配线23、223、323对于栅极信号的阻抗和寄生电容等引起的阻抗,使第一配线22、222、322的阻抗与第二配线23、223、323的阻抗大致相同,能够防止在场效应晶体管发生信号延迟。
因此,场效应晶体管能够均匀地工作,能够充分抑制振铃现象和电涌电压,并且能够实现场效应晶体管的稳定工作。
另外,在一个实施方式的场效应晶体管中,上述阻抗调节部17、217是设置于上述第一配线22、222和上述第二配线23、223中的至少一个配线的电阻元件。
根据上述实施方式,上述阻抗调节部17、217是设置于上述第一配线22、222和上述第二配线23、223中的至少一个配线的电阻元件。因此,能够通过利用该电阻元件使第一配线22、222的阻抗与第二配线23、223的阻抗大致相同的简单的构造来调节阻抗。
另外,在一个实施方式的场效应晶体管中,上述漏极电极11、上述源极电极12和上述阻抗调节部17、217由欧姆金属构成。
根据上述实施方式,上述漏极电极11、上述源极电极12和上述阻抗调节部17、217由欧姆金属构成,所以能够在相同的工序中形成漏极电极11、源极电极12和阻抗调节部17、217。因此,不需要追加用于形成阻抗调节部17、217的另外的工序或进行掩模工艺,能够降低制作成本。
另外,在一个实施方式的场效应晶体管中,上述阻抗调节部317由上述第一配线322和上述第二配线323中的至少一个配线的一部分构成。
根据上述实施方式,上述第一配线322和上述第二配线323中的至少一个配线的一部分构成上述阻抗调节部317。因此,不需要另外设置电阻元件等来作为阻抗调节部。因此,不需要追加用于设置电阻元件等的另外的工序、或增大芯片的面积、或进行掩模工艺,所以能够降低GaN类HFET的制作成本。
另外,在一个实施方式的场效应晶体管中,上述漏极电极11和上述源极电极12在上述第二方向上彼此隔开间隔大致平行地交替配置有多个,并且在上述第一方向上呈指状地延伸。
根据上述实施方式,具有上述呈指状地延伸的多个漏极电极11和源极电极12。因此,能够在场效应晶体管流动大电流,并且即使流过大电流也能够均匀地工作,能够充分抑制振铃现象和电涌电压,能够实现场效应晶体管的稳定工作。
附图标记说明
5 GaN类层叠体
8 层间绝缘膜
11 漏极欧姆电极
12 源极欧姆电极
13 栅极电极
16 栅极电极焊盘
17、217 电阻元件
317 阻抗调节部
22、222、322 第一配线
23、223、323 第二配线。

Claims (5)

1.一种场效应晶体管,其特征在于,包括:
具有异质结的GaN类层叠体(5);
以在第一方向上延伸的方式形成在所述GaN类层叠体(5)上的漏极电极(11);
源极电极(12),其以在所述第一方向上延伸的方式形成在所述GaN类层叠体(5)上,并且形成为在与所述第一方向交叉的第二方向上与所述漏极电极(11)隔开预定的间隔;
俯视时形成在所述漏极电极(11)与所述源极电极(12)之间的栅极电极(13);
在所述GaN类层叠体(5)上以覆盖所述栅极电极(13)的方式形成的绝缘层(8);
形成在所述绝缘层(8)上的栅极电极焊盘(16);
连接所述栅极电极(13)的一端部与所述栅极电极焊盘(16)的第一配线(22、222、322);
连接所述栅极电极(13)的另一端部与所述栅极电极焊盘(16)的第二配线(23、223、323);和
能够调节所述第一配线(22、222、322)和所述第二配线(23、223、323)中的至少一个配线的阻抗的阻抗调节部(17、217、317)。
2.如权利要求1所述的场效应晶体管,其特征在于:
所述阻抗调节部(17、217)是设置于所述第一配线(22、222)和所述第二配线(23、223)中的至少一个配线的电阻元件。
3.如权利要求2所述的场效应晶体管,其特征在于:
所述漏极电极(11)、所述源极电极(12)和所述阻抗调节部(17、217)由欧姆金属构成。
4.如权利要求1所述的场效应晶体管,其特征在于:
所述阻抗调节部(317)由所述第一配线(322)和所述第二配线(323)中的至少一个配线的一部分构成。
5.如权利要求1~4中任一项所述的场效应晶体管,其特征在于:
所述漏极电极(11)和所述源极电极(12)在所述第二方向上彼此隔开间隔大致平行地交替配置有多个,并且在所述第一方向上呈指状地延伸。
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