CN106409966B - 半导体受光元件 - Google Patents
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Abstract
得到一种半导体受光元件,该半导体受光元件能够抑制漏电流、防止受光灵敏度的降低。在半绝缘衬底(1)之上依次层叠有缓冲层(2)、p型接触层(3)、光吸收层(4)、p型电场缓和层(6)、电子倍增层(7)、n型电场缓和层(8)以及n型接触层(10)。缓冲层(2)具有使InP层(2a)和AlxGayIn1‑x‑yAs层(2b)交替地层叠的超晶格,缓冲层(2)不吸收由光吸收层(4)进行吸收的波段的光,其中,0.16≤x≤0.48,0≤y≤0.31。
Description
技术领域
本发明涉及一种半导体受光元件。
背景技术
在用于光通信的高速响应雪崩光电二极管中,将AlInAs用于电子倍增层。其中,近几年还开发了在半绝缘性InP衬底之上依次生长有p型接触层、光吸收层、p型电场缓和层、电子倍增层、以及n型接触层的雪崩光电二极管(例如参照非专利文献1)。这样的构造虽然高速响应的特性优异,但是在半绝缘性InP衬底中包含的Fe和p型接触层中的Zn容易发生相互扩散,因此可能会对设备成品率造成影响(例如参照非专利文献2)。
非专利文献1:Japanese Journal of Applied Physics 51(2012)02BG03
非专利文献2:Journal of Applied Physics 84(1998)8
特别是在衬底之上并列形成有多个二极管的情况下,因为上述的Fe和Zn的相互扩散,所以二极管之间不能充分地分离,存在产生漏电流的问题。为了防止该问题,想到通过在Fe掺杂半绝缘性InP衬底之上作为缓冲层而较厚地生长出未掺杂InP层,从而分离衬底和p型接触层。但是,在InP缓冲层的情况下,不能抑制在外延层与衬底的界面残存的Si等杂质的影响,不能抑制漏电流。另外,由于缓冲层的生长时间变长,因此从材料消耗量等生产性的观点出发并不优选。并且,有时会由缓冲层将入射光吸收,受光灵敏度降低。
发明内容
本发明就是为了解决如上述的课题而提出的,其目的在于得到一种半导体受光元件,该半导体受光元件能够抑制漏电流、防止受光灵敏度的降低。
本发明涉及的半导体受光元件的特征在于,具有:半绝缘性衬底;以及在所述半绝缘性衬底之上依次层叠的缓冲层、p型接触层、光吸收层、p型电场缓和层、电子倍增层、n型电场缓和层以及n型接触层,所述缓冲层具有使InP层和AlxGayIn1-x-yAs层交替地层叠的超晶格,所述缓冲层不吸收由所述光吸收层进行吸收的波段的光,其中,0.16≤x≤0.48,0≤y≤0.31。
发明的效果
在本发明中,缓冲层具有将InP层和AlxGayIn1-x-yAs层(0.16≤x≤0.48,0≤y≤0.31)交替地层叠的超晶格,该缓冲层不吸收由光吸收层进行吸收的波段的光。由此,能够抑制漏电流、防止受光灵敏度的降低。
附图说明
图1是表示本发明的实施方式涉及的半导体受光元件的剖视图。
图2是表示本发明的实施方式涉及的半导体受光元件的衬底和缓冲层的带能(band energy)的图。
图3是表示本发明的实施方式涉及的半导体受光元件的变形例的剖视图。
标号的说明
1Fe掺杂半绝缘性InP衬底,2缓冲层,2a InP层,2b Al0.48In0.52As层,3p型InGaAs接触层,4、4a、4b n-型InGaAs光吸收层,6、6a、6b p型AlInAs电场缓和层,7、7a、7b未掺杂AlInAs雪崩倍增层,8、8a、8b n-型AlInAs电场缓和层,10、10a、10b n型InGaAs接触层
具体实施方式
图1是表示本发明的实施方式涉及的半导体受光元件的剖视图。该半导体受光元件为电子倍增型的雪崩光电二极管100。
在Fe掺杂半绝缘性InP衬底1之上依次层叠有:缓冲层2、p型InGaAs接触层3、n-型InGaAs光吸收层4、n-型AlGaInAs过渡层5、p型AlInAs电场缓和层6、未掺杂AlInAs雪崩倍增层7、n-型AlInAs电场缓和层8、n-型InP窗层9以及n型InGaAs接触层10。在n型InGaAs接触层10之上形成有n电极11。将位于p型InGaAs接触层3的一部分的上方的晶体层去除,在该p型InGaAs接触层3的一部分之上形成有p电极12。
下面,对本实施方式涉及的半导体受光元件的动作进行说明。从外部施加反向偏置电压以使得n电极11侧成为+、p电极12侧成为-,在该状态下,要进行检测的光从Fe掺杂半绝缘性InP衬底1的背面侧射入至半导体受光元件。在这里,如果使作为光通信波段的1.3μm波段或1.5μm波段的近红外区域的光射入,则光在n-型InGaAs光吸收层4处被吸收而产生电子-空穴对,电子移动至n电极11侧,空穴移动至p电极12侧。在反向偏置电压充分高的情况下,在未掺杂AlInAs雪崩倍增层7处电子离子化而生成新的电子-空穴对,与新生成的电子、空穴一起引起进一步的离子化。由此,引起电子和空穴雪崩式地倍增的雪崩倍增。
图2是表示本发明的实施方式涉及的半导体受光元件的衬底和缓冲层的带能的图。本实施方式涉及的缓冲层2是将InP层2a和Al0.48In0.52As层2b交替地反复层叠了10次的超晶格。InP的带隙能量Eg为1.35eV,Al0.48In0.52As的带隙能量Eg为1.42eV。在使InP和AlInAs形成了异质结时,传导带的能量差ΔEc为0.24eV,价电子带的能量差ΔEv为-0.17eV。
下面,对本实施方式涉及的半导体受光元件的制造方法进行说明。各半导体层的生长方法为金属有机气相生长法(MOVPE:Metal Organic Vapor Phase Epitaxy)或分子束外延生长法(MBE:Molecular Beam Epitaxy)等。在这里,使用MOVPE法,将生长温度设为600℃左右。此外,如果各半导体层的生长温度为600~630℃之间,则能够使希望的晶体层进行生长。
首先,在Fe掺杂半绝缘性InP衬底1之上,使厚度0.02~0.05μm的未掺杂InP层2a和厚度0.02~0.05μm的未掺杂AlInAs层2b交替地反复生长10次而形成厚度0.4~1.0μm的缓冲层2。
然后,形成载流子浓度1.0~5×1018cm-3、厚度0.1~0.5μm的p型InGaAs接触层3。然后,形成载流子浓度1~5×1015cm-3、厚度1~2μm的n-型InGaAs光吸收层4。然后,形成载流子浓度1~5×1015cm-3、厚度0.01~0.05μm的n-型AlGaInAs过渡层5。然后,形成进行了碳掺杂的载流子浓度0.5~1×1018cm-3、厚度0.05~0.15μm的p型AlInAs电场缓和层6。
然后,形成厚度0.05~0.1μm的未掺杂AlInAs雪崩倍增层7。然后,形成载流子浓度1~5×1016cm-3、厚度0.1~0.3μm的n-型AlInAs电场缓和层8。然后,形成载流子浓度1~5×1016cm-3、厚度0.1~0.5μm的n-型InP窗层9。然后,形成载流子浓度1~5×1018cm-3、厚度0.3~0.6μm的n型InGaAs接触层10。
然后,将镂空出直径20μm左右的圆形后的SiOx膜作为掩模,仅在n型InGaAs接触层10之上由AuGeNi形成n电极11。然后,去除p型InGaAs接触层3之上的SiOx膜。然后,使用反应性离子蚀刻等手法将位于p型InGaAs接触层3的一部分的上方的晶体层去除,在该p型InGaAs接触层3的一部分之上由AuZn等形成p电极12。最后,研磨Fe掺杂半绝缘性InP衬底1的背面、即与层叠有缓冲层2的面相反的面。通过以上的工序制造本实施方式涉及的半导体受光元件。
如上所述,本实施方式涉及的缓冲层2是使InP层2a和Al0.48In0.52As层2b交替地反复层叠了10次的超晶格。InP层2a与Al0.48In0.52As层2b的传导带的能量差ΔEc对于电子来说成为障壁。并且,在本实施方式中利用将InP层2a和Al0.48In0.52As层2b交替地层叠的超晶格获得传导带能量差ΔEc,从而能够抑制漏电流。
另外,本实施方式涉及的缓冲层2利用由异质结引起的能量差而抑制漏电流,因此与InP单层的缓冲层相比也可以不增加膜厚。从而,缓冲层2的生长时间变短,材料费也变少,因此从生产性的观点出发是优选的。并且,由于AlInAs与InP晶格匹配,因此晶体生长也容易。
另外,AlInAs的带隙充分大于光通信所使用的入射光的能量,因此缓冲层2不吸收由n-型InGaAs光吸收层4进行吸收的波段的光。从而,能够防止由缓冲层2处的光吸收导致的受光灵敏度的降低。
图3是表示本发明的实施方式涉及的半导体受光元件的变形例的剖视图。在该例子中,在相同的Fe掺杂半绝缘性InP衬底1之上并列形成有第一及第二雪崩光电二极管100a、100b。
具体地说,n-型InGaAs光吸收层4a、4b相互分离地形成在p型接触层之上。在n-型InGaAs光吸收层4a之上依次层叠有:n-型AlGaInAs过渡层5a、p型AlInAs电场缓和层6a、未掺杂AlInAs雪崩倍增层7a、n-型AlInAs电场缓和层8a、n-型InP窗层9a以及n型InGaAs接触层10a。在n-型InGaAs光吸收层4b之上依次层叠有:n-型AlGaInAs过渡层5b、p型AlInAs电场缓和层6b、未掺杂AlInAs雪崩倍增层7b、n-型AlInAs电场缓和层8b、n-型InP窗层9b以及n型InGaAs接触层10b。在n型InGaAs接触层10a、10b之上分别形成有n电极11a、11b,在去除了位于上方的晶体层后的p型InGaAs接触层3的一部分之上形成有p电极12a、12b。
n-型InGaAs光吸收层4a、n-型AlGaInAs过渡层5a、p型AlInAs电场缓和层6a、未掺杂AlInAs雪崩倍增层7a、n-型AlInAs电场缓和层8a、n-型InP窗层9a以及n型InGaAs接触层10a构成第一雪崩光电二极管100a。n-型InGaAs光吸收层4b、n-型AlGaInAs过渡层5b、p型AlInAs电场缓和层6b、未掺杂AlInAs雪崩倍增层7b、n-型AlInAs电场缓和层8b、n-型InP窗层9b以及n型InGaAs接触层10b构成第二雪崩光电二极管100b。
在这里,随着响应速度变快,要求并列形成多个二极管而非单体。在现有的结构中,由于在衬底界面残存的杂质的影响,二极管之间不能充分地分离,存在发生漏电流的问题。与此相对,在本实施方式中作为缓冲层2而使用将InP层2a和AlxGayIn1-x-yAs层交替地层叠的超晶格。由此,能够降低在衬底界面残存的杂质的影响,抑制漏电流。
此外,在本实施方式中缓冲层2是包含Al0.48In0.52As层2b的超晶格,但不限于此,能够使用将InP层2a和AlxGayIn1-x-yAs层(0.16≤x≤0.48,0≤y≤0.31)交替地层叠的超晶格作为缓冲层2。
另外,缓冲层2不限于未掺杂,也可以将Fe或Ru等过渡金属作为半绝缘性掺杂剂而进行掺杂。由此,进一步提高抑制电流泄漏的效果。但是,在由于生长装置的制约而难以掺杂过渡金属的情况下,通过调整缓冲层2的AlxGayIn1-x-yAs层的生长时的温度、V族流量而导入氧,也能够期待同样的效果。此时,将缓冲层2的AlxGayIn1-x-yAs层中的氧浓度设为大于或等于1E+15cm-3、小于或等于1E+20cm-3。
Claims (4)
1.一种半导体受光元件,其特征在于,具有:
半绝缘性衬底;以及
在所述半绝缘性衬底之上依次层叠的缓冲层、p型接触层、光吸收层、p型电场缓和层、电子倍增层、n型电场缓和层以及n型接触层,
所述缓冲层具有使厚度0.02~0.05μm的InP层和厚度0.02~0.05μm的AlxGayIn1-x-yAs层交替地层叠的超晶格,所述缓冲层形成相对于电子的障壁,不吸收由所述光吸收层进行吸收的波段的光,其中,0.16≤x≤0.48,0≤y≤0.31。
2.根据权利要求1所述的半导体受光元件,其特征在于,
所述光吸收层具有在所述p型接触层之上相互分离地形成的第一及第二光吸收层,
所述p型电场缓和层具有分别在所述第一及第二光吸收层之上形成的第一及第二p型电场缓和层,
所述电子倍增层具有分别在所述第一及第二p型电场缓和层之上形成的第一及第二电子倍增层,
所述n型电场缓和层具有分别在所述第一及第二电子倍增层之上形成的第一及第二n型电场缓和层,
所述n型接触层具有分别在所述第一及第二n型电场缓和层之上形成的第一及第二n型接触层,
所述第一光吸收层、所述第一p型电场缓和层、所述第一电子倍增层、所述第一n型电场缓和层以及所述第一n型接触层构成第一雪崩光电二极管,
所述第二光吸收层、所述第二p型电场缓和层、所述第二电子倍增层、所述第二n型电场缓和层以及所述第二n型接触层构成第二雪崩光电二极管。
3.根据权利要求1或2所述的半导体受光元件,其特征在于,
所述缓冲层为未掺杂或掺杂有半绝缘性掺杂剂。
4.根据权利要求1或2所述的半导体受光元件,其特征在于,
所述缓冲层的所述AlxGayIn1-x-yAs层中的氧浓度为大于或等于1E+15cm-3、小于或等于1E+20cm-3。
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