CN106252392A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN106252392A
CN106252392A CN201510311866.9A CN201510311866A CN106252392A CN 106252392 A CN106252392 A CN 106252392A CN 201510311866 A CN201510311866 A CN 201510311866A CN 106252392 A CN106252392 A CN 106252392A
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fin structure
fin
epitaxial layer
germanium
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CN106252392B (zh
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童宇诚
刘恩铨
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。该半导体元件的制作方法为，首先提供一基底，该基底上设有至少一鳍状结构，其中鳍状结构包含一上半部以及一下半部。然后形成一栅极结构于鳍状结构上，形成一遮盖层于栅极结构未覆盖的鳍状结构的上半部上方，进行一退火制作工艺将遮盖层内的锗原子趋入鳍状结构的上半部，去除遮盖层，最后再形成一外延层于鳍状结构的上半部周围。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种利用退火制作工艺将锗趋入鳍状结构的方法。
背景技术
随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(drain induced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现有鳍状场效晶体管元件制作工艺中，去除部分鳍状结构后形成凹槽以进行后续外延层成长的标准制作工艺时常因过渡蚀刻鳍状结构而使鳍状结构略低于周围的浅沟隔离，影响后续外延层的成长。因此如何改良现有鳍状场效晶体管制作工艺以改良前述缺点即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例揭露一种制作半导体元件的方法。首先提供一基底，该基底上设有至少一鳍状结构，其中鳍状结构包含一上半部以及一下半部。然后形成一栅极结构于鳍状结构上，形成一遮盖层于栅极结构未覆盖的鳍状结构的上半部上方，进行一退火制作工艺将遮盖层内的锗原子趋入鳍状结构的上半部，去除遮盖层，最后再形成一外延层于鳍状结构的上半部周围。
本发明另一实施例揭露一种制作半导体元件的方法。首先提供一基底，该基底上设有至少一鳍状结构，其中鳍状结构包含一上半部以及一下半部且上半部及下半部包含不同材料。然后进行一湿式清洗改变鳍状结构上半部的形状，之后再形成一第一外延层于鳍状结构上半部周围。
本发明又一实施例揭露一种半导体元件，其包含一基底、至少一鳍状结构设于基底上且包含一上半部与一下半部以及一栅极结构设于基底及鳍状结构上。其中栅极结构所覆盖的鳍状结构与未被栅极结构所覆盖的鳍状结构具有不同形状，且未被栅极结构所覆盖的鳍状结构小于被栅极结构所覆盖的鳍状结构。
附图说明
图1a至图6b为本发明优选实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 浅沟隔离 18 上半部
20 下半部 22 栅极结构
24 间隙壁 26 遮盖层
28 外延层 30 外延层
32 遮盖层
具体实施方式
请参照图1a至图6b，图1a至图6b为本发明优选实施例制作一半导体元件的方法示意图，其中各图示中的右半部分为本发明鳍状结构晶体管的立体结构示意图，左半部分则为右半部分中沿着切线AA'的剖面示意图。如图1a、图1b所示，首先提供一基底12，例如一硅基底或硅覆绝缘(silicon oninsulator, SOI)基板，然后形成至少一鳍状结构14于基底12上，并接着形成一浅沟隔离(shallow trench isolation, STI)16环绕鳍状结构14。在本实施例中，鳍状结构14优选包含一上半部18与一下半部20，其中上半部18与下半部20的交界处优选与浅沟隔离16表面切齐，而且上半部18的底表面或下半部20的上表面等大小且均与浅沟隔离16表面齐平。另外鳍状结构14虽以一根为例，但其数量并不以此为限，可依据产品需求进行调整，例如可形成一根或一根以上的鳍状结构14于基底12上。
依据本发明的优选实施例，鳍状结构14优选通过侧壁图案转移(sidewallimage transfer,SIT)技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构14。另外，鳍状结构14的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构14。这些形成鳍状结构14的实施例均属本发明所涵盖的范围。
接着可于基底12上形成栅极结构22横跨鳍状结构14，在栅极结构22两侧的鳍状结构14中形成轻掺杂漏极(图未示)，形成间隙壁24于栅极结构22侧壁，并于间隙壁24两侧的鳍状结构14中形成源极/漏极区域(图未示)等元件。
如图2a、图2b所示，然后全面性形成一遮盖层26于栅极结构22两侧的鳍状结构14上，其中遮盖层26优选覆盖栅极结构22两侧被暴露的整个鳍状结构14上半部18。在本实施例中，遮盖层26优选为一利用选择性外延成长制作工艺所形成的外延层，例如一由氧化锗(GeO)或锗化硅(SiGe)所构成的外延层，且其会沿特定结晶面进行成长而使遮盖层26的剖面优选呈现如图2a、图2b所示的菱形。需注意的是，此时遮盖层26所覆盖的鳍状结构14上半部18与栅极结构22正下方的鳍状结构14上半部18仍具有相同形状与大小，例如均为矩形。
接着如图3a、图3b所示，进行一退火制作工艺将遮盖层26内的锗原子趋入栅极结构22两侧的鳍状结构14上半部18，使原本为单晶硅结构的鳍状结构14上半部18转变成锗浓度大于50％的锗化硅结构。在本实施例中，退火制作工艺优选将原本具有棱角的矩形剖面的鳍状结构14上半部18顶端以及具有菱形剖面的遮盖层26改变为圆弧状，并同时缩小鳍状结构14上半部18的体积。更具体而言，经由退火制作工艺所缩小的鳍状结构14上半部18与下半部20优选具有不同宽度，例如鳍状结构14上半部18的底表面宽度优选小于鳍状结构14下半部20的上表面宽度。
值得注意的是，由于栅极结构14原本便盖住部分鳍状结构14，因此退火制作工艺仅缩小栅极结构22两侧的鳍状结构14上半部18但不影响到原本设于栅极结构22正下方的部分鳍状结构14上半部18。换句话说，原本鳍状结构14经由退火制作工艺后优选被分隔为两部分，其中设于栅极结构22正下方的鳍状结构14上半部18(亦即通道区域)由于不受退火制作工艺影响优选维持原本具有棱角的矩形且高度不变，栅极结构22两侧的鳍状结构14上半部18(亦即源极/漏极区域)则经由退火制作工艺呈圆弧状且高度降低。
随后如图4a、图4b所示，先去除遮盖层26裸露出栅极结构22两侧的鳍状结构14上半部18，然后选择性形成一外延层28覆盖栅极结构22两侧的鳍状结构14上半部18，其中外延层28可具有约略菱形的剖面包覆住约略椭圆顶部的鳍状结构14上半部18，且外延层28可包含锗化硅。至此可完成本发明一实施例的半导体元件的制作。
此外，如图5a、图5b所示，本发明另一实施例可再接着进行一湿式清洗或湿式蚀刻去除外延层28与部分栅极结构22两侧的鳍状结构14上半部18，由此改变栅极结构22两侧鳍状结构14上半部18的形状，例如将原本具有圆弧状顶部的鳍状结构14上半部18沿特定结晶面进行蚀刻而修整为约略菱形。在本实施例中，湿式清洗或蚀刻所使用的溶液优选选自由氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)、氢氧化钾(potassiumhydroxide,KOH)以及乙二胺-邻苯二酚(ethylenediamine pyrocatechol,EDP)所构成的群组，但不局限于此。
在本实施例中，栅极结构22两侧的鳍状结构14上半部18体积可于清洗的过程中再次被缩小，例如其高度可低于图3a、图3b剖面结构中栅极结构22两侧鳍状结构14上半部的高度，且其宽度可再小于图3a、图3b剖面结构中栅极结构22两侧鳍状结构14上半部18的宽度。另外如同图3a、图3b中栅极结构22两侧鳍状结构14上半部与下半部之间的宽度比例，图5a、图5b中栅极结构22两侧鳍状结构14上半部18与下半部20同样具有不同宽度，例如鳍状结构14上半部18的底表面宽度优选小于鳍状结构14下半部20的上表面宽度。
需注意的是，本实施例虽于去除遮盖层26后先于鳍状结构14上半部18形成一外延层28再进行湿式清洗，但又可选择省略形成外延层28的步骤，直接于去除遮盖层26后对栅极结构22两侧的鳍状结构14上半部18进行清洗制作工艺来改变鳍状结构14的形状，此实施例也属本发明所涵盖的范围。
如图6a、图6b所示，接着形成一外延层30于栅极结构22两侧的鳍状结构14的上半部18周围，其中外延层30优选与原本栅极结构22两侧的鳍状结构14上半部18同为菱形。在本实施例中，外延层30优选包含锗，且其锗浓度优选高于栅极结构22两侧鳍状结构14上半部18的锗浓度。另外，在形成外延层30时，可同时(in-situ)掺杂硼作为源极/漏极区域，而栅极结构22两侧的鳍状结构14上半部18则优选不包含硼。之后可再形成一由外延所构成的遮盖层32环绕外延层30，其中遮盖层32同样包含锗且其锗浓度又高于外延层30的锗浓度，另外可再选择性形成一由硅所构成的另一遮盖层(图未示)于遮盖层32外围，此实施例也属本发明所涵盖的范围。
此外，在形成外延层30之后又可选择性再进行一掺杂制作工艺以及一退火制作工艺以形成源极/漏极区域。换句话说，本发明总共可于三个时间点形成源极/漏极区域，包括可于图2a、图2b形成遮盖层26之前以离子注入形成源极/漏极区域，在图6a、图6b形成外延层30的时候以掺杂硼的方式形成源极/漏极区域，或形成外延层30之后以另一掺杂制作工艺形成源极/漏极区域。其中本发明可于上述三个时间点的任何一者或任何组合来形成源极/漏极区域，且可于各离子注入或掺杂制作工艺后分别搭配进行一退火制作工艺形成源极/漏极区域，这些实施例均属本发明所涵盖的范围。至此即完成本发明优选实施例的半导体元件的制作。
请再参照图5a、图5b，图5a、图5b另揭露一种半导体元件结构。如图中所示，本发明的半导体元件包含一基底12、至少一鳍状结构14设于基底12上、一栅极结构22设于基底12上并横跨鳍状结构14以及一浅沟隔离16设于鳍状结构14周围、一外延层30设于栅极结构22两侧的鳍状结构14上半部18周围以及一遮盖层32覆盖于外延层30表面。
在本实施例中，栅极结构22两侧的鳍状结构14上半部18与下半部20优选包含不同材料，例如上半部18优选包含锗而下半部20则由纯硅所构成。更具体而言，栅极结构22两侧鳍状结构14上半部18的锗浓度大于50％，外延层30的锗浓度优选高于栅极结构22两侧鳍状结构14上半部18的锗浓度，遮盖层32的锗浓度又高于外延层30的锗浓度，且外延层30包含硼而栅极结构22两侧的鳍状结构14上半部18则不包含任何硼。
以结构形状来看，栅极结构22正下方或其所覆盖的鳍状结构14上半部18优选为矩形，栅极结构22两侧的鳍状结构14上半部18则为菱形，外延层30与遮盖层32也优选为菱形，且栅极结构22两侧的鳍状结构14上半部18高度优选小于鳍状结构14下半部20高度的二分之一。从细部来看，栅极结构22正下方或其所覆盖的鳍状结构14上半部18与下半部20优选具有相同宽度，栅极结构22两侧的鳍状结构14上半部18与下半部20则具有不同宽度，例如栅极结构22两侧的鳍状结构14上半部18的底表面宽度优选小于鳍状结构14下半部20的上表面宽度，但无论鳍状结构14上半部18底表面或鳍状结构14下半部20上表面均与浅沟隔离16上表面齐平。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上设有至少一鳍状结构，其中该鳍状结构包含一上半部以及一下半部；
形成一栅极结构于该鳍状结构上；
形成一遮盖层于该栅极结构未覆盖的该鳍状结构的该上半部上方；
进行一退火制作工艺将该遮盖层内的锗原子趋入该鳍状结构的该上半部；
去除该遮盖层；以及
形成一外延层于该鳍状结构的该上半部周围。
2.如权利要求1所述的方法，其中该遮盖层包含氧化锗或锗化硅。
3.如权利要求1所述的方法，其中该鳍状结构的该上半部包含锗。
4.如权利要求3所述的方法，其中该外延层包含锗。
5.如权利要求4所述的方法，其中该外延层的锗浓度高于该鳍状结构的该上半部的锗浓度。
6.一种制作半导体元件的方法，包含：
提供一基底，该基底上设有至少一鳍状结构，其中该鳍状结构包含一上半部以及一下半部且该上半部及该下半部包含不同材料；
进行一湿式清洗以改变该鳍状结构的该上半部的形状；以及
形成一第一外延层于该鳍状结构的该上半部周围。
7.如权利要求6所述的方法，还包含于进行该湿式清洗之前形成一第二外延层于该鳍状结构的该上半部上方。
8.如权利要求6所述的方法，还包含进行该湿式清洗以将该鳍状结构的该上半部的形状转变为菱形。
9.如权利要求6所述的方法，其中该第一外延层包含一菱形。
10.如权利要求6所述的方法，其中该鳍状结构的该上半部包含锗。
11.如权利要求10所述的方法，其中该第一外延层包含锗。
12.如权利要求11所述的方法，其中该第一外延层的锗浓度高于该鳍状结构的该上半部的锗浓度。
13.一种半导体元件，包含：
基底；
至少一鳍状结构设于该基底上，该鳍状结构包含一上半部以及一下半部；以及
栅极结构设于该基底及该鳍状结构上，其中该栅极结构所覆盖的该鳍状结构与未被该栅极结构所覆盖的该鳍状结构具有不同形状，且未被该栅极结构所覆盖的该鳍状结构小于被该栅极结构所覆盖的该鳍状结构。
14.如权利要求13所述的半导体元件，其中该鳍状结构的该上半部包含锗。
15.如权利要求13所述的半导体元件，其中该上半部及该下半部包含不同材料且该上半部为菱形。
16.如权利要求14所述的半导体元件，还包含一外延层设于该鳍状结构的该上半部周围，其中该外延层的锗浓度高于该鳍状结构的该上半部的锗浓度。
17.如权利要求16所述的半导体元件，其中该外延层包含硼且该鳍状结构的该上半部不包含硼。
18.如权利要求16所述的半导体元件，还包含一遮盖层设于该外延层周围。
19.如权利要求13所述的半导体元件，还包含一浅沟隔离设于该鳍状结构周围，且该鳍状结构的该上半部的底表面与该浅沟隔离的上表面齐平。
20.如权利要求13所述的半导体元件，其中该鳍状结构的该上半部的高度小于该鳍状结构的该下半部的高度的二分之一。
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