CN106158935A - 垂直晶体管及其制造方法 - Google Patents
垂直晶体管及其制造方法 Download PDFInfo
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- CN106158935A CN106158935A CN201510147785.XA CN201510147785A CN106158935A CN 106158935 A CN106158935 A CN 106158935A CN 201510147785 A CN201510147785 A CN 201510147785A CN 106158935 A CN106158935 A CN 106158935A
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- raceway groove
- vertical transistor
- grid
- channel
- drain electrode
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
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- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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Abstract
垂直晶体管包括源极-沟道-漏极结构、栅极和栅极介电层。源极-沟道-漏极结构包括源极、源极上方的漏极和介于源极和漏极之间的沟道。栅极围绕沟道的一部分。当垂直晶体管是n沟道垂直晶体管时,栅极被配置成提供基本沿着沟道的延伸方向的压缩应变,或当垂直晶体管是p沟道垂直晶体管时,栅极被配置成提供基本沿着沟道的延伸方向的拉伸应变。在一些实施例中,垂直晶体管还包括ILD,当垂直晶体管是n沟道垂直晶体管时,ILD被配置成提供基本沿着沟道的延伸方向的拉伸应变,或者当垂直晶体管是p沟道垂直晶体管时,ILD被配置成提供基本沿着沟道的延伸方向的压缩应变。本发明还提供了垂直晶体管的制造方法。
Description
技术领域
本发明一般地涉及半导体技术领域,更具体地涉及晶体管及其制造方法。
背景技术
晶体管主要包括源极、漏极、介于两者之间的沟道以及栅极。众所周知,根据施加给栅极的电压,在沟道内选择性地发生导电或防止导电。载流子迁移率是保持晶体管的足够性能的主要因素,其在施加给栅极的电压的控制下会影响沟道中流动的电流或电荷量。
具有低载流子迁移率的晶体管不仅会降低开关速度还会减小“导通”电阻与“截止”电阻之间的差值。因此,将继续寻找提高沟道的载流子迁移率的方法。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种垂直晶体管,包括:源极-沟道-漏极结构,包括源极、位于所述源极上方漏极和介于所述源极和所述漏极之间的沟道;栅极,围绕所述沟道的一部分,当所述垂直晶体管是n沟道垂直晶体管时,所述栅极被配置成提供基本沿着所述沟道的延伸方向的压缩应变,或当所述垂直晶体管是p沟道垂直晶体管时,所述栅极被配置成提供基本沿着所述沟道的所述延伸方向的拉伸应变;以及栅极介电层,介于所述沟道和所述栅极之间。
在该垂直晶体管中,被配置成提供基本沿着所述沟道的所述延伸方向的所述压缩应变的所述栅极包括钛铝(TiAl)、碳化钛铝(TiAlC)或它们的组合。
在该垂直晶体管中,被配置成提供基本沿着所述沟道的所述延伸方向的所述拉伸应变的所述栅极包括钨(W)。
该垂直晶体管还包括层间介电层(ILD),位于所述栅极上方,与所述栅极介电层相接触并且围绕所述沟道的另一部分,并且当所述垂直晶体管是所述n沟道垂直晶体管时,所述ILD被配置成提供基本沿着所述沟道的所述延伸方向的拉伸应变,或当所述垂直晶体管是所述p沟道垂直晶体管时,所述ILD被配置成提供基本沿着所述沟道的所述延伸方向的压缩应变。
在该垂直晶体管中,所述漏极的宽度大于所述沟道的宽度。
在该垂直晶体管中,所述垂直晶体管包括彼此基本平行的多个所述源极-沟道-漏极结构。
根据本发明的另一方面,提供了一种垂直晶体管,包括:源极-沟道-漏极结构,包括源极、位于所述源极上方漏极和介于所述源极和所述漏极之间的沟道;栅极,围绕所述沟道的一部分;栅极介电层,位于所述沟道和所述栅极之间;以及ILD,位于所述栅极上方,与所述栅极介电层相接触并围绕所述沟道的另一部分,当所述垂直晶体管是n沟道垂直晶体管时,所述ILD被配置成提供基本沿着所述沟道的延伸方向的拉伸应变,或当所述垂直晶体管是p沟道垂直晶体管时,所述ILD被配置成提供基本沿着所述沟道的延伸方向的压缩应变。
在该垂直晶体管中,所述漏极的宽度大于所述沟道的宽度。
在该垂直晶体管中,所述漏极的宽度大于所述漏极的底面宽度。
在该垂直晶体管中,所述漏极的宽度和所述漏极的底面宽度之间的宽度差小于或等于约10nm。
在该垂直晶体管中,所述漏极具有底面和围绕所述底面的有角度的侧面,并且所述底面和所述有角度的侧面之间的夹角大于90度且小于180度。
在该垂直晶体管中,所述有角度的侧面的最高点和所述有角度的侧面的最低点之间的高度差小于或等于约30nm。
该垂直晶体管还包括围绕所述漏极的间隔件。
在该垂直晶体管中,所述间隔件的厚度为约2nm至约15nm。
根据本发明的又一方面,提供了一种制造垂直晶体管的方法,包括:形成源极-沟道-漏极结构,其中,所述源极-沟道-漏极结构包括源极、位于所述源极上方的漏极和介于所述源极和所述漏极之间的沟道;形成围绕所述沟道的栅极介电层;
形成围绕所述栅极介电层的一部分的栅极;以及
形成ILD,所述ILD在所述栅极上方,围绕并接触所述栅极介电层的另一部分,
其中,所述栅极和所述ILD被配置成单独地或共同地提供基本沿着所述沟道的延伸方向的应变。
该方法还包括在形成围绕所述沟道的所述栅极介电层之前,形成覆盖所述漏极的间隔件。
该方法还包括当形成围绕所述沟道的所述栅极介电层时,使所述沟道变窄。
该方法还包括当形成围绕所述沟道的所述栅极介电层时,缩小所述漏极的底部。
在该方法中,当所述垂直晶体管是n沟道垂直晶体管时,所述栅极被配置成提供压缩应变,或所述ILD被配置成提供拉伸应变,或所述栅极和所述ILD被配置成分别提供所述压缩应变和所述拉伸应变。
在该方法中,当所述垂直晶体管是p沟道垂直晶体管时,所述栅极被配置成提供拉伸应变,或所述ILD被配置成提供压缩应变,或所述栅极和所述ILD被配置成分别提供所述拉伸应变和所述压缩应变。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的各方面。应该强调的是,根据工业中的标准实践,没有按比例绘制各种部件。实际上,为了清楚地讨论,可以任意地增加或减小各种部件的尺寸。
图1是根据本发明的一些实施例的n沟道垂直晶体管的截面图。
图2是根据本发明的一些实施例的n沟道垂直晶体管的截面图。
图3是根据本发明的一些实施例的p沟道垂直晶体管的截面图。
图4是根据本发明的一些实施例的p沟道垂直晶体管的截面图。
图5A至图5Q是根据本发明的一些实施例的处于制造n沟道垂直晶体管和p沟道垂直晶体管的各种阶段的截面图。
具体实施方式
以下公开内容提供了许多不同实施例或实例,用于实现所提供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然,这些仅是实例并且不旨在限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的,并且其本身不表示所述多个实施例和/或配置之间的关系。
此外,为了便于描述,本文中可使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语,以描述如图中所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外,空间关系术语旨在包括使用或操作过程中的器件的不同的方位。装置可以以其他方式定位(旋转90度或在其他方位),并且在本文中使用的空间关系描述符可同样地进行相应地解释。
本发明提供了具有应变增强的垂直晶体管,可通过栅极、层间介电层(ILD)或它们的组合提供该应变增强,从而有效地提高载流子(例如,电子或空穴)迁移率。下文将顺序地详细描述垂直晶体管及其制造方法的实施例。
图1是根据本发明的一些实施例的n沟道垂直晶体管的截面图。N沟道垂直晶体管包括源极-沟道-漏极结构、栅极G1和栅极介电层140。源极-沟道-漏极结构包括源极S1、漏极D1以及介于源极S1和漏极D1之间的沟道C1。在一些实施例中,源极-沟道-漏极结构是纳米线。在一些实施例中,在俯视图中,源极-沟道-漏极结构具有圆形、矩形、椭圆形或其他形状。在一些实施例中,n沟道垂直晶体管包括彼此基本平行的多个源极-沟道-漏极结构。源极-沟道-漏极结构的源极可彼此耦接或连接,和/或其漏极可彼此耦接或连接。
在一些实施例中,源极S1位于衬底(未示出)上方。在一些实施例中,衬底包括元素半导体,包括单晶硅、多晶硅或单晶锗、多晶锗、或非晶结构;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和GaInAsP;任意其他合适的材料或它们的组合。在一些实施例中,源极S1是n型重掺杂层。在一些实施例中,源极S1包括n型掺杂剂,诸如,磷、砷、锑、铋、硒、碲;其他合适的n型掺杂剂或它们的组合。在一些实施例中,源极S1的掺杂浓度在约1019离子/立方厘米(irons/cm3)至约1022离子/立方厘米的范围内。在一些实施例中,衬底包括阱区(未示出),该阱区的导电类型不同于源极S1的导电类型,并且从衬底的上表面延伸到衬底中。在一些实施例中,源极S1位于阱区上并与其相接触。在一些实施例中,阱区是p型阱区。
漏极D1位于源极S1上方。沟道C1介于源极S1和漏极D1之间。在一些实施例中,漏极D1是n型重掺杂层。在一些实施例中,漏极D1包括n型掺杂剂。在一些实施例中,漏极D1的掺杂浓度在约1019离子/立方厘米至约1022离子/立方厘米的范围内。在一些实施例中,沟道是n型轻掺杂层。在一些实施例中,沟道C1包括n型掺杂剂。在一些实施例中,沟道C1的掺杂浓度在约1016离子/立方厘米至约1019离子/立方厘米的范围内。
栅极G1围绕沟道C1的一部分。在其他实施例中,栅极围绕整个沟道。换言之,n沟道垂直晶体管属于垂直全环栅(VGAA)n沟道垂直晶体管。值得注意的是,在一些实施例中,栅极G1被配置成提供基本沿着n沟道C1的延伸方向的压缩应变,因此在n沟道C1中产生拉伸应变,以增加电子迁移率。在一些实施例中,栅极G1被配置成提供基本沿着沟道C1的延伸方向的压缩应变,该栅极包括钛铝(TiAl)、碳化钛铝(TiAlC)、它们的组合或其他合适的材料。在一些实施例,栅极G1提供的压缩应变为约0.5GPa至约3GPa。在一些实施例中,栅极G1的厚度为约2nm至约10nm。
栅极介电层140设置在沟道C1和栅极G1之间。在一些实施例中,栅极介电层140包括介电材料,诸如氧化硅、氮化硅、氮氧化硅、高k材料(例如,氧化铪(HfOx)、氧化锆(ZrOx)或氧化铝(Al2O3))或其他合适的绝缘材料。
在一些实施例中,垂直晶体管还包括ILD 170,该ILD 170位于栅极G1上方,与栅极介电层140相接触并且围绕沟道C1的另一部分。在一些实施例中,ILD 170包括诸如氮化硅、氮氧化硅的介电材料或其他合适的绝缘材料。值得注意的是,在一些实施例中,ILD 170被配置成提供基本沿着n沟道C1的延伸方向的拉伸应变,因此在n沟道C1中产生拉伸应变,以增强电子迁移率。在一些实施例中,在控制功率的情况下使用沉积工艺形成ILD 170,该ILD 170配置成提供拉伸应变。在一些实施例中,ILD 170提供的拉伸应变为约0.5GPa至约2GPa。在一些实施例中,ILD 170的厚度为约3nm至约20nm。
值得注意的是,在一些实施例中,漏极D1宽度DW大于沟道C1的宽度CW,因此为保持由ILD 170提供的拉伸应变提供支撑面(即,有角度的侧面ASS)。因此,由于存在有角度的侧面ASS,所以可增强由ILD 170提供的拉伸应变。在一些实施例中,宽度DW在约10nm至约20nm的范围内。在一些实施例中,宽度CW在约5nm至约15nm的范围内。在一些实施例中,漏极D1的宽度DW大于漏极D1的底面宽度BW。在一些实施例中,介于漏极D1的宽度DW和漏极D1的底面宽度BW之间的宽度差小于或等于约10nm。在一些实施例中,漏极D1具有底面BS和围绕底面BS的有角度的侧面ASS,并且底面BS和有角度的侧面ASS之间的夹角θ大于90度且小于180度。在一些实施例中,夹角θ在约105度至约170度的范围内。在一些实施例中,有角度的侧面ASS的最高点HP和有角度的侧面ASS的最低点LP之间的高度差HD小于或等于约30nm。
在一些实施例中,栅极G1和ILD 170被配置成分别提供压缩应变和拉伸应变,以在n沟道C1中产生更多的拉伸应变,从而进一步增强电子迁移率。然而,在一些实施例中,ILD 170单独提供基本沿着n沟道C1的延伸方向的拉伸应变,该ILD 170也可以增强电子迁移率。在一些实施例中,栅极G1单独提供基本沿着n沟道C1的延伸方向的压缩应变,该栅极也可以增强电子迁移率。
在一些实施例中,垂直晶体管还包括介于源极S1和栅极G1之间的源极介电层110,以电隔离源极S1和栅极G1。在一些实施例中,源极介电层110包括诸如氮化硅、氮氧化硅的介电材料或其他合适的绝缘材料。
在一些实施例中,垂直晶体管还包括介于栅极介电层140和栅极G1之间以及介于源极介电层110和栅极G1之间的高k介电层150。在一些实施例中,高k介电层150包括HfO2、ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO、SrTiO、它们的组合或其他合适的材料。
在一些实施例中,垂直晶体管还包括围绕漏极D1的间隔件132。在一些实施例中,间隔件132包括诸如氧化硅、氮化硅、氮氧化硅的介电材料或其他合适的绝缘材料。在一些实施例中,间隔件132的厚度为约2nm至约15nm。
图2是根据本发明的其他实施例的n沟道垂直晶体管的截面图。图1和图2的实施例之间的差别在于图2的漏极D1具有基本均匀的宽度DW。在一些实施例中,漏极D1为保持由ILD 170提供的拉伸应变提供了支撑面(即,与沟道C1不接触的底面BS)。
图3是根据本发明的一些实施例的p沟道垂直晶体管的截面图。p沟道垂直晶体管包括源极-沟道-漏极结构,包括源极S2、漏极D2、介于两者之间的沟道C2;栅极G2和栅极介电层140。在一些实施例中,源极-沟道-漏极结构是纳米线。在一些实施例中,在俯视图中,源极-沟道-漏极结构具有圆形、矩形、椭圆形或其他形状。在一些实施例中,垂直晶体管包括彼此基本平行的多个源极-沟道-漏极结构。源极-沟道-漏极结构的源极可彼此连接,和/或源极-沟道-漏极结构的漏极可彼此连接。
在一些实施例中,源极S2位于衬底(未示出)上方。在一些实施例中,源极S2是p型重掺杂层。在一些实施例中,源极S2包括p型掺杂剂,诸如,硼、二氟化甲氧硼、或其他合适的p型掺杂剂或它们的组合。在一些实施例中,源极S2的掺杂浓度在约1019离子/立方厘米至约1022离子/立方厘米的范围内。在一些实施例中,衬底包括的阱区(未示出)的导电类型不同于源极S2的导电类型,其从衬底的上表面延伸到衬底中。在一些实施例中,源极S2位于阱区上且与其相接触。在一些实施例中,阱区是n型阱区。
漏极D2位于源极S2上方。沟道C2介于源极S2和漏极D2之间。在一些实施例中,漏极D2是p型重掺杂层。在一些实施例中,漏极D2包括p型掺杂剂。在一些实施例中,漏极D2的掺杂浓度在约1019离子/立方厘米至约1022离子/立方厘米的范围内。在一些实施例中,沟道是p型轻掺杂层。在一些实施例中,沟道C2包括p型掺杂剂。在一些实施例中,沟道C2的掺杂浓度在约1016离子/立方厘米至约1019离子/立方厘米的范围内。
栅极G2围绕沟道C2的一部分。在其他实施例中,栅极围绕整个沟道。值得注意的是,在一些实施例中,栅极G2被配置成提供基本沿着p沟道C2的延伸方向的拉伸应变,因此在p沟道C2中产生压缩应变,从而增强空穴迁移率。在一些实施例中,栅极G2被配置成提供基本沿着沟道C2的延伸方向的拉伸应变,该栅极G2包括钨(W)或其他合适的材料。在一些实施例中,栅极G2提供的拉伸应变为约0.5GPa至约3GPa。在一些实施例中,栅极G2的晶粒尺寸为约5nm至约50nm。在一些实施例中,栅极G2的厚度为约2nm至约50nm。
栅极介电层140介于沟道C2和栅极G2之间。在一些实施例中,栅极介电层140包括诸如氧化硅、氮化硅、氮氧化硅的介电材料或其他合适的绝缘材料。
在一些实施例中,垂直晶体管还包括ILD 180,该ILD 180位于栅极G2上方且与栅极介电层140相接触以及围绕沟道C2的另一个部分。在一些实施例中,ILD 180包括诸如氮化硅、氮氧化硅的介电材料或其他合适的绝缘材料。值得注意的是,在一些实施例中,ILD 180被配置成基本沿着p沟道C2的延伸方向提供压缩应变,因此在p沟道C2中产生压缩应变,从而增强空穴迁移率。在一些实施例中,ILD 180被配置成提供压缩应变,在功率的控制下使用沉积工艺形成该ILD 180。在一些实施例中,ILD 180提供的压缩应变为约0.5GPa至约2GPa。在一些实施例中,ILD 180的厚度为约3nm至约20nm。
在一些实施例中,漏极D2的宽度DW大于沟道C2的宽度CW,因此为保持由ILD 180提供的压缩应变提供支撑面(即,有角度的侧面ASS)。因此,由于存在有角度的侧面ASS,所以可增强由ILD 180提供的压缩应变。漏极D2的尺寸可参照图1的漏极D1示出的尺寸。
在一些实施例中,如图3所示,栅极G2和ILD 180被配置为分别提供拉伸应变和压缩应变,以在p沟道C2中产生更多的压缩应变,从而进一步增强空穴迁移率。然而,在一些实施例中,ILD 180单独提供基本沿着p沟道C2的延伸方向的压缩应变,ILD 180也可增强空穴迁移率。在一些实施例中,栅极G2单独提供基本沿着p沟道C2的延伸方向的拉伸应变,该栅极G2也可增强空穴迁移率。
在一些实施例中,垂直晶体管还包括介于源极S2和栅极G2之间的源极介电层110,以电隔离源极S2和栅极G2。在一些实施例中,垂直晶体管还包括围绕漏极D2的间隔件132。在一些实施例中,间隔件132具有介于约2nm至约15nm之间的厚度。在一些实施例中,垂直晶体管还包括介于栅极介电层140和栅极G2之间以及源极介电层110和栅极G2之间的高k介电层150。
图4是根据本发明的其他实施例的p沟道垂直晶体管的截面图。图3和图4的实施例之间的差别在于图4的漏极D2具有基本均匀的宽度DW。在一些实施例中,漏极D2为保持由ILD 180提供的压缩应变提供支撑面(即,不与沟道C2接触的底面BS)。
图5A至图5Q是根据本发明的一些实施例的处于制造n沟道垂直晶体管和p沟道垂直晶体管的各种阶段的截面图。可以理解,用于制造n沟道垂直晶体管或p沟道垂直晶体管的方法的实施例可包含在以下示出的实施例中。
如图5A所示,形成源极层SL1、SL2;沟道层CL1、CL2;和漏极层DL1、DL2。在实施例中,源极层SL1、SL2形成为彼此横向邻近,沟道层CL1、CL2形成为彼此横向邻近,以及漏极层DL1、DL2形成为彼此横向邻近。在一些实施例中,源极层SL1、沟道层CL1和漏极层CL1是n型,并且源极层SL2、沟道层CL2和漏极层DL2是p型。在其他实施例中,源极层彼此分隔开,沟道层彼此分隔开以及漏极层彼此分隔开。在一些实施例中,通过外延(epi)生长以及使用不同类型的掺杂剂和不同掺杂浓度的掺杂工艺形成源极层SL1、SL2;沟道层CL1、沟道层CL2;和漏极层DL1、DL2。在一些实施例中,使用离子注入和退火工艺形成源极层SL1、SL2;沟道层CL1、CL2;和漏极层DL1、DL2。在一些实施例中,源极层SL1、SL2和漏极层DL1、DL2的每一个的掺杂浓度在约1016离子/立方厘米至约1019离子/立方厘米的范围内。
因此,如图5A所示,硬掩模层HM形成在漏极层DL1、DL2上方。在一些实施例中,使用化学汽相沉积(CVD)工艺、物理汽相沉积(PVD)工艺、旋涂或其他合适的形成工艺形成硬掩模材料,然后使用光刻工艺或其他合适的材料去除工艺图案化形成的硬掩模材料,以形成硬掩模层HM。在一些实施例中,硬掩模层HM由氮化硅、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)或其他合适的材料构成。
如图5A至图5B所示,根据硬掩模层HM图案化图5A的漏极层DL1、DL2;沟道层CL1、CL2;和源极层SL1、SL2,以形成第一源极-沟道-漏极结构SCD1和第二源极-沟道-漏极结构SCD2。第一源极-沟道-漏极结构SCD1包括源极S1、位于源极S1上方的漏极D1和介于这两者之间沟道C1。第二源极-沟道-漏极结构SCD2包括源极S2、位于源极S2上方的漏极D2以及介于两者之间的沟道C2。在一些实施例中,如图5A所示,通过干蚀刻工艺去除通过硬掩模层HM暴露的漏极层DL1、DL2以及其下面的沟道层CL1、CL2和源极层SL1、SL2。在一些实施例中,蚀刻剂包括氟化碳(CxFy)、六氟化硫(SF6)、氧气(O2)、氦(He)、四氯化碳(CxCly)、氩(Ar)或其他合适的蚀刻剂材料。在一些实施例中,第一源极-沟道-漏极结构SCD1和第二源极-沟道-漏极结构SCD2是纳米线。在一些实施例中,纳米线的高度H在约40nm至约100nm的范围内。
如图5C所示,形成源极介电层110、伪介电层120和间隔件层130。源极介电层110被配置成用作源极S1、S2的间隔件。在后续操作中将去除伪介电层120。间隔件层130被配置成在后续操作中形成覆盖漏极D1、D2的间隔件。在一些实施例中,使用CVD工艺、PVD工艺、旋涂工艺或其他合适的形成工艺形成源极介电层110、伪介电层120和间隔件层130的每一个。在一些实施例中,伪介电材料沉积在源极介电层110上方,围绕沟道C1、C2且覆盖漏极D1、D2和硬掩模层HM,然后进行平坦化和回蚀,以形成暴露漏极D1、D2的伪介电层120;随后,毯式形成间隔件层130以覆盖漏极D1、D2和硬掩模层HM。在一些实施例中,源极介电层110和间隔件层130由氮化硅、SiCN、SiOCN或其他合适的材料制成。在一些实施例中,伪介电层120由氧化硅、氮氧化硅或其他合适的材料制成。
如图5C至图5D所示,蚀刻间隔件层130,以形成覆盖漏极D2、D2的侧壁的间隔件132。在一些实施例中,对间隔件层130进行各向异性干蚀刻工艺,以沿着漏极D1、D2的侧壁形成间隔件132。在一些实施例中,间隔件132的厚度为约2nm至约15nm。在一些实施例中,介于源极S1和漏极D1或介于源极S2和漏极D2之间的距离d1在约10nm至约100nm的范围内。
如图5D至图5E所示,去除伪介电层120,以暴露出沟道C1、C2。在一些实施例中,源极介电层110和间隔件132之间的距离d2在约10nm至约100nm的范围内。在一些实施例中,如图5D所示的距离d1等于或略不同于图5E所示的距离d2。
如图5E至图5F所示,围绕沟道C1、C2形成栅极介电层140。在一些实施例中,使用蚀刻工艺、氧化工艺(诸如,湿氧化、干氧化、等离子体氧化)或其他合适的工艺形成栅极介电层140。在一些实施例中,当形成围绕沟道C1、C2的栅极介电层140时,当围绕沟道C1、C2形成栅极介电层140时,图5E的沟道C1、C2横向缩小和变窄,以形成图5F中的沟道C1、C2。在一些实施例中,当围绕沟道C1、C2形成栅极介电层140时,图5E的漏极D1、D2的底部也缩小,以形成图5F中的具有大头部的漏极D1、D2(从截面图角度看)。漏极D1、D2的尺寸可参照上文示出的实施例。
如图5G所示,顺序地毯式形成高k介电层150和栅极层GL1,以覆盖源极介电层110、栅极介电层140和间隔件132。在一些实施例中,使用CVD工艺、ALD(原子层沉积)工艺或其他合适的形成工艺毯式形成高k介电层150。在一些实施例中,栅极层GL1被配置成提供基本沿着n沟道C1的延伸方向的压缩应变,因此在n沟道C1中产生拉伸应变,以增强电子迁移率。在一些实施例中,使用PVD工艺、溅射工艺或其他合适的形成工艺形成栅极层GL1,该栅极层GL1被配置成提供压缩应变。在一些实施例中,配置成提供压缩应变的栅极层GL1包括钛铝(TiAl)、碳化钛铝(TiAlC)、它们的组合或其他合适的材料。在一些实施例中,栅极层GL1的厚度为约2nm至约10nm。
如图5G至图5H所示,形成光刻胶PR1以覆盖漏极D1、沟道C1和源极S1,然后去除漏极D2上方的栅极层GL1。在一些实施例中,通过干蚀刻工艺、湿蚀刻工艺、它们的组合或其他合适的工艺去除位于漏极D2上方栅极层GL1。之后,通过任意合适的工艺去除光刻胶PR1。
如图5I所示,毯式形成栅极层GL2,以覆盖高k介电层150和栅极层GL1。在一些实施例中,栅极层GL2被配置成提供基本沿着p沟道C2的延伸方向的拉伸应变,因此在p沟道C2中产生压缩应变,以增强空穴迁移率。在一些实施例中,使用ALD工艺、CVD工艺、它们的组合或其他合适的工艺形成栅极层GL2,该栅极层GL2被配置成提供拉伸应变。在一些实施例中,被配置成提供拉伸应变的栅极层GL2包括钨(W)或其他合适的材料。在一些实施例中,栅极层GL2的厚度为约2nm至约50nm。
如图5I至图5J所示,形成覆盖漏极D1、D2的光刻胶PR2,然后去除通过光刻胶PR2暴露的栅极层GL2和其下面的栅极层GL1,以隔离源极S1上方的栅极层GL1和源极S2上方栅极层GL2。在一些实施例中,通过干蚀刻工艺、湿蚀刻工艺、它们的组合或其他合适的工艺去除通过光刻胶PR2暴露的栅极层GL2及其下面的栅极层GL1。之后,通过任意合适的工艺去除光刻胶PR2。
如图5K所示,形成钝化层160,以覆盖栅极层GL2。在一些实施例中,使用CVD工艺、PVD工艺、ALD工艺、旋涂工艺或其他合适的形成工艺形成钝化层160。在一些实施例中,钝化层160是多层结构。在一些实施例中,钝化层160包括与栅极层GL2和源极介电层110相接触地毯式形成的第一钝化层(未示出),以及位于第一钝化层上方的第二钝化层(未示出)。在一些实施例中,第一钝化层由氮化硅、氮氧化硅或其他合适的材料制成。在一些实施例中,第二钝化层由氧化硅、氮氧化硅或其他合适的材料制成。
如图5K至图5L所示,对钝化层160、栅极层(GL2、GL1)和高k介电层150进行回蚀,以形成栅极G1、G2以及暴露出栅极介电层140的部分。在一些实施例中,距离d3在约5nm至约25nm的范围内。在一些实施例中,介于间隔件132和栅极G1之间或介于间隔件132和栅极G2之间的距离d4在约5nm至约25nm的范围内。在一些实施例中,在一些实施例中,距离d4为约10nm至约20nm。距离d3等于或略不同于距离d4。在一些实施例中,距离d5在约10nm至约100nm的范围内。在一些实施例中,沟道C1的未被栅极G1围绕的部分和沟道C2的未被栅极G2围绕的部分用作轻掺杂漏极(LDD)部分,以优化源极-漏极电阻(Rsd)并降低短沟道效应(S.C.E.)。
如图5M所示,ILD 170毯式形成在漏极D1、D2;栅极G1、G2;和钝化层160上方。还形成ILD 170以围绕且与栅极介电层140的部分接触。在一些实施例中,ILD 170被配置成提供基本沿着n沟道C1的延伸方向的拉伸应变,因此在n沟道C1中产生拉伸应变,以增强电子迁移率。在一些实施例中,使用CVD工艺、PVD工艺、ALD工艺、旋涂工艺或其他合适的形成工艺形成ILD 170,该ILD 170被配置成提供拉伸应变。在一些实施例中,在功率的控制下使用SiH4和NH3前体通过PECVD工艺形成ILD 170,该ILD 170被配置成提供拉伸应变。在一些实施例中,ILD 170包括诸如氮化硅、氮氧化硅的介电材料或其他合适的绝缘材料。在一些实施例中,ILD170的厚度为约3nm至约20nm。
如图5M至图5N所示,形成光刻胶PR3,以覆盖位于栅极G1和漏极D1上方的ILD 170,并且然后去除位于栅极G2和漏极D2上方的ILD 170。在一些实施例中,通过干蚀刻工艺、湿蚀刻工艺、它们的组合或其他合适的工艺去除ILD 170。之后,通过任意合适的工艺去除光刻胶PR3。
如图5O所示,ILD 180毯式形成在ILD 170、漏极D1、漏极D2和栅极G1、栅极G2上方。形成的ILD 180还围绕且接触栅极介电层140的围绕沟槽C2的部分。在一些实施例中,ILD 180被配置成提供基本沿着p沟道C2的延伸方向的压缩应变,因此在p沟道C2中产生压缩应变,以增强空穴迁移率。在一些实施例中,使用CVD工艺、PVD工艺、ALD工艺、旋涂工艺或其他合适的形成工艺形成ILD 180,该ILD 180被配置成提供压缩应变。在一些实施例中,在功率的控制下使用SiH4和NH3前体通过PECVD工艺形成被配置成提供压缩应变的ILD 180。在一些实施例中,ILD180包括诸如氮化硅、氮氧化硅的介电材料或其他合适的绝缘材料。在一些实施例中,ILD 180的厚度为约3nm至约20nm。
如图5P所示,介电层190形成在ILD 180上方。在一些实施例中,使用CVD工艺、PVD工艺、ALD工艺、旋涂工艺或其他合适的形成工艺形成介电层190。在一些实施例中,介电层190包括诸如氧化硅、氮氧化硅的介电材料或其他合适的绝缘材料。
如图5P至图5Q所示,进行平坦化工艺,以暴露出漏极D1、D2。在一些实施例中,平坦化工艺包括CMP工艺、研磨工艺、蚀刻工艺或其他合适的材料去除工艺。在一些实施例中,在平坦化工艺之后,漏极D1的上表面和漏极D2的上表面与介电层190的上表面共平面。在一些实施例中,在进行平坦化工艺之后,漏极焊盘(未示出)分别形成在漏极D1、D2上方。在一些实施例中,使用任意合适的形成工艺形成漏极焊盘材料,然后使用光刻/蚀刻工艺或其他合适的材料去除工艺对形成的漏极焊盘材料进行图案化,以形成漏极焊盘。在一些实施例中,漏极焊盘包括金属、金属化合物、硅化物或它们的组合。在一些实施例中,金属或金属化合物包括Ti、Ta、W、Al、Cu、Mo、Pt、TiN、TaN、TaC、TaSiN、WN、MoN、MoON、RuO2、TiAl、TiAlN、TaCN、它们的组合或其他合适的材料。在一些实施例中,硅化物包括硅化钴、硅化钛、硅化钨、硅化镍或它们的组合。
参照图5Q,源极S1、沟道C1、漏极D1、栅极G1和栅极介电层140构造成n沟道垂直晶体管。栅极G1和ILD 170可独立地或共同地提供应变,以增强n沟道C1的电子迁移率。具体地,栅极G1可被配置成提供压缩应变,或ILD 170可被配置成提供拉伸应变,或栅极G1和ILD170可被配置成分别提供压缩应变和拉伸应变,以增强n沟道C1的电子迁移率。
在另一方面,源极S2、沟道C2、漏极D2、栅极G2和栅极介电层140构造成p沟道垂直晶体管。栅极G2和ILD 180可独立地或共同地提供应变,以增强p沟道C2的空穴迁移率。具体地,栅极G2可被配置成提供拉伸应变,或ILD 180可被配置成提供压缩应变,或栅极G2和ILD 180可被配置成分别提供拉伸应变和压缩应变,以增强p沟道C2的空穴迁移率。
根据一些实施例,垂直晶体管包括源极-沟道-漏极结构、栅极和栅极介电层。源极-沟道-漏极结构包括源极、位于源极上方的漏极和介于源极和漏极之间的沟道。栅极围绕沟道的一部分。当垂直晶体管是n沟道垂直晶体管时,栅极被配置成提供基本沿着沟道的延伸方向的压缩应变,或当垂直晶体管是p沟道垂直晶体管时,栅极被配置成提供基本沿着沟道的延伸方向的拉伸应变。栅极介电层介于沟道和栅极之间。
根据一些实施例,垂直晶体管包括源极-沟道-漏极结构、栅极、栅极介电层和ILD。源极-沟道-漏极结构包括源极、位于源极上方的漏极和介于源极和漏极之间的沟道。栅极围绕沟道的一部分。沟道介电层介于沟道和栅极之间。ILD位于栅极上方且与栅极介电层相接触并且围绕沟道的另一部分。当垂直晶体管是n沟道垂直晶体管时,ILD被配置成提供基本沿着沟道的延伸方向的拉伸应变,或当垂直晶体管是p沟道垂直晶体管时,ILD被配置成提供基本沿着沟道的延伸方向的压缩应变。
根据一些实施例,提供了一种制造垂直晶体管的方法,该方法包括形成源极-沟道-漏极结构,其中,源极-沟道-漏极结构包括源极、位于源极上方的漏极以及介于源极和漏极之间的沟道。形成栅极介电层,以围绕沟道。形成栅极,以围绕栅极介电层的一部分。ILD形成在栅极上方并且围绕和接触栅极介电层的另一部分。栅极和ILD被配置成单独地或共同地提供基本沿着沟道的延伸方向的应变。
上面论述了若干实施例的部件,使得本领域的技术人员可以更好地理解本发明的各个方面。本领域的普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域的技术人员也应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、更换以及改变。
Claims (10)
1.一种垂直晶体管,包括:
源极-沟道-漏极结构,包括源极、位于所述源极上方漏极和介于所述源极和所述漏极之间的沟道;
栅极,围绕所述沟道的一部分,当所述垂直晶体管是n沟道垂直晶体管时,所述栅极被配置成提供基本沿着所述沟道的延伸方向的压缩应变,或当所述垂直晶体管是p沟道垂直晶体管时,所述栅极被配置成提供基本沿着所述沟道的所述延伸方向的拉伸应变;以及
栅极介电层,介于所述沟道和所述栅极之间。
2.根据权利要求1所述的垂直晶体管,其中,被配置成提供基本沿着所述沟道的所述延伸方向的所述压缩应变的所述栅极包括钛铝(TiAl)、碳化钛铝(TiAlC)或它们的组合。
3.根据权利要求1所述的垂直晶体管,其中,被配置成提供基本沿着所述沟道的所述延伸方向的所述拉伸应变的所述栅极包括钨(W)。
4.根据权利要求1所述的垂直晶体管,还包括层间介电层(ILD),位于所述栅极上方,与所述栅极介电层相接触并且围绕所述沟道的另一部分,并且当所述垂直晶体管是所述n沟道垂直晶体管时,所述ILD被配置成提供基本沿着所述沟道的所述延伸方向的拉伸应变,或当所述垂直晶体管是所述p沟道垂直晶体管时,所述ILD被配置成提供基本沿着所述沟道的所述延伸方向的压缩应变。
5.根据权利要求4所述的垂直晶体管,其中,所述漏极的宽度大于所述沟道的宽度。
6.根据权利要求1所述的垂直晶体管,其中,所述垂直晶体管包括彼此基本平行的多个所述源极-沟道-漏极结构。
7.一种垂直晶体管,包括:
源极-沟道-漏极结构,包括源极、位于所述源极上方漏极和介于所述源极和所述漏极之间的沟道;
栅极,围绕所述沟道的一部分;
栅极介电层,位于所述沟道和所述栅极之间;以及
ILD,位于所述栅极上方,与所述栅极介电层相接触并围绕所述沟道的另一部分,当所述垂直晶体管是n沟道垂直晶体管时,所述ILD被配置成提供基本沿着所述沟道的延伸方向的拉伸应变,或当所述垂直晶体管是p沟道垂直晶体管时,所述ILD被配置成提供基本沿着所述沟道的延伸方向的压缩应变。
8.根据权利要求7所述的垂直晶体管,其中,所述漏极的宽度大于所述沟道的宽度。
9.根据权利要求8所述的垂直晶体管,其中,所述漏极的宽度大于所述漏极的底面宽度。
10.一种制造垂直晶体管的方法,包括:
形成源极-沟道-漏极结构,其中,所述源极-沟道-漏极结构包括源极、位于所述源极上方的漏极和介于所述源极和所述漏极之间的沟道;
形成围绕所述沟道的栅极介电层;
形成围绕所述栅极介电层的一部分的栅极;以及
形成ILD,所述ILD在所述栅极上方,围绕并接触所述栅极介电层的另一部分,
其中,所述栅极和所述ILD被配置成单独地或共同地提供基本沿着所述沟道的延伸方向的应变。
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US20160064541A1 (en) | 2016-03-03 |
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US9911848B2 (en) | 2018-03-06 |
KR20160026613A (ko) | 2016-03-09 |
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