CN106158925B - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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CN106158925B
CN106158925B CN201610206256.7A CN201610206256A CN106158925B CN 106158925 B CN106158925 B CN 106158925B CN 201610206256 A CN201610206256 A CN 201610206256A CN 106158925 B CN106158925 B CN 106158925B
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semiconductor layer
region
trench
epitaxial layer
forming
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CN106158925A (zh
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西村武义
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

本发明提供半导体装置及半导体装置的制造方法。与通过蚀刻设置有沟槽部的半导体层相比，通过使进一步形成在该沟槽部的外延层的杂质浓度降低来缓和沟槽部中的电场集中。在本发明的第一形态中，提供一种半导体装置，具备：第一半导体层，其具有第一导电型的杂质；沟槽部，其设置在第一半导体层的正面侧；以及第二半导体层，其设置在沟槽部的内壁，具有浓度比第一半导体层低的第一导电型的杂质。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及半导体装置及半导体装置的制造方法。
背景技术
以往，通过蚀刻在半导体基板形成沟槽部之后，进一步在该沟槽部形成外延层(例如，参照专利文献1～3)。另外，已知在半导体基板中，在与活性部相邻的周边部设置场氧化膜(例如，专利文献4)，并且在半导体基板设置LOCOS隔离区(例如，专利文献5)。
现有技术文献
专利文献
专利文献1：日本特开2005-32792号公报
专利文献2：日本特开昭59-69943号公报
专利文献3：日本特开2007-329385号公报
专利文献4：日本特开平5-55262号公报
专利文献5：日本特开平1-246844号公报
发明内容
技术问题
然而，在通过蚀刻形成的沟槽部的半导体层和进一步形成在该沟槽部的外延层具有相同程度的杂质浓度的情况下，可能在沟槽的底部发生电场集中。
技术方案
在本发明的第一形态中，提供一种半导体装置，具备：第一半导体层，其具有第一导电型的杂质；沟槽部，其设置在第一半导体层的正面侧；以及第二半导体层，其设置在沟槽部的内壁，且具有浓度比第一半导体层低的第一导电型的杂质。
第一半导体层的杂质浓度可以为4E14cm-3以上且7E16cm-3以下，第二半导体层的杂质浓度可以为3.2E14cm-3以上且4.5E16cm-3以下。
第二半导体层的厚度可以为沟槽部的宽度的27.3％以上且36.4％以下。
第二半导体层可以被设置为到第一半导体层的正面的端部为止。
半导体装置还可以具备氧化物区，其设置在端部的区域中的第二半导体层。
第二半导体层可以具有：低浓度杂质区；以及高浓度杂质区，其形成在比低浓度杂质区更靠近沟槽部的区域，且杂质浓度比低浓度杂质区高。
半导体装置还可以具备：沟槽绝缘膜，其在沟槽部的内部以与第二半导体层接触的方式设置；以及沟槽电极，其在沟槽部的内部以与沟槽绝缘膜接触的方式设置。
在本发明的第二形态中，提供一种半导体装置的制造方法，包括：形成具有第一导电型的杂质的第一半导体层的阶段；在第一半导体层的正面侧形成沟槽部的阶段；以及在沟槽部的内壁形成具有浓度比第一半导体层低的第一导电型的杂质的第二半导体层的阶段。
半导体装置的制造方法还可以包括在形成第二半导体层的阶段之后在第二半导体层的端部的区域形成氧化物区的阶段。
半导体装置的制造方法还可以包括在形成第二半导体层的阶段之后，在形成氧化物区的阶段之前，在第二半导体层的正面侧形成第一绝缘膜的阶段；以及在形成第一绝缘膜的阶段之后，在第一绝缘膜的正面侧形成针对第一绝缘膜具有蚀刻选择性的第二绝缘膜的阶段。在形成氧化物区的阶段中，可以在形成第二绝缘膜的阶段之后部分地去除端部的区域中的第二绝缘膜，在部分地去除了第二绝缘膜的区域形成氧化物区。
应予说明，上述的发明内容未列举本发明的所有特征。另外，这些特征群的再组合也能够成为发明。
附图说明
图1是表示第一实施方式的半导体装置100的上表面的示意图。
图2是表示图1中的II-II的截面的示意图。
图3A是表示形成第一外延层14的阶段的图。
图3B是表示形成氧化硅膜60和光致抗蚀层62的阶段的图。
图3C是表示隔着氧化硅膜60对第一外延层14进行蚀刻的阶段的图。
图3D是表示经过损伤去除阶段而形成沟槽部30的阶段的图。
图3E是表示形成第二外延层20的阶段的图。
图3F是表示按顺序形成氧化硅膜36和氮化硅膜37的阶段的图。
图3G是表示部分去除氮化硅膜37的阶段的图。
图3H是表示形成LOCOS区52的阶段的图。
图3I是表示设置第二导电型阱区46、第一导电型源区48、层间绝缘膜50、源极54和漏极56的阶段的图。
图4是表示第二实施方式的半导体装置200的截面的示意图。
图5是表示第二实施方式的变形例的示意图。
图6是表示在包括端部15的区域82进行反掺杂的阶段的图。
符号说明
10：活性部
12：半导体基板
14：第一外延层
15：端部
16：正面
17：第一外延层
18：低浓度外延层
20：第二外延层
25：沟槽部
27：宽度
30：沟槽部
31：内壁
32：宽度
33：底部
34：厚度
35：宽度
36：氧化硅膜
37：氮化硅膜
38：低浓度杂质区
39：高浓度杂质区
42：沟槽绝缘膜
44：沟槽电极
46：第二导电型阱区
48：第一导电型源区
50：层间绝缘膜
52：LOCOS区
53：FP电极
54：源极
56：漏极
60：氧化硅膜
62：光致抗蚀层
80：周边部
82：区域
100：半导体装置
200：半导体装置
具体实施方式
以下，通过发明的实施方式说明本发明，但以下的实施方式不限定权利要求书的发明。另外，实施方式中说明的特征的全部组合不一定是发明的解决手段所必须的。
图1是表示第一实施方式的半导体装置100的上表面的示意图。本例的半导体装置100是具备活性部10和周边部80的半导体芯片。活性部10是具有MOSFET(Metal OxideSemiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)元件或IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)元件等的区域。周边部80以包围活性部10的方式设置，是具有耐压结构的区域。
图2是表示图1中的II-II的截面的示意图。在本说明书中，将第一外延层14的表面中的设有源极54的一侧的面称为正面，将设有半导体基板12的一侧的面称为背面。同样地，将第二外延层20的表面中的设有源极54的一侧的面称为正面，将设有第一外延层14的一侧的面称为背面。另外，同样地将半导体基板12的表面中的设有第一外延层14的一侧的面称为正面，将设有漏极56的一侧的面称为背面。正面和背面的概念在沟槽部的曲面中也可以类推适用。另外，在本例中，使第一导电型为n型，使第二导电型为p型。然而，在其它例中，也可以使第一导电型为p型，使第二导电型为n型。
本例的半导体装置100是在活性部10具有沟槽栅型的MOSFET，在周边部80具有作为氧化物区的LOCOS(LOCal Oxidation of Silicon：硅的局部氧化)区52和场板电极(以下，记为FP电极53)的半导体装置。本例的半导体基板12是硅基板，但在其它例中也可以是碳化硅(SiC)基板。
半导体装置100具有半导体基板12、作为第一半导体层的第一外延层14和作为第二半导体层的第二外延层20。半导体装置100还具有沟槽部30、沟槽绝缘膜42、沟槽电极44、第二导电型阱区46、第一导电型源区48、层间绝缘膜50、源极54和漏极56。
半导体基板12和第一外延层14均具有第一导电型的杂质。第一外延层14是在半导体基板12的正面侧进行外延生长而成的层，是具有比半导体基板12低的杂质浓度的层。第一外延层14的杂质浓度可以根据半导体装置100的耐压确定。本例的第一外延层14的杂质浓度可以为4E14cm-3以上且7E16cm-3以下。应予说明，E是指10的幂。例如E14是指10的14次方。
由于本例的第一外延层14主要具有硅，所以n型的杂质可以是磷(P)或砷(As)，p型的杂质可以是硼(B)或铝(Al)。应予说明，在第一外延层14由SiC构成的情况下，n型的杂质可以是磷(P)或氮(N)，p型的杂质可以是铝(Al)或硼(B)。
第一外延层14在活性部10的正面侧具有多个沟槽部30。在沟槽部30的内壁31设有第二外延层20，第二外延层20具有浓度比第一外延层14低的第一导电型的杂质。
本例的第二外延层20具有浓度比第一外延层14低的第一导电型的杂质。第二外延层20的杂质浓度可以为3.2E14cm-3～4.5E16cm-3。第二外延层20被设置为到第一外延层14的正面的端部15为止。在端部15的区域82中的第二外延层20设有LOCOS区52。在本说明书中，端部15的区域82是指在周边部80中从端部15向活性部10延伸的具有一定宽度的区域82。
在LOCOS区52的正面设有FP电极53。如果对FP电极53施加比施加到第一外延层14和第二外延层20的电压低的电压，则FP电极53附近的第一外延层14和第二外延层20被耗尽。由此，耗尽层容易从活性部10延伸到周边部80。特别是由于第二外延层20的杂质浓度比第一外延层14低，所以耗尽层容易延伸。由此，在周边部80中耗尽层内部的电场强度被缓和，因此能够提高半导体装置100的耐压。
在沟槽部30的内部，以与第二外延层20接触的方式设有沟槽绝缘膜42，以与沟槽绝缘膜42接触的方式设有沟槽电极44。以下，为了方便，将沟槽绝缘膜42和沟槽电极44统称为沟槽结构。应予说明，层间绝缘膜50防止沟槽电极44与源极54电连接。
第二导电型阱区46设置在各沟槽结构的两侧。第二导电型阱区46被设置为在相邻的沟槽结构之间共用。第一导电型源区48也设置在各沟槽结构的两侧。当为了使半导体装置100处于导通状态而对沟槽电极44施加有适当的正电压时，在与沟槽结构接触的第二导电型阱区46形成反转层。此外，当在源极54与漏极56之间存在适当的电位差时，电流从漏极56经由反转层和第一导电型源区48流向源极54。应予说明，本例的沟槽电极44表示栅极。
在本例中，在沟槽部30中的U字形的内壁31的底部33也设置有第二外延层20。如上所述，第二外延层20的第一导电型的杂质浓度比第一外延层14低。在PN结中，杂质浓度越低耗尽层越容易扩展。由于本例的沟槽部30在底部33具有第二外延层20，所以即使在沟槽部30的底部33，耗尽层也容易扩展。由此，即使在沟槽部30的底部33，耗尽层的电场强度也得到缓和，因此半导体装置100的耐压提高。另外，在沟槽部30的内部，通过以与第二外延层20接触的方式设置有沟槽绝缘膜42，以与沟槽绝缘膜42接触的方式设置沟槽电极44，从而能够具备微细的沟槽结构。
图3A～图3I是表示半导体装置100的制造工序的图。图3A是表示形成第一外延层14的阶段的图。可以将具有平坦的表面的半导体基板12加热到1000℃以上，流通甲硅烷(SiH4)、二硅烷(Si2H6)、二氯硅烷(SiH2Cl2)和三氯硅烷(SiHCl3)等气体而形成4.0μm以上且15μm以下的第一外延层14。应予说明，第一外延层14的厚度因半导体装置100的耐压的不同而异。第一外延层14在吸收半导体基板12的第一导电型杂质的同时生长，但杂质浓度比半导体基板12的杂质浓度低。
图3B是表示形成氧化硅膜60和光致抗蚀层62的阶段的图。图3B是图3A的后续工序。利用等离子体CVD等方法在第一外延层14的整个正面16形成氧化硅膜60。其后，利用光刻工艺将光致抗蚀层62成膜，并进行曝光而形成光致抗蚀层62的图案。其后，通过蚀刻去除没有被光致抗蚀层62覆盖的氧化硅膜60。
图3C是表示隔着氧化硅膜60对第一外延层14进行蚀刻的阶段的图。图3C是图3B的后续工序。通过图3B的工序，在去除了氧化硅膜60的部分中，第一外延层14的正面16露出。将氧化硅膜60作为掩模，对露出的第一外延层14进行蚀刻而形成沟槽部25。在本例中，由于没有将作为有机物的光致抗蚀层62用作沟槽部30的蚀刻用掩模，所以有机物不会进入沟槽部25。由此，能够防止对MOSEFT的沟道特性带来不良影响，例如能够防止有机物扩散到沟槽部内而产生缺陷和/或可动离子，或者漏电流增加、Vth等特性变化、耐受量降低和栅极可靠性降低的发生等不良影响。该阶段的沟槽部25可以具有0.8μm以上且1.2μm以下的宽度27。
图3D是表示经过损伤去除阶段，形成沟槽部30的阶段的图。图3D是图3C的后续工序。在图3C的阶段的沟槽部25存在具有由蚀刻引起的表面粗糙等的损伤层。损伤层会导致沟道区域中的结晶缺陷等，因此不被期望。因此，通过湿式氧化或热氧化在沟槽部25的内部形成牺牲氧化层。其后，通过蚀刻来去除牺牲氧化层。由此结束损伤去除工序，在第一外延层14的正面侧形成沟槽部30。
通过损伤去除工序，沟槽部25的宽度27扩大0.3μm左右。换言之，通过损伤去除工序，沟槽部30的宽度32例如为1.1μm以上且1.5μm以下。
图3E是表示形成第二外延层20的阶段的图。图3E是图3D的后续工序。在本工序中，在第一外延层14的正面16和沟槽部30的内壁31使硅膜外延生长，形成第二外延层20。例如，在图3D的工序中的沟槽部30的宽度32为1.1μm的情况下，外延生长0.3μm左右的硅膜，在图3D的工序中的沟槽部30的宽度32为1.3μm的情况下，外延生长0.4μm左右的硅膜。由此，沟槽部30的宽度35为0.5μm左右。
第二外延层20的形成方法可以与第一外延层14的形成方法(图3A)相同。第二外延层20在吸收第一外延层14的第一导电型杂质的同时进行生长，但杂质浓度比第一外延层14的杂质浓度低。在本例中，即便使用具有1μm的分辨率的通常的曝光装置也能够实现具有与使用0.5μm的分辨率的昂贵的曝光装置同等的沟槽部30的宽度35(在本例中为0.5μm)。
本例的第二外延层20的沟槽部的厚度34和周边部中的厚度34为0.3μm以上且0.4μm以下。换言之，第二外延层20的厚度34为第一外延层14中的沟槽部30的宽度32的27.3(＝0.3μm/1.1μm)％以上且36.4(＝0.4μm/1.3μm)％以下。
图3F是表示按顺序形成氧化硅膜36和氮化硅膜37的阶段的图。图3F是图3E的后续工序。在该工序中，以例如
Figure BDA0000957783050000081
以上且
Figure BDA0000957783050000082
以下的厚度在第二外延层20的正面侧形成作为第一绝缘膜的氧化硅膜36。其后，以例如
Figure BDA0000957783050000083
程度的厚度在氧化硅膜36的正面侧形成作为第二绝缘膜的氮化硅膜37。应予说明，氧化硅膜36和氮化硅膜37例如利用等离子体CVD等方法而设置在第二外延层20的整个面。换言之，氧化硅膜36和氮化硅膜37除了被设置在平坦的周边部80以外，也被设置在活性部10的平坦的区域和沟槽部30。
图3G是表示部分去除氮化硅膜37的阶段的图。图3G是图3F的后续工序。氮化硅膜37对第一绝缘膜具有蚀刻选择性。在该工序中，氧化硅膜36作为对氮化硅膜37的蚀刻阻挡膜发挥作用，因此能够仅部分地去除端部15的区域82中的氮化硅膜37。在本例中，在部分地去除氮化硅膜37后，不去除在区域82露出的氧化硅膜36，但在其它例中也可以使用稀氢氟酸去除氧化硅膜36。
图3H是表示形成LOCOS区52的阶段的图。图3H是图3G的后续工序。氮化硅膜37作为用于在第二外延层20选择性地形成LOCOS区52的掩模发挥作用。通过将第一外延层14暴露在例如800℃以上且1100℃以下程度的气氛中(热氧化法)，从而在部分地去除了氮化硅膜37的端部15的区域82形成LOCOS区52。在LOCOS区52形成后通过蚀刻去除氧化硅膜36和氮化硅膜37。
在本例中，在LOCOS区52的形成(图3H)之前进行沟槽部30的形成(图3B～图3E)。与此相反，在沟槽部30的形成(图3B～图3E)之前进行LOCOS区52的形成(图3H)的情况下，由于LOCOS区52的鸟嘴(Bird's beak)等斜面而产生光刻工艺(图3B)中的驻波效应。如果产生驻波效应，则存在无法形成所希望的光致抗蚀层62的图案的问题。另外，为了防止驻波效应，需要追加另行设置防反射层等的工艺。在本例中，由于在LOCOS区52的形成(图3H)之前进行沟槽部30的形成(图3B～图3E)，所以不受到驻波效应的影响。由此，能够准确地形成具有1μm以下的宽度35的沟槽部30。
应予说明，在形成LOCOS区52的工序中，也考虑到使氧化硅膜堆积来代替热氧化法。但是，这种情况下，为了使氧化硅膜部分地保留在区域82，需要在后续工序中去除堆积在沟槽部30内的氧化硅膜。堆积的氧化硅膜的膜厚比氧化硅膜36和氮化硅膜37厚。因此，在去除堆积的氧化硅膜的情况下，沟槽部30的第二外延层20也被蚀刻，可能失去微细地形成沟槽部30的宽度的优点。因此，在该工序中，优选使用热氧化法。
应予说明，LOCOS区52的活性部10侧的端部可以被设置为从活性部10中的最靠近周边部80的沟槽部30分离30μm以上。然而，在附图中，考虑到观察的容易性，请注意LOCOS区52的活性部10侧的端部与最靠近周边部80的沟槽部30的距离描绘得比实际尺寸更近。
图3I是表示设置第二导电型阱区46、第一导电型源区48、层间绝缘膜50、源极54和漏极56的阶段的图。图3I是图3H的后续工序。在该工序中，利用已知的离子注入法等在第一外延层14和第二外延层20形成多个第二导电型阱区46和第一导电型源区48。
接下来，依次形成沟槽绝缘膜42和沟槽电极44。沟槽绝缘膜42可以是氧化硅膜，沟槽电极44可以是掺杂了杂质的多晶硅。此外，将层间绝缘膜50设置在沟槽结构的表面侧。其后，在活性部10形成源极54，在LOCOS区52的表面侧形成FP电极53，在半导体基板12的背面侧形成漏极56。层间绝缘膜50防止沟槽电极44与源极54电连接。
图4是表示第二实施方式的半导体装置200的截面的示意图。在半导体装置200中，第二外延层20具有低浓度杂质区38和高浓度杂质区39。在这个方面与第一实施方式的半导体装置100不同。其它方面与第一实施方式的半导体装置100相同。低浓度杂质区38是第二外延层20中的位于端部15的区域82的区域。高浓度杂质区39形成在与低浓度杂质区38相比靠近沟槽部30的区域，是杂质浓度比低浓度杂质区38高的区域。
在本例中，通过在第一导电型的第二外延层20反掺杂第二导电型的杂质，从而使低浓度杂质区38的杂质浓度比高浓度杂质区39低。例如，在低浓度杂质区38追加掺杂8.0E13～1.2E16cm-3的第二导电型的杂质。应予说明，在其它例中，可以在第一导电型的第二外延层20的形成后，不在低浓度杂质区38掺杂第一杂质，而在高浓度杂质区39追加掺杂第一杂质，由此设置杂质浓度差。例如，可以在高浓度杂质区39追加掺杂8.0E13～1.2E16cm-3的第一导电型的杂质。追加掺杂的情况下，优选以第一外延层14的杂质浓度降低20％左右的方式形成。
然而，在进行追加掺杂时，需要降低第一外延层14的杂质浓度，因此通态电阻增加。因此，如图5所示，通过在第一外延层17的上表面形成杂质浓度比第一外延层17低的低浓度外延层18，从而能够改善特性。
图5是表示第二实施方式的变形例的示意图。第一外延层17与第一外延层14为相同的浓度，低浓度外延层18比第一外延层17降低20％的杂质浓度。应予说明，低浓度外延层18的杂质浓度可以是与第二外延层20相同的杂质浓度。低浓度外延层18的厚度是在低浓度外延层18内形成沟槽底部33的厚度。此时，也可以不进行对后述的区域82的反掺杂。
由此，与第一实施方式相比，FP电极53附近的第一外延层14和第二外延层20更容易被耗尽化。因此，与第一实施方式相比，耗尽层容易从活性部10延伸到周边部80。
图6是表示在包括端部15的区域82进行反掺杂的阶段的图。该阶段可以处于部分地去除第一实施方式的氮化硅膜37的阶段(图3G)与形成LOCOS区52的阶段(图3H)之间。在本例中，从第一外延层14的正面16侧整面地掺杂第二导电型的杂质。包括端部15的区域82以外的区域，杂质被氮化硅膜37阻挡不侵入到氧化硅膜36。由此，能够仅对包括端部15的区域82掺杂第二导电型的杂质。
以上，利用实施方式说明了本发明，但本发明的技术的范围不限于上述实施方式记载的范围。对上述实施方式进行各种变更或改良对于本领域技术人员而言也是明确的。根据权利要求书的记载可知其进行了各种变更或改良的方式也包括在本发明的技术方案内。
应当注意的是，只要权利要求书、说明书和附图中所示的装置、系统、程序和方法中的动作、顺序、步骤和阶段等各处理的执行顺序并未特别明确“在……之前”，“……以前”等，另外，未在后续处理中使用之前处理的结果，否则都可以按任意顺序实现。方便起见，对权利要求书、说明书和附图中的动作流程使用“首先”，“接下来”等进行说明，也不表示一定要按照该顺序实施。

Claims (9)

1.一种半导体装置，其特征在于，具备：
第一半导体层，其具有第一导电型的杂质；
沟槽部，其设置在所述第一半导体层的正面侧；以及
第二半导体层，其设置在所述沟槽部的内壁，且具有浓度比所述第一半导体层低的第一导电型的杂质，
所述第二半导体层被设置为到所述第一半导体层的正面的端部为止。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第一半导体层的杂质浓度为4E14cm-3以上且7E16cm-3以下，
所述第二半导体层的杂质浓度为3.2E14cm-3以上且4.5E16cm-3以下。
3.根据权利要求1所述的半导体装置，其特征在于，
所述第二半导体层的厚度为所述沟槽部的宽度的27.3％以上且36.4％以下。
4.根据权利要求1所述的半导体装置，其特征在于，还具备：
氧化物区，其设置在所述端部的区域中的所述第二半导体层上。
5.根据权利要求4所述的半导体装置，其特征在于，所述第二半导体层具有：
低浓度杂质区；以及
高浓度杂质区，其形成在比所述低浓度杂质区更靠近所述沟槽部的区域，且杂质浓度比所述低浓度杂质区高。
6.根据权利要求1所述的半导体装置，其特征在于，还具备：
沟槽绝缘膜，其在所述沟槽部的内部以与所述第二半导体层接触的方式设置；以及
沟槽电极，其在所述沟槽部的内部以与所述沟槽绝缘膜接触的方式设置。
7.一种半导体装置的制造方法，其特征在于，包括：
形成具有第一导电型的杂质的第一半导体层的阶段；
在所述第一半导体层的正面侧形成沟槽部的阶段；以及
在所述沟槽部的内壁形成具有浓度比所述第一半导体层低的第一导电型的杂质的第二半导体层的阶段，
所述第二半导体层还被设置为到所述第一半导体层的正面的端部为止。
8.根据权利要求7所述的半导体装置的制造方法，其特征在于，
还具备在形成所述第二半导体层的阶段之后，在所述端部的区域中的所述第二半导体层上形成氧化物区的阶段。
9.根据权利要求8所述的半导体装置的制造方法，其特征在于，
还具备在形成所述第二半导体层的阶段之后，在形成所述氧化物区的阶段之前，在所述第二半导体层的正面侧形成第一绝缘膜的阶段；以及
在形成所述第一绝缘膜的阶段之后，在形成所述氧化物区的阶段之前，在所述第一绝缘膜的正面侧形成针对所述第一绝缘膜具有蚀刻选择性的第二绝缘膜的阶段，
在形成所述氧化物区的阶段中，部分地去除所述端部的区域中的所述第二绝缘膜，在部分地去除了所述第二绝缘膜的区域形成所述氧化物区。
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