CN106158809A - TSOP-48L chip package increases the error-proof structure of identification point - Google Patents
TSOP-48L chip package increases the error-proof structure of identification point Download PDFInfo
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- CN106158809A CN106158809A CN201510208306.0A CN201510208306A CN106158809A CN 106158809 A CN106158809 A CN 106158809A CN 201510208306 A CN201510208306 A CN 201510208306A CN 106158809 A CN106158809 A CN 106158809A
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- lead frame
- pin
- identification point
- tsop
- error
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses TSOP-48L chip package and increase the error-proof structure of identification point, TSOP-48L chip includes lead frame, single IC lead frame slip, crystal grain, die paddle and multiple pin, lead frame is provided with one, single IC lead frame slip is placed in lead frame, crystal grain is placed in single IC lead frame slip, one end of single IC lead frame slip is provided with die paddle, the interval that multiple pins are provided with between 48 multiple pins is identical, and it is symmetrical and width is identical, the first pin edge in multiple pins is along being provided with identification point, identification point is half round cut, the radius of half round cut is 0.15mm；Technique scheme is to add identification point PIN1 by the first pin in multiple pins, so that be easy to during encapsulation identify, be difficult to misplace position, improve work efficiency, saved the time, serve good foolproof function.
Description
Technical field
The invention belongs to integrated antenna package technical field, disclosing TSOP-48L chip package increases the error-proof structure of identification point.
Background technology
Currently, lead frame (lead frame is also copper conductor frame) is widely used in IC encapsulation and manufactures, and the many uses of pin product are drawn
Wire frame realizes wafer circuit function as input and output conductive channel, TSOP-48L be use lead frame packing forms
In one, this be packaged with 48 pins for the multiple encapsulation such as external circuit communication, also TSOP-54L, TSOP-66L
Form is all to use leadframe package.Lead frame used by industry all makes the lead frame sheet of upper EDS maps multiple IC unit at present
Bar.And existing lead frame is distributed multiple TSOP-48L IC lead frame unit, the pin at every two ends is all symmetrical,
So direction the most easy to identify when packaging operation, even if direction puts back and is not easy to be noticeable during board feeding, the die bond of wafer die
It is directional requirement that technique is placed, if lead frame enters die bond track front to by tune turnback, crystal grain storing angle
Will result in below bonding wire cannot operation and scrap.
Summary of the invention
In order to solve the problems of the prior art, the invention discloses and add identification point by the first pin in multiple pins
PIN1, so that be easy to during encapsulation identify have good foolproof function, the encapsulation being used on TSOP-48L chip increases
The error-proof structure of identification point.
The open TSOP-48L chip package of the present invention increases the error-proof structure of identification point, and described TSOP-48L chip includes lead frame,
Single IC lead frame slip, crystal grain, die paddle and multiple pin, described lead frame is provided with one, described single IC lead-in wire
Frame slip is placed in lead frame, and described crystal grain is placed in single IC lead frame slip, described single IC lead frame slip
One end be provided with die paddle, the plurality of pin is provided with 48, and the interval between the plurality of pin is identical, and multiple pin
Symmetry and width are identical, and the first pin edge in the plurality of pin is along being provided with identification point, and described identification point is half round cut, institute
The radius stating half round cut is 0.15mm.
Limiting further as the present invention, the global shape of the plurality of pin is rectangle, between the plurality of pin
Interval forms hollow out.
Limiting further as the present invention, described first pin is PIN1.
Compared with prior art, the invention has the beneficial effects as follows: TSOP-48L chip package of the present invention increases the fool proof knot of identification point
Structure, mainly adds identification point PIN1 by the first pin in multiple pins, so that be easy to during encapsulation identify, is difficult to
Misplace position, improve work efficiency, saved the time, serve good foolproof function, can make at any lead frame product
Use, use extensively, be worthy to be popularized.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing TSOP-48L chip in the present invention；
Fig. 2 is the structural representation of existing TSOP-48L chip in the present invention；
Fig. 3 is the error-proof structure schematic diagram that in the present invention, TSOP-48L chip package increases identification point.
Fig. 4 is that in the present invention, the error-proof structure of TSOP-48L chip package increase identification point puts lead frame structural representation.
Fig. 5 is that in the present invention, the error-proof structure of TSOP-48L chip package increase identification point completes to cut structural representation.
In figure: chip 1, lead frame 2, single IC lead frame slip 3, crystal grain 4, die paddle 5, pin 6, hollow out
61, the first pin 7, identification point 8.
Detailed description of the invention
The present invention will be further described below in conjunction with the accompanying drawings, it will be appreciated that specific embodiment described herein is only used for explaining
The present invention, is not intended to limit the present invention.
As depicted in figs. 1 and 2, existing during TSOP-48L chip package, its encapsulation is generally all made lead frame used
Article one, lead frame 2, at the lead frame slip 3 of upper EDS maps multiple IC unit.It is distributed multiple TSOP-48L IC as Fig. 1 is one
Lead frame unit, the pin 6 at every two ends is all symmetrical, and the width of pin 6 all as, be so difficult to when packaging operation
Identifying direction, during board feeding, be not easy to be noticeable even if direction puts back, it is directional that the die bond technique of wafer die is placed
Requiring, if a lead frame entrance die bond track front is to being adjusted turnback, angle put by crystal grain will become the sample of Fig. 2
Son cause below bonding wire cannot operation and scrap.
As shown in Figures 3 to 5, TSOP-48L chip package increases the error-proof structure of identification point, described TSOP-48L chip bag
Include lead frame 1, single IC lead frame slip 2, crystal grain 4, die paddle 5 and multiple pin 6, the two of the plurality of pin 6
End symmetry, described lead frame 2 is provided with one, and described single IC lead frame slip 3 is placed in lead frame, described crystal grain 4
Being placed in single IC lead frame slip, one end of described single IC lead frame slip 3 is provided with die paddle 5, the plurality of
Pin 6 is provided with 48, and the interval between the plurality of pin 6 is identical, forms hollow out 61, and the width phase of multiple pin 6
With, the global shape of the plurality of pin 8 is rectangle.The first pin 7 edge in the plurality of pin 6 is provided with identification
Point 8, described first pin 7 is PIN1.So arrange, it is simple to during encapsulation, the positive and negative of identification chip.Described identification point 8
For the breach of semi-circular shape, so arrange, it is easy to identify.The radius of the breach of described semi-circular shape is 0.15mm.
The TSOP-48L chip package of the present invention increases the error-proof structure of identification point, it is achieved mode is as follows:
1, near the first pin, on rim charge, set the semicircular breach of a radius 0.15mm, so arrange, in encapsulation process
In, operator can eye recognition the most intuitively, it is also possible to by equipment identification, can after completing encapsulation breach will and rim charge
Cut together；(as shown in Figure 3)
2, the lead frame in error-proof structure is increased.(as shown in Figure 4)
3, complete die-cut after single IC pin, fool proof breach and rim charge together with cut.(as shown in Figure 5)
In sum, the TSOP-48L chip package of the present invention increases the error-proof structure of identification point, and TSOP-48L chip is in encapsulation
During, when its position is placed, misplace direction and don't can not be arrived by equipment Inspection, by increasing lead frame, it is achieved that fool proof
Function, increases fool proof identification characteristic point 8 near the first pin of lead frame, and it is labeled as PIN1, so arranges, and changes identification
Point is readily operated personnel or sealed in unit identification, thus plays foolproof function；It addition, this identification point is not increasing any envelope
In the case of dress technique process, can be removed again and finally encapsulated rear product and do not set up the product of fool proof point without any difference
Different, this identification point, during chip package, had played good foolproof function and identity was good, easy to operate.
Further, the TSOP-48L chip package of the present invention increases the error-proof structure of identification point, can be generalized to any use and draws
On the product of wire frame class, and the diameter of the fool proof identification point of the leadframe package of other multi-form and position thereof, should be according to specifically
The change of packing forms, on the basis of its design mainly can easily be seen based on bore hole and identify and don't affect packaging effect, increases anti-
Slow-witted design, reduces encapsulation error, it is to avoid product is wasted.
TSOP-48L chip package of the present invention increases the error-proof structure of identification point, main by the first pin increasing in multiple pins
Add identification point PIN1, so that be easy to during encapsulation identify, be difficult to misplace position, improve work efficiency, saved the time,
Serve good foolproof function, can use extensively, be worthy to be popularized on any lead frame product uses.It is pointed out that
Above-mentioned better embodiment is only technology design and the feature of the explanation present invention, its object is to allow person skilled in the art's energy
Solution present disclosure much of that is also implemented according to this, can not limit the scope of the invention with this.All real according to spirit of the present invention
Significant Change that matter is made or modification, all should contain within protection scope of the present invention.
Claims (3)
1.TSOP-48L chip package increases the error-proof structure of identification point, it is characterised in that: described TSOP-48L chip includes drawing
Wire frame, single IC lead frame slip, crystal grain, die paddle and multiple pin, described lead frame is provided with one, described single
IC lead frame slip is placed in lead frame, and described crystal grain is placed in single IC lead frame slip, described single IC lead-in wire
One end of frame slip is provided with die paddle, and the plurality of pin is provided with 48, and the interval between the plurality of pin is identical, and many
Individual pin is symmetrical and width is identical, and the first pin edge in the plurality of pin is along being provided with identification point, and described identification point is that semicircle lacks
Mouthful, the radius of described half round cut is 0.15mm.
TSOP-48L chip package the most according to claim 1 increases the error-proof structure of identification point, it is characterised in that: described
The global shape of multiple pins is rectangle, and the interval between the plurality of pin forms hollow out.
TSOP-48L chip package the most according to claim 1 increases the error-proof structure of identification point, it is characterised in that: described
First pin is PIN1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510208306.0A CN106158809A (en) | 2015-04-24 | 2015-04-24 | TSOP-48L chip package increases the error-proof structure of identification point |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510208306.0A CN106158809A (en) | 2015-04-24 | 2015-04-24 | TSOP-48L chip package increases the error-proof structure of identification point |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106158809A true CN106158809A (en) | 2016-11-23 |
Family
ID=57346586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510208306.0A Pending CN106158809A (en) | 2015-04-24 | 2015-04-24 | TSOP-48L chip package increases the error-proof structure of identification point |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106158809A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109994698A (en) * | 2018-12-06 | 2019-07-09 | 深圳欣旺达智能科技有限公司 | Battery protecting plate anti-misoperation device |
| CN110265378A (en) * | 2019-06-19 | 2019-09-20 | 福建福顺半导体制造有限公司 | A kind of electronic component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752341A (en) * | 2008-12-09 | 2010-06-23 | 四川金湾电子有限责任公司 | Lead frame of multi-chip integrated circuit |
| CN102891129A (en) * | 2012-08-30 | 2013-01-23 | 无锡永阳电子科技有限公司 | Pre-plastic-package lead frame and package process thereof |
-
2015
- 2015-04-24 CN CN201510208306.0A patent/CN106158809A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752341A (en) * | 2008-12-09 | 2010-06-23 | 四川金湾电子有限责任公司 | Lead frame of multi-chip integrated circuit |
| CN102891129A (en) * | 2012-08-30 | 2013-01-23 | 无锡永阳电子科技有限公司 | Pre-plastic-package lead frame and package process thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109994698A (en) * | 2018-12-06 | 2019-07-09 | 深圳欣旺达智能科技有限公司 | Battery protecting plate anti-misoperation device |
| CN110265378A (en) * | 2019-06-19 | 2019-09-20 | 福建福顺半导体制造有限公司 | A kind of electronic component |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161123 |