CN203573973U - DFN packaging lead frame - Google Patents
DFN packaging lead frame Download PDFInfo
- Publication number
- CN203573973U CN203573973U CN201320413221.2U CN201320413221U CN203573973U CN 203573973 U CN203573973 U CN 203573973U CN 201320413221 U CN201320413221 U CN 201320413221U CN 203573973 U CN203573973 U CN 203573973U
- Authority
- CN
- China
- Prior art keywords
- lead frame
- lead
- island
- chip
- outer pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model provides a DFN packaging lead frame, and the lead frame enables three or four related chips to be packaged in one device without external connection wires, thereby enabling the performance to be stable, achieving the packaging miniaturization of a chip, and reducing the cost because of one device. The lead frame comprises a frame, base islands, and outer pins. The central position of the lead frame is provided with the base islands. Two opposite sides of the lead frame are provided with the outer pins. The lead frame is characterized in that the central position of the lead frame is provided with the four base islands; and chips disposed on the base islands are respectively connected with the corresponding outer pin through an internal lead.
Description
Technical field
The utility model relates to the technical field of semiconductor packages, is specially a kind of DFN encapsulating lead.
Background technology
The lead frame of the DFN3 of standard * 2-8L encapsulation pattern is double-basis island, and the center of two Ji Dao is respectively placed with a chip, and for the product that has two chips that are associated, this encapsulation can meet miniaturization, function cheaply.But, be accompanied by the constantly complicated of product, there is the situation of simultaneously associated three chips, four chips in existing product, existing encapsulating structure can only be packaged into respectively two devices, by aerial lug, form again, owing to having used aerial lug, make stability poor; And owing to having used two packagings, it makes the chip package volume of product large, and has increased cost.
Summary of the invention
For the problems referred to above, the utility model provides a kind of DFN encapsulating lead, it makes can encapsulate three or four chips that are associated in a device simultaneously, without aerial lug, make stable performance, and encapsulation miniaturization, the microminiaturization of product chips are achieved, and a device has also reduced cost simultaneously.
A kind of DFN encapsulating lead, its technical scheme is such: it comprises framework, Ji Dao, outer pin, the center of described framework is provided with Ji Dao, a wherein offside of described framework is respectively arranged with outer pin, it is characterized in that: the center of described framework is provided with Si Geji island, the chip being loaded on described Ji Dao connects respectively corresponding outer pin by lead.
It is further characterized in that: a wherein offside of described framework is respectively arranged with four outer pins, wherein a side Liang Geji island is communicated with respectively two outer pins of the position separately of its respective side, on opposite side Liang Geji island, mutually cuts off with four outer pins of its respective side.
Adopt after the utility model, the Liang Geji island, center of DFN3 * 2-8L encapsulating lead of standard is separated into Si Geji island, the upper setting of Ji Dao mostly is four chip blocks most, chip connects respectively outer pin by lead, complete afterwards the encapsulation to chip, it makes can encapsulate three or four chips that are associated in a device simultaneously, and without aerial lug, make stable performance, and encapsulation miniaturization, the microminiaturization of product chips are achieved, and a device has also reduced cost simultaneously.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
Embodiment
See Fig. 1, it comprises framework 1, base island 2, outer pin 3, a wherein offside of framework 1 is respectively arranged with four outer pins 3, the center of framework 1 is provided with Si Geji island 2, wherein a side Liang Geji island 2 is communicated with respectively two outer pins 3 of the position separately of its respective side, on opposite side Liang Geji island 2, mutually cut off with four outer pins 3 of its respective side, the chip 4 being loaded on base island 2 connects respectively corresponding outer pin 3 by lead 5.
Its chips 4 connects outer pin 3 by lead 5 and can directly connect, thereby also chip 4 can be connected to by lead 5 and the corresponding outer pin 3 Ji island 2 that is connected completes the connection of the outer pin 3 of chip 4 and correspondence.
Claims (2)
1. a DFN encapsulating lead, it comprises framework, Ji Dao, outer pin, the center of described framework is provided with Ji Dao, a wherein offside of described framework is respectively arranged with outer pin, it is characterized in that: the center of described framework is provided with Si Geji island, the chip being loaded on described Ji Dao connects respectively corresponding outer pin by lead.
2. a kind of DFN encapsulating lead according to claim 1, it is characterized in that: a wherein offside of described framework is respectively arranged with four outer pins, wherein a side Liang Geji island is communicated with respectively two outer pins of the position separately of its respective side, on opposite side Liang Geji island, mutually cuts off with four outer pins of its respective side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320413221.2U CN203573973U (en) | 2013-07-12 | 2013-07-12 | DFN packaging lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320413221.2U CN203573973U (en) | 2013-07-12 | 2013-07-12 | DFN packaging lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203573973U true CN203573973U (en) | 2014-04-30 |
Family
ID=50541687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320413221.2U Expired - Lifetime CN203573973U (en) | 2013-07-12 | 2013-07-12 | DFN packaging lead frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203573973U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103413801A (en) * | 2013-07-12 | 2013-11-27 | 无锡红光微电子有限公司 | DFN package lead frame |
-
2013
- 2013-07-12 CN CN201320413221.2U patent/CN203573973U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103413801A (en) * | 2013-07-12 | 2013-11-27 | 无锡红光微电子有限公司 | DFN package lead frame |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140430 |