CN201829490U - Chip area punching integrated circuit lead frame - Google Patents
Chip area punching integrated circuit lead frame Download PDFInfo
- Publication number
- CN201829490U CN201829490U CN2010205810445U CN201020581044U CN201829490U CN 201829490 U CN201829490 U CN 201829490U CN 2010205810445 U CN2010205810445 U CN 2010205810445U CN 201020581044 U CN201020581044 U CN 201020581044U CN 201829490 U CN201829490 U CN 201829490U
- Authority
- CN
- China
- Prior art keywords
- chip area
- lead frame
- chip region
- circuit lead
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a chip area punching integrated circuit lead frame which comprises a chip area (1), a connecting rod (2), pins (4) connected with the chip area (1) into a whole and small welding spots (3) arranged on the pins (4), and is characterized in that each of four corners of the chip area (1) is provided with a small round hole (5). For the chip area punching integrated circuit lead frame, as four small round holes are added in the chip area, when a substrate and a plastic package body are combined, the plastic package body passes through the small round holes, so that the binding force between the chip area and the plastic package body can be improved, and the plastic package body is not easy to be stripped and damaged even when being subjected to external force.
Description
Technical field
The utility model relates to a kind of lead frame, is specifically related to a kind of chip region punching circuit lead frame, the lead frame of the use in the thin type integrated circuit encapsulation that suits.
Background technology
Lead frame is to make the basic element of character of producing semiconductor element, utilizes resin plastic-sealed chip to be fixed into holistic semiconductor element.
Existing integrated circuits SSOP24L lead frame as shown in Figure 2, it is linked to be whole pin 4 by chip region 1, connecting rod 2 and chip region 1, each little solder joint 3 above the pin 4 is formed.Its plastic packaging slim body when being subjected to external force, makes Ji Dao and plastic-sealed body peel off easily, damage.
Summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides the adhesion of a kind of Ji Dao and plastic-sealed body strong, the chip region punching circuit lead frame that is difficult for peeling off.
The purpose of this utility model is achieved in that a kind of chip region punching circuit lead frame, comprise that chip region, connecting rod and chip region are linked to be whole pin and each little solder joint above the pin, is characterized in that: respectively be provided with a small sircle hole on four angles of described chip region.
The diameter of described small sircle hole is 0.8 ± 0.1 ㎜.
Compared with prior art, the beneficial effects of the utility model are:
The utility model chip region punching circuit lead frame, increased by four small sircle holes in chip region, when Ji Dao and plastic-sealed body in conjunction with the time, plastic-sealed body passes from small sircle hole, can improve the adhesion of chip region and plastic-sealed body, also be difficult for when making it be subjected to external force peeling off, damaging.
Description of drawings
Fig. 1 is a prior art circuit lead frame product schematic diagram.
Fig. 2 is the I portion enlarged drawing of Fig. 1.
Fig. 3 is the structural representation of the utility model chip region punching circuit lead frame.
Fig. 4 is the encapsulation figure of Fig. 3.
Wherein:
Embodiment
Referring to Fig. 3, a kind of SSOP24L chip region punching circuit lead frame that the utility model relates to, described lead frame is linked to be whole pin 4 by chip region 1, connecting rod 2 and chip region 1 and the little solder joint 3 above each pin 4 is formed, respectively be provided with a small sircle hole 5 on four angles of described chip region 1, the diameter of described small sircle hole 5 is 0.8 ± 0.1 ㎜.
During lead-frame packages, referring to Fig. 4, plastic-sealed body 6 passes from small sircle hole 5, can improve the adhesion of chip region (being Ji Dao) and plastic-sealed body 6, also is difficult for when making it be subjected to external force peeling off, damaging.
Claims (2)
1. chip region punching circuit lead frame, comprise that chip region (1), connecting rod (2) and chip region (1) are linked to be whole pin (4) and the little solder joint (3) above each pin (4), is characterized in that: respectively be provided with a small sircle hole (5) on four angles of described chip region (1).
2. a kind of chip region punching circuit lead frame according to claim 1, it is characterized in that: the diameter of described small sircle hole (5) is 0.8 ± 0.1 ㎜.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205810445U CN201829490U (en) | 2010-10-28 | 2010-10-28 | Chip area punching integrated circuit lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205810445U CN201829490U (en) | 2010-10-28 | 2010-10-28 | Chip area punching integrated circuit lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201829490U true CN201829490U (en) | 2011-05-11 |
Family
ID=43968008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010205810445U Expired - Fee Related CN201829490U (en) | 2010-10-28 | 2010-10-28 | Chip area punching integrated circuit lead frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201829490U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760717A (en) * | 2012-07-19 | 2012-10-31 | 无锡红光微电子有限公司 | SOT223-3L packaging lead frame |
| CN102760716A (en) * | 2012-07-19 | 2012-10-31 | 无锡红光微电子有限公司 | TO-252 package lead framework structure |
| CN104752386A (en) * | 2013-12-25 | 2015-07-01 | 天水华天科技股份有限公司 | High reliability small outline package (SOP) lead frame and production method of packaging piece |
-
2010
- 2010-10-28 CN CN2010205810445U patent/CN201829490U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760717A (en) * | 2012-07-19 | 2012-10-31 | 无锡红光微电子有限公司 | SOT223-3L packaging lead frame |
| CN102760716A (en) * | 2012-07-19 | 2012-10-31 | 无锡红光微电子有限公司 | TO-252 package lead framework structure |
| CN104752386A (en) * | 2013-12-25 | 2015-07-01 | 天水华天科技股份有限公司 | High reliability small outline package (SOP) lead frame and production method of packaging piece |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110511 Termination date: 20151028 |
|
| EXPY | Termination of patent right or utility model |