CN201893335U - Dual-chip integrated circuit lead frame - Google Patents

Dual-chip integrated circuit lead frame Download PDF

Info

Publication number
CN201893335U
CN201893335U CN 201020678940 CN201020678940U CN201893335U CN 201893335 U CN201893335 U CN 201893335U CN 201020678940 CN201020678940 CN 201020678940 CN 201020678940 U CN201020678940 U CN 201020678940U CN 201893335 U CN201893335 U CN 201893335U
Authority
CN
China
Prior art keywords
lead frame
pin
dap
paddle
dual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 201020678940
Other languages
Chinese (zh)
Inventor
王辉
阮怀其
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd
Original Assignee
ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd filed Critical ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd
Priority to CN 201020678940 priority Critical patent/CN201893335U/en
Application granted granted Critical
Publication of CN201893335U publication Critical patent/CN201893335U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The utility model relates to a dual-chip integrated circuit lead frame, which comprises a Paddle DAP, a small Paddle DAP and pins, wherein a seventh pin and an eighth pin are connected with the Paddle DAP, and at least one locking hole is arranged on the Paddle DAP; and the aperture of each locking hole is 0.7-0.72mm. In the actual production process, since the locking holes are additionally arranged on the Paddle DAP, the bonding force of a plastic-sealed material and the lead frame can be increased, and the layering or cracking of products can be reduced.

Description

A kind of twin-core sheet leads of IC frame
Technical field
The utility model relates to a kind of lead frame, is specifically related to a kind of twin-core sheet leads of IC frame.
Background technology
Multicore sheet encapsulation is a unusual hot issue in the market.In the cavity of an integrated circuit, put into more than one chip, can save the application space greatly, make things convenient for the design of complete machine to use.Some device, the technology difference owing to adopting can't realize in a chip in chip manufacturing proces, maybe can't be integrated in the chip.Twin-core sheet encapsulation is exactly to solve the chip of two different manufacturing process to be placed on method in the same circuit.DIP8 twin-core sheet lead frame on present market has many moneys, and during the very big leadframe design of wherein a use amount, 7 pin, 8 pin and Ji Dao connect together, as shown in Figure 1.This lead frame operation product connects together because of 7 pin, 8 pin and Ji Dao, and area is very big, and plastic packaging is when the plastic-sealed body inner frame is stressed in the Trim Molding process, and product is easy to generate layering, even cracking.
Summary of the invention
At above-mentioned problems of the prior art, the purpose of this utility model is to provide a kind of twin-core sheet leads of IC frame, and this lead frame can not produce layering or cracking in the Trim Molding process.
The utility model is the technical scheme that its purpose of realization is taked: a kind of twin-core sheet leads of IC frame, comprise Ji Dao, little Ji Dao and pin, and 7 pin, 8 pin in the described pin link to each other with Ji Dao, establish at least one lock-bit hole on the described Ji Dao.The aperture in described lock-bit hole is 0.7-0.72mm.
The beneficial effects of the utility model: in actual production process,, can increase the adhesion of plastic packaging material and lead frame, reduce product layering or cracking owing to the lock-bit hole that on Ji Dao, increases.
Description of drawings
Below in conjunction with the drawings and specific embodiments the utility model is further specified.
Fig. 1 is DIP8 twin-core sheet lead frame structure figure of the prior art;
Fig. 2 is the utility model structural representation.
Embodiment
Referring to Fig. 1, present embodiment is an example with DIP8 twin-core sheet lead frame, and this lead frame comprises basic island 2, little basic island 3 and pin 1.DIP8 twin-core sheet lead frame contains 8 pins, and wherein 7 pin, 8 pin and basic island 2 link to each other, and establish lock-bit hole 4 on basic island 2.The lock-bit hole can be established 1-3, establishes 2 in this example.The aperture in lock-bit hole is 0.711mm.Owing to the lock-bit hole that on Ji Dao, increases, can increase the adhesion of plastic packaging material and lead frame, reduce the product layering.

Claims (2)

1. a twin-core sheet leads of IC frame comprises Ji Dao, little Ji Dao and pin, and 7 pin, 8 pin in the described pin link to each other with Ji Dao, it is characterized in that: establish at least one lock-bit hole on the described Ji Dao.
2. twin-core sheet leads of IC frame according to claim 1, it is characterized in that: the aperture in described lock-bit hole is 0.7-0.72mm.
CN 201020678940 2010-12-24 2010-12-24 Dual-chip integrated circuit lead frame Expired - Fee Related CN201893335U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201020678940 CN201893335U (en) 2010-12-24 2010-12-24 Dual-chip integrated circuit lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201020678940 CN201893335U (en) 2010-12-24 2010-12-24 Dual-chip integrated circuit lead frame

Publications (1)

Publication Number Publication Date
CN201893335U true CN201893335U (en) 2011-07-06

Family

ID=44222805

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201020678940 Expired - Fee Related CN201893335U (en) 2010-12-24 2010-12-24 Dual-chip integrated circuit lead frame

Country Status (1)

Country Link
CN (1) CN201893335U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103943593A (en) * 2014-03-26 2014-07-23 张轩 Lead frame with two kinds of chips
CN109075151A (en) * 2016-04-26 2018-12-21 凌力尔特科技有限责任公司 The lead frame that mechanical engagement and electrically and thermally for component package circuit conduct
US11749576B2 (en) 2018-03-27 2023-09-05 Analog Devices International Unlimited Company Stacked circuit package with molded base having laser drilled openings for upper package
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103943593A (en) * 2014-03-26 2014-07-23 张轩 Lead frame with two kinds of chips
CN109075151A (en) * 2016-04-26 2018-12-21 凌力尔特科技有限责任公司 The lead frame that mechanical engagement and electrically and thermally for component package circuit conduct
US11749576B2 (en) 2018-03-27 2023-09-05 Analog Devices International Unlimited Company Stacked circuit package with molded base having laser drilled openings for upper package
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Similar Documents

Publication Publication Date Title
CN201893335U (en) Dual-chip integrated circuit lead frame
EP2811514A3 (en) Moulded semiconductor package with capacitive and inductive components
WO2007100927A3 (en) Method of packaging a semiconductor die and package thereof
CN103985692A (en) Encapsulating structure for AC-DC power circuit and encapsulating method thereof
CN201773825U (en) Encapsulation die
CN201829489U (en) Chip area blank-pressing integrated circuit lead frame
CN209119087U (en) Lead frame and the packaging body for using the lead frame
CN201829490U (en) Chip area punching integrated circuit lead frame
CN203871320U (en) Packaging structure of AC-DC power supply circuit
CN202084532U (en) TO92 model encapsulation box and supporting moulds
CN202651105U (en) Surface-mount-type bridge-type lead frame
CN201229941Y (en) Lead wire frame for transistor
CN202712172U (en) Multi-chip dual-base island SOP package structure
CN204054661U (en) A kind of annulus pasting mould of enhancing productivity
CN204375733U (en) A kind of Double-lead-frame
CN104175497B (en) Imbedded fiber in mould
CN204516746U (en) The fingerprint sensor package structure of pluggable FPC
CN202917480U (en) Multi-chip integrated circuit leading wire framework for increasing plastic packaging binding force
CN203210622U (en) Plastic packaging mold box
CN203277358U (en) Leading wire frame for MOS semiconductor device
CN201689919U (en) LED-SMD lead frame structure
CN203617274U (en) Lead frame for low-power devices
CN204375734U (en) Framework is utilized to encapsulate the wire bonding and packaging structure rerouted
CN201829491U (en) Plastic-packaged reinforced triode lead frame
CN202120882U (en) Semiconductor packaging mold construction having no pins all around

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110706

Termination date: 20141224

EXPY Termination of patent right or utility model