CN202120882U - Semiconductor packaging mold construction having no pins all around - Google Patents

Semiconductor packaging mold construction having no pins all around Download PDF

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Publication number
CN202120882U
CN202120882U CN 201120201239 CN201120201239U CN202120882U CN 202120882 U CN202120882 U CN 202120882U CN 201120201239 CN201120201239 CN 201120201239 CN 201120201239 U CN201120201239 U CN 201120201239U CN 202120882 U CN202120882 U CN 202120882U
Authority
CN
China
Prior art keywords
lead frame
mold
electromagnet
utility
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN 201120201239
Other languages
Chinese (zh)
Inventor
王新潮
谢洁人
吴昊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN 201120201239 priority Critical patent/CN202120882U/en
Application granted granted Critical
Publication of CN202120882U publication Critical patent/CN202120882U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model relates to a semiconductor packaging mold construction having no pins all around. The mold construction includes a lead frame which is made by magnetic materials and comprises a base island (1), a pin (2), wherein the lead frame which is provided with a chip (5) and a metal wire (6) is arrange between an upper mold (8) and a lower mold (9) and the lower mold (9) is connected with a electromagnet (10). The semiconductor packaging mold construction having no pins all around provided by the utility model connects an electromagnet switch on the packaging mold to make magnetic lead sucking on the packaging mold during packaging, thus saving a traditional back adhesive film and reducing cost for producing a lead frame. Moreover, as no adhesive film is attached on the back, the product quality is easier to control and the production yield can be improved during wire bonding.

Description

Four sides leadless semiconductor encapsulating mould structure
Technical field
The utility model relates to a kind of semiconductor packaging mold structure.Belong to the semiconductor packaging field.
Background technology
The tradition four sides does not have the structure of pin lead frame; Be to adopt earlier after chemical etching and electroplating surface are carried out in the front of metal substrate; Stick the resistant to elevated temperatures glued membrane of one deck again at the back side of metal substrate and form the leadframe carrier (as shown in Figure 1) that to carry out encapsulation process; Again leadframe carrier is carried out the load routing, carry out the encapsulation of plastic packaging material at last again.But because but the glued membrane of one deck costliness high temperature resistance must be sticked in this kind packaged type lead frame back side, so directly increased packaging cost.Again because the glued membrane quality is soft, in load routing process, cause easily routing loosening with problems such as solder joint is not firm, like Fig. 2.And it is bad in encapsulation process, glue-film stickup to occur through regular meeting, thereby causes plastic packaging material flash in the encapsulation process to form defective products to lead frame positive Ji Dao or pin.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency, provide a kind of packaging cost low, can not cause problems such as routing is bad and the four sides leadless semiconductor encapsulating mould structure that can effectively avoid flash.
The purpose of the utility model is achieved in that a kind of four sides leadless semiconductor encapsulating mould structure; Said mould structure comprises lead frame; Lead frame adopts magnetic material to make, and lead frame comprises Ji Dao and pin, and lead frame is provided with chip and metal wire; The said lead frame that is provided with chip and metal wire is positioned between a patrix and the counterdie, and counterdie is connected with electromagnet.
The utility model four sides leadless semiconductor encapsulating mould structure, can also be applied with on the said patrix with said counterdie on another opposite electromagnet of electromagnet polarity.
The utility model four sides leadless semiconductor encapsulating mould structure, said magnetic material is iron or ferroalloy.
The utility model four sides leadless semiconductor encapsulating mould structure, said magnetic material is the composite material of iron and copper; Or be the composite material of ferroalloy and copper.
Because lead frame and counterdie adsorbed close, plastic packaging material can not pierce the bottom of Ji Dao and pin on the lead frame, has saved pad pasting.After treating that plastic packaging material solidifies, promptly accomplished traditional operation of sealing.
The beneficial effect of the utility model is:
Problems such as the four sides that the utility model mould structure adopts magnetic metal to make does not have the pin lead frame structure, has saved the glued membrane at the back side, not only reduced packaging cost, and in load routing technology, it is bad can not routing to occur, and solder joint is loosening.When follow-up encapsulation, and when encapsulation, adopt magnetic encapsulating mold to seal plastic packaging material,, control whether adsorb the magnetic lead frame through selecting opening or closing of electromagnet.When encapsulating mold adsorbs lead frame, can effectively avoid flash.
Description of drawings
Fig. 1 was not for had the sketch map that high temperature resistant glued membrane is sticked at the pin lead frame back side at the four sides in the past.
Fig. 2 is that the four sides of rubberizing film did not have pin lead frame routing sketch map in the past.
The four sides that Fig. 3 adopts for the utility model does not have the sketch map of pin lead frame structure.
Fig. 4 does not have pin lead frame routing sketch map for the four sides of the utility model.
Fig. 5 is the utility model four sides leadless semiconductor encapsulating mould structural representation.
Reference numeral among the figure:
Base island 1
Pin 2
Glued membrane 3
The company's of etching partially muscle 4
Chip 5
Metal wire 6
Chopper 7
Patrix 8
Counterdie 9
Electromagnet 10.
Embodiment
Referring to Fig. 5, Fig. 5 is the utility model four sides leadless semiconductor encapsulating mould structural representation.Can find out by Fig. 5; The four sides leadless semiconductor encapsulating mould structure that the utility model relates to, said mould structure comprises lead frame, lead frame adopts magnetic material to make; Lead frame comprises basic island 1 and pin 2; Lead frame is provided with chip 5 and metal wire 6, and the said lead frame that is provided with chip 5 and metal wire 6 is positioned between a patrix 8 and the counterdie 9, is connected with electromagnet 10 on the counterdie 9.
The making of said mould structure comprises following technical process:
Step 1, get a magnetic material substrate and carry out chemical etching and electroplating surface, form basic island 1, pin 2 and the company's of etching partially muscle 4, accomplish the production of lead frame, like Fig. 3 at the magnetic material substrate on its surface.Said magnetic material substrate is made with magnetic metal materials such as iron, ferroalloys, or is the composite material making of ferroalloy and copper.
Step 2, the lead frame that step 1 is completed carry out the load routing, like Fig. 4;
Step 3, the lead frame that will accomplish behind the load routing are positioned between a patrix 8 and the counterdie 9, and counterdie 9 is connected with electromagnet 10, after lead frame is placed into assigned address; Open the switch of electromagnet 10; Counterdie 9 is that adsorbed close is lived lead frame, like Fig. 5, carries out mold-closing injection this moment again.After treating that plastic packaging material solidifies, promptly accomplished traditional operation of sealing.
The utility model can also be applied with on the said patrix 8 with said counterdie 9 on electromagnet 10 opposite polarity another electromagnet (not shown)s, with avoid having on the patrix with counterdie 9 on opposite polarity polarity.
The said magnetic material of the utility model is iron or ferroalloy; Or be that said magnetic material is the composite material of iron and copper; Or be the composite material of ferroalloy and copper.

Claims (3)

1. four sides leadless semiconductor encapsulating mould structure; It is characterized in that: said mould structure comprises lead frame; Lead frame adopts magnetic material to make, and lead frame comprises Ji Dao (1) and pin (2), and lead frame is provided with chip (5) and metal wire (6); The said lead frame that is provided with chip (5) and metal wire (6) is positioned between a patrix (8) and the counterdie (9), and counterdie (9) is connected with electromagnet (10).
2. a kind of four sides according to claim 1 leadless semiconductor encapsulating mould structure is characterized in that: be applied with on the said patrix (8) with said counterdie (9) on opposite polarity another electromagnet of electromagnet (10).
3. a kind of four sides according to claim 1 and 2 leadless semiconductor encapsulating mould structure, it is characterized in that: said magnetic material is iron or ferroalloy.
CN 201120201239 2011-06-15 2011-06-15 Semiconductor packaging mold construction having no pins all around Expired - Lifetime CN202120882U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201120201239 CN202120882U (en) 2011-06-15 2011-06-15 Semiconductor packaging mold construction having no pins all around

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201120201239 CN202120882U (en) 2011-06-15 2011-06-15 Semiconductor packaging mold construction having no pins all around

Publications (1)

Publication Number Publication Date
CN202120882U true CN202120882U (en) 2012-01-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201120201239 Expired - Lifetime CN202120882U (en) 2011-06-15 2011-06-15 Semiconductor packaging mold construction having no pins all around

Country Status (1)

Country Link
CN (1) CN202120882U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231366A (en) * 2011-06-15 2011-11-02 江苏长电科技股份有限公司 Four-side without pin semiconductor packaging method and packaging die structure thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231366A (en) * 2011-06-15 2011-11-02 江苏长电科技股份有限公司 Four-side without pin semiconductor packaging method and packaging die structure thereof

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20170113

Address after: Tianjin City, Tianjin free trade zone (Dongjiang Bonded Port) No. 6865 North Road, 1-1-1802-7 financial and trade center of Asia

Patentee after: Xin Xin finance leasing (Tianjin) Co., Ltd.

Address before: 214434 Binjiang Middle Road, Jiangyin Development Zone, Jiangsu, China, No. 275, No.

Patentee before: Jiangsu Changdian Sci. & Tech. Co., Ltd.

EE01 Entry into force of recordation of patent licensing contract
EE01 Entry into force of recordation of patent licensing contract

Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd.

Assignor: Xin Xin finance leasing (Tianjin) Co., Ltd.

Contract record no.: 2017320000152

Denomination of utility model: Semiconductor packaging mold construction having no pins all around

Granted publication date: 20120118

License type: Exclusive License

Record date: 20170614

EC01 Cancellation of recordation of patent licensing contract
EC01 Cancellation of recordation of patent licensing contract

Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.

Assignor: Xin Xin finance leasing (Tianjin) Co., Ltd.

Contract record no.: 2017320000152

Date of cancellation: 20200416

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20200428

Address after: 214434, No. 78, mayor road, Chengjiang, Jiangsu, Jiangyin, Wuxi

Patentee after: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.

Address before: 1-1-1802-7, North Zone, financial and Trade Center, No. 6865, Asia Road, Tianjin pilot free trade zone (Dongjiang Free Trade Port Area), Tianjin

Patentee before: Xin Xin finance leasing (Tianjin) Co., Ltd.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20120118