CN203339152U - Monolithic chip flat packaging part based on stamping framework - Google Patents
Monolithic chip flat packaging part based on stamping framework Download PDFInfo
- Publication number
- CN203339152U CN203339152U CN201220425503XU CN201220425503U CN203339152U CN 203339152 U CN203339152 U CN 203339152U CN 201220425503X U CN201220425503X U CN 201220425503XU CN 201220425503 U CN201220425503 U CN 201220425503U CN 203339152 U CN203339152 U CN 203339152U
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- CN
- China
- Prior art keywords
- framework
- chip
- bonding
- lead frame
- part based
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to a monolithic chip flat packaging part based on stamping framework, belonging to the integrated circuit package technology field. The monolithic chip flat packaging part based on stamping framework employs a novel framework which is made by stamping method and through holes are formed on the framework through stamping or drilling to replace the etching method of etching steps on the framework to resist delamination; the sealants are filled in the through holes in the process of packaging of the integrated circuit so as to form a structure effectively preventing pulling and dragging between the framework and the sealants; and so the binding force between the sealants and the framework is better, which greatly reduces the possibility of delamination and greatly improves product reliability. In the meantime, the monolithic chip flat packaging part based on stamping framework solves the defects that the costs of the grinding framework and the half-erosion framework are high and the costs are greatly reduced.
Description
Technical field
The utility model relates to a kind of single-chip flat packaging part based on ram frame, belongs to the integrated antenna package technical field.
Background technology
The QFN(flat-four-side is without pin package) and the dual flat non-leaded encapsulation of DFN() encapsulation grows up, is applicable to high frequency, broadband, low noise, high heat conduction, small size in the generation (digital camera, mobile phone, PC, MP3) along with communication and portable small-sized digital electronic goods in recent years, the high-speed encapsulation that waits the middle small scale integrated circuit electrically required.We know that the QFN/DFN encapsulation has effectively utilized the encapsulated space of terminal pin, thereby have improved significantly packaging efficiency.But all face some difficult problems for selecting of framework in the manufacture process of current most of semiconductor packages QFN/DFN of manufacturer, available frame is two kinds of ram frame and etched frame, ram frame, its mould adopts the Mechanical Method work to form, production efficiency is high, single product cost is lower, but the lead frame for some special graphs, can't select pressing processing, the framework exposed such as carriers such as QFN/DFN/QFP, between carrier and interior pin, certain difference in height is arranged, form certain step, pressing is difficult to realization and controls this step well; The chemical etching framework, its die cost is low, and the construction cycle is short, can reach 2 weeks～1 month, and during encapsulation, plastic packaging, cutting die can share, and input cost is low, but its production efficiency is low, and single product cost is higher.
In the plastic packaging operation of existing QFN/DFN technique, due to the limitation of frame structure, cause the QFN/DFN encapsulation to have the following disadvantages:
1. the adhesion of integrated circuit (IC) chip and carrier is bad, when changed by external environment affect the time, can cause interiors of products to produce lamination defect, cause taking off of performance, even lost efficacy.
2. the adhesion of the carrier back side and plastic packaging material is bad, when the impact that is subject to external environment, can cause product to produce defect (layering); Or expose on carrier (Ji Dao) thicker flash is arranged.
The utility model content
For above-mentioned defect, the utility model provides a kind of single-chip flat packaging part based on ram frame, and the combination of plastic packaging material and framework is more firm, and anti-layered effect is better.
The technical solution adopted in the utility model: the single-chip package part comprises lead frame 1, bonding die glue 2, chip 3, bonding line 4, perforate 5, plastic-sealed body 6; On lead frame 1, be wherein bonding die glue 2; it on bonding die glue 2, is chip 3; solder joint on chip 3 and the bonding wire on lead frame are bonding lines 4; chip 3 is connected by bonding die glue 2 with lead frame 1; bonding line 4 is directly got to lead frame 1 from chip 3; lead frame 1 is provided with perforate 5; plastic-sealed body 6 has surrounded the integral body that lead frame 1, bonding die glue 2, chip 3, bonding line 4 have formed circuit; the bonding line 4 of 6 pairs of chips 3 of plastic-sealed body has played support and protective effect, and chip 3, bonding line 4, lead frame 1 have formed power supply and the signalling channel of circuit.
Described bonding die glue 2 can use glue film (DAF) to replace; Bonding line 4 adopts gold thread or copper cash.
The beneficial effects of the utility model: the utility model makes the adhesion between plastic packaging material and framework better, greatly reduces may going of layering, significantly improves product reliability.Solved simultaneously and ground framework in the past and partly corrode the defect that the framework expense is high, greatly reduced cost.
The accompanying drawing explanation
Fig. 1 plastic packaged products profile of the present utility model.
In figure: 1-lead frame, 2-bonding die glue or glue film (DAF), 3-chip, 4-bonding line, 5-perforate, 6-plastic-sealed body.
Embodiment
Below in conjunction with accompanying drawing, the utility model is elaborated, to facilitate the technical staff to understand.
As shown in Figure 1: the single-chip package part comprises lead frame 1, bonding die glue 2, chip 3, bonding line 4, perforate 5, plastic-sealed body 6; On lead frame 1, be wherein bonding die glue 2; it on bonding die glue 2, is chip 3; solder joint on chip 3 and the bonding wire on lead frame are bonding lines 4; chip 3 is connected by bonding die glue 2 with lead frame 1; bonding line 4 is directly got to lead frame 1 from chip 3; lead frame 1 is provided with perforate 5; plastic-sealed body 6 has surrounded the integral body that lead frame 1, bonding die glue 2, chip 3, bonding line 4 have formed circuit; the bonding line 4 of 6 pairs of chips 3 of plastic-sealed body has played support and protective effect, and chip 3, bonding line 4, lead frame 1 have formed power supply and the signalling channel of circuit.
Described bonding die glue 2 can use glue film (DAF) to replace; Bonding line 4 adopts gold thread or copper cash.
The tradition ram frame is after plastic packaging operation plastic packaging material is filled, and because framework itself is smooth smooth, the conjugation between plastic packaging material and framework is low, the situation of layering very easily occurs, and the packaging part reliability can not be guaranteed.The ram frame different from the past that the utility model adopts, after method square hole 5 with punching or boring on framework, during plastic packaging, plastic packaging material can be inserted square hole 5 automatically, form effectively anti-traction structure between framework and plastic packaging material, greatly reduce the occurrence probability of packaging part layering situation, greatly improve product reliability, be better than the plastic packaging effect that tradition etches partially ram frame.
The utility model describes by specific implementation process, in the situation that do not break away from the utility model scope, can also carry out various conversion and be equal to replacement the utility model patent.Therefore, the utility model patent is not limited to disclosed specific implementation process, and should comprise the whole embodiments that fall in the utility model Patent right requirement scope.
Claims (3)
1. the single-chip flat packaging part based on ram frame, it is characterized in that: the single-chip package part comprises lead frame, bonding die glue, chip, bonding line, perforate, plastic-sealed body; On lead frame, be wherein bonding die glue; on bonding die glue, it is chip; solder joint and the bonding wire on lead frame on chip are bonding lines; chip is connected by bonding die glue with lead frame; bonding line is directly got to lead frame from chip; lead frame is provided with perforate; plastic-sealed body has surrounded the integral body that lead frame, bonding die glue, chip, bonding line have formed circuit; plastic-sealed body has played support and protective effect to the bonding line of chip, and chip, bonding line, lead frame have formed power supply and the signalling channel of circuit.
2. a kind of single-chip flat packaging part based on ram frame according to claim 1, it is characterized in that: bonding die glue can replace with glue film.
3. a kind of single-chip flat packaging part based on ram frame according to claim 1, is characterized in that: bonding line employing gold thread or copper cash.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220425503XU CN203339152U (en) | 2012-08-21 | 2012-08-21 | Monolithic chip flat packaging part based on stamping framework |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220425503XU CN203339152U (en) | 2012-08-21 | 2012-08-21 | Monolithic chip flat packaging part based on stamping framework |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203339152U true CN203339152U (en) | 2013-12-11 |
Family
ID=49707814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201220425503XU Expired - Lifetime CN203339152U (en) | 2012-08-21 | 2012-08-21 | Monolithic chip flat packaging part based on stamping framework |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203339152U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104505381A (en) * | 2014-12-30 | 2015-04-08 | 华天科技（西安）有限公司 | Lead frame of cavity carrier structure |
-
2012
- 2012-08-21 CN CN201220425503XU patent/CN203339152U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104505381A (en) * | 2014-12-30 | 2015-04-08 | 华天科技（西安）有限公司 | Lead frame of cavity carrier structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131211 |
|
| CX01 | Expiry of patent term |