CN102832141A - Manufacturing process of carrier-free package based on framework - Google Patents
Manufacturing process of carrier-free package based on framework Download PDFInfo
- Publication number
- CN102832141A CN102832141A CN2012103068308A CN201210306830A CN102832141A CN 102832141 A CN102832141 A CN 102832141A CN 2012103068308 A CN2012103068308 A CN 2012103068308A CN 201210306830 A CN201210306830 A CN 201210306830A CN 102832141 A CN102832141 A CN 102832141A
- Authority
- CN
- China
- Prior art keywords
- carrier
- framework
- salient point
- metal salient
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 43
- 238000005520 cutting process Methods 0.000 claims abstract description 6
- 238000003466 welding Methods 0.000 claims abstract description 6
- 238000004806 packaging method and process Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 25
- 239000003292 glue Substances 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 11
- 238000005260 corrosion Methods 0.000 claims description 4
- 230000007797 corrosion Effects 0.000 claims description 4
- 239000000428 dust Substances 0.000 claims description 4
- 239000000969 carrier Substances 0.000 abstract 1
- 238000003754 machining Methods 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000003319 supportive effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention relates to a manufacturing process of a carrier-free package based on a framework, belonging to the technical field of integrated circuit package. The manufacturing process successively comprises wafer thinning, scribing, core installing, making of metal bumps, press welding, plastic package, removal of the framework and cutting. An ordinary framework can be used for the produce manufacturing flow, the machining of excessive framework carriers is not required, the design and manufacturing period is shortened, and the cost is reduced. The bump arrangement and I/O number are not restricted by the framework and the manufacturing, the free definition of bump arrangement is realized, and the interconnection between a chip and a carrier is better realized; and I/O are more intensive, and the cost is lower.
Description
Technical field
The present invention relates to a kind of manufacture craft of the carrier-free formula packaging part based on framework, belong to integrated circuit encapsulation technology field.
Background technology
QFN (flat-four-side does not have pin package) and DFN (dual flat non-leaded encapsulation) encapsulation was growing up, had been applicable to high frequency, broadband, low noise, high heat conduction, small size along with the generation (digital camera, mobile phone, PC, MP3) of communication and portable small-sized digital electronic goods in recent years, the high-speed encapsulation that waits the middle small scale integrated circuit that electrically requires.We know that the QFN/DFN encapsulation has effectively utilized the encapsulated space of terminal pin, thereby have improved packaging efficiency significantly.This encapsulation can make CPU volume-diminished 30%-50% because lead-in wire is short and small, the plastic-sealed body size is little, packaging body is thin.So it can provide remarkable electrical property, and outstanding heat dispersion also is provided simultaneously.
Not enough below the common main existence of QFN/DFN encapsulation: the QFN/DFN product needed of frame carrier is according to chip size and circuit communication design framework figure; Framework is processed into the figure that designs with methods such as corrosion again; Design and fabrication cycle are long, and cost is than higher.And present QFN/DFN series packaging part salient point arrange and the dense degree of I/O on also because Frame Design and framework manufacturing process and restriction to some extent.
Summary of the invention
In order to overcome the problem that above-mentioned prior art exists; The present invention provides a kind of manufacture craft of the carrier-free formula packaging part based on framework, adopts frame-generic can carry out the production flow process, need not the multi-processing frame carrier; Shorten design and fabrication cycle, reduce cost; Arrange and the I/O number does not receive Frame Design and makes restriction at salient point, realized that salient point is arranged to define arbitrarily, better must realize the interconnected of chip and carrier; Make more crypto set of I/O, cost is lower.
To achieve these goals, the technical scheme that adopts of the present invention: a kind of manufacture craft flow process of the carrier-free formula packaging part based on framework is following:
1, attenuate; According to actual needs wafer thickness is carried out reduction processing;
2, scribing; The wafer of thickness more than 150 μ m adopts common Q FN scribing process, and the wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
3, go up core; Adopt core on the bonding die glue;
4, do metal salient point; Method with planting ball is made metal salient point on frame carrier;
5, pressure welding; Keystroke zygonema between chip and metal salient point, metal salient point;
6, plastic packaging;
7, remove frame carrier; With the method for corrosion or abrasive dust frame carrier is removed behind the product plastic packaging;
8, cutting.
Described 3,5,6,8 steps are adopted conventional QFN/DFN technology.
Beneficial effect of the present invention: adopt frame-generic can carry out the production flow process, need not the multi-processing frame carrier, shorten design and fabrication cycle, reduce cost; Arrange and the I/O number does not receive Frame Design and makes restriction at salient point, realized that salient point is arranged to define arbitrarily, better must realize the interconnected of chip and carrier; Make more crypto set of I/O, cost is lower.
Description of drawings
The individual pen finished product profile that Fig. 1 the present invention processes
Many circles finished product profile that Fig. 2 the present invention processes
Among the figure: 1-lead frame, 2-bonding die glue, 3-chip, 4-metal salient point A, 5-bonding line, 6-plastic-sealed body, 7-metal salient point B.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further specified, understand to make things convenient for the technical staff.
A kind of manufacture craft flow process of the carrier-free formula packaging part based on framework is following:
1, attenuate; According to actual needs wafer thickness is carried out reduction processing;
2, scribing; The wafer of thickness more than 150 μ m adopts common Q FN scribing process, and the wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
3, go up core; Adopt core on the bonding die glue;
4, do metal salient point; Method with planting ball is made metal salient point on frame carrier;
5, pressure welding; Keystroke zygonema between chip and metal salient point, metal salient point;
6, plastic packaging;
7, remove frame carrier; With the method for corrosion or abrasive dust frame carrier is removed behind the product plastic packaging;
8, cutting.
Described 3,5,6,8 steps are adopted conventional QFN/DFN technology.
Embodiment 1 makes the individual pen packaging part:
A kind of manufacture craft flow process of the carrier-free formula packaging part based on framework is following:
1, attenuate; According to actual needs wafer thickness is carried out reduction processing;
2, scribing; The wafer of thickness more than 150 μ m adopts common Q FN scribing process,
3, go up core; Adopt core on the bonding die glue 2;
4, be metal salient point A4; Method with planting ball is made metal salient point A4 on frame carrier;
5, pressure welding; Keystroke zygonema 5 between chip 3 and metal salient point A4;
6, plastic packaging;
7, remove frame carrier 1; With corroding method frame carrier 1 is removed behind the product plastic packaging;
8, cutting.
Described 3,5,6,8 steps are adopted conventional QFN/DFN technology.
As shown in Figure 1: the individual pen packaging part of making comprises lead frame 1, bonding die glue 2, chip 3, metal salient point A4, bonding line 5, plastic-sealed body 6; Its chips 3 links to each other through bonding die glue 2 with lead frame 1; Bonding line 5 is directly got on the metal salient point A4 from chip 3; On the lead frame 1 bonding die glue 2; Be chip 3 on the bonding die glue 2, the bonding wire between solder joint on the chip 3 and metal salient point A4 is a bonding line 5, and plastic-sealed body 6 has surrounded the integral body that lead frame 1, bonding die glue 2, chip 3, metal salient point A4, bonding line 5 have constituted circuit; The bonding line 5 of 6 pairs of chips of plastic-sealed body 3 and metal salient point A4 has played support and protective effect, and chip 3, metal salient point A4, bonding line 5, lead frame 1 have constituted the power supply and the signalling channel of circuit.
Embodiment 2 makes many circle packaging parts:
A kind of manufacture craft flow process of the carrier-free formula packaging part based on framework is following:
1, attenuate; According to actual needs wafer thickness is carried out reduction processing;
2, scribing; The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
3, go up core; Adopt core on the bonding die glue 2;
4, be metal salient point A4, metal salient point B7; Method with planting ball is made metal salient point A4, metal salient point B7 on frame carrier;
5, pressure welding; Keystroke zygonema 5 between chip and metal salient point A4, metal salient point A4 and metal salient point B7;
6, plastic packaging;
7, remove frame carrier 1; Method with abrasive dust behind the product plastic packaging is removed frame carrier 1;
8, cutting.
Described 3,5,6,8 steps are adopted conventional QFN/DFN technology.
As shown in Figure 2: the carrier-free formula of making is enclosed packaging part more and is comprised: lead frame 1, bonding die glue 2, chip 3, metal salient point A4, bonding line 5, plastic-sealed body 6, metal salient point B7; Its chips 3 links to each other through bonding die glue 2 with lead frame 1; Bonding line 5 is directly got on metal salient point A4 and the metal salient point B7 from chip 3; On the lead frame 1 bonding die glue 2; It on the bonding die glue 2 chip 3; Bonding wire between solder joint on the chip 3 and metal salient point A4, metal salient point B7 is a bonding line 5; Plastic-sealed body 6 has surrounded the integral body that lead frame 1, bonding die glue 2, chip 3, metal salient point A4, metal salient point B7, bonding line 5 have constituted circuit, and plastic-sealed body 6 pairs of chips 3 have played support and protective effect with the bonding line 5 of metal salient point A4, metal salient point B7, and chip 3, metal salient point A4, metal salient point B7, bonding line 5, lead frame 1 have constituted the power supply and the signalling channel of circuit.
The present invention describes through accompanying drawing; Without departing from the present invention; Can also carry out various conversion and be equal to replacement patent of the present invention; Therefore, patent of the present invention is not limited to disclosed practical implementation process, and should comprise the whole embodiments that fall in the Patent right requirement scope of the present invention.
Claims (2)
1. manufacture craft based on the carrier-free formula packaging part of framework is characterized in that: a kind of manufacture craft flow process of the carrier-free formula packaging part based on framework is following:
(1), attenuate; According to actual needs wafer thickness is carried out reduction processing;
(2), scribing; The wafer of thickness more than 150 μ m adopts common Q FN scribing process, and the wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
(3), go up core; Adopt core on the bonding die glue;
(4), do metal salient point; Method with planting ball is made metal salient point on frame carrier;
(5), pressure welding; Keystroke zygonema between chip and metal salient point, metal salient point;
(6), plastic packaging;
(7), remove frame carrier; With the method for corrosion or abrasive dust frame carrier is removed behind the product plastic packaging;
(8), cutting.
2. the manufacture craft of a kind of carrier-free formula packaging part based on framework according to claim 1 is characterized in that: described (3), (5), (6), (8) step are adopted conventional QFN/DFN technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103068308A CN102832141A (en) | 2012-08-18 | 2012-08-18 | Manufacturing process of carrier-free package based on framework |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103068308A CN102832141A (en) | 2012-08-18 | 2012-08-18 | Manufacturing process of carrier-free package based on framework |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102832141A true CN102832141A (en) | 2012-12-19 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103068308A Pending CN102832141A (en) | 2012-08-18 | 2012-08-18 | Manufacturing process of carrier-free package based on framework |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102832141A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346140A (en) * | 2013-06-10 | 2013-10-09 | 孙青秀 | Package based on silvering technology adopted for frame and manufacturing process of package |
| CN106653625A (en) * | 2017-02-04 | 2017-05-10 | 常州银河世纪微电子股份有限公司 | Manufacturing process for ultra-thin packaged element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050214980A1 (en) * | 2004-03-24 | 2005-09-29 | Shiu Hei M | Land grid array packaged device and method of forming same |
| CN101901788A (en) * | 2009-02-06 | 2010-12-01 | 精工电子有限公司 | Resin molded semiconductor device and manufacture method thereof |
-
2012
- 2012-08-18 CN CN2012103068308A patent/CN102832141A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050214980A1 (en) * | 2004-03-24 | 2005-09-29 | Shiu Hei M | Land grid array packaged device and method of forming same |
| CN101901788A (en) * | 2009-02-06 | 2010-12-01 | 精工电子有限公司 | Resin molded semiconductor device and manufacture method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346140A (en) * | 2013-06-10 | 2013-10-09 | 孙青秀 | Package based on silvering technology adopted for frame and manufacturing process of package |
| CN106653625A (en) * | 2017-02-04 | 2017-05-10 | 常州银河世纪微电子股份有限公司 | Manufacturing process for ultra-thin packaged element |
| CN106653625B (en) * | 2017-02-04 | 2019-03-26 | 常州银河世纪微电子股份有限公司 | The manufacture craft of Ultrathin packaging element |
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Legal Events
| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: CHINA CHIPPACKING TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: SUN QINGXIU Effective date: 20141222 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 710018 XI'AN, SHAANXI PROVINCE TO: 518111 SHENZHEN, GUANGDONG PROVINCE |
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| TA01 | Transfer of patent application right |
Effective date of registration: 20141222 Address after: Longgang District of Shenzhen City, Guangdong province 518111 Pinghu Street Community Ping Wo Flower New Street No. 165 Building 1 floor 105 Hengshun Factory 1, 2-5 floor Applicant after: CHINA CHIPPACKING TECHNOLOGY CO., LTD. Address before: The essence of the door No. 50 Wenjing road 710018 Shaanxi province Weiyang District of Xi'an city 6-2206 room Applicant before: Sun Qingxiu |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20121219 |
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| RJ01 | Rejection of invention patent application after publication |