CN103346135A - Package based on technology that frame is connected through bonding wires and manufacturing process of package - Google Patents
Package based on technology that frame is connected through bonding wires and manufacturing process of package Download PDFInfo
- Publication number
- CN103346135A CN103346135A CN 201310231318 CN201310231318A CN103346135A CN 103346135 A CN103346135 A CN 103346135A CN 201310231318 CN201310231318 CN 201310231318 CN 201310231318 A CN201310231318 A CN 201310231318A CN 103346135 A CN103346135 A CN 103346135A
- Authority
- CN
- China
- Prior art keywords
- chip
- silver coating
- bonding line
- silver
- salient point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000005516 engineering process Methods 0.000 title claims abstract description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052709 silver Inorganic materials 0.000 claims abstract description 43
- 239000004332 silver Substances 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 238000004806 packaging method and process Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000003466 welding Methods 0.000 claims abstract description 14
- 238000005260 corrosion Methods 0.000 claims abstract description 8
- 230000007797 corrosion Effects 0.000 claims abstract description 8
- 238000007747 plating Methods 0.000 claims abstract description 3
- 239000011248 coating agent Substances 0.000 claims description 42
- 238000000576 coating method Methods 0.000 claims description 42
- 230000011664 signaling Effects 0.000 claims description 6
- 238000007796 conventional method Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 2
- 230000000007 visual effect Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 11
- 238000005520 cutting process Methods 0.000 abstract description 3
- 238000012856 packing Methods 0.000 abstract description 3
- 239000000969 carrier Substances 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a package based on the technology that a frame is connected through bonding wires and a manufacturing process of the package. The package comprises a chip, a plastic packaging body, a silver-plated layer and the bonding wires. The silver-plated layer is composed of silver-plated layer sections which are independent from each other, the chip is located on a part of the silver-plated layer, the chip is connected with the portions, without the chip, of the silver-plated layer through the bonding wires, the plastic packaging body wraps the chip, the silver-plated layer and the bonding wires, and the chip, the silver-plated layer and the bonding wires constitute a power source and signal channel of a circuit. The package further comprises metal bumps. The manufacturing process comprises silver plating of the frame, wafer thinning, scribing, assembly of the chip, manufacturing of the metal bumps, pressure welding, plastic packaging, corrosion of the frame, cutting and packing, wherein the step of manufacturing of the metal bumps can be eliminated. According to the package and the manufacturing process thereof, due to the fact that pressure welding is directly conducted on the metal bumps after electrosilvering or the method of direct wiring after electrosilvering is used, design of a frame graph is finished when the frame is manufactured, the manufacturing period is shortened, interconnection of the chip and carriers is achieved better, the higher I/O density is achieved, and cost is lower.
Description
Technical field
The invention belongs to integrated circuit encapsulation technology field, specifically is a kind of packaging part and manufacture craft thereof that adopts the bonding line interconnection technique based on framework.
Background technology
Integrated circuit flat non-pin encapsulation grows up in the generation (digital camera, mobile phone, PC, MP3) along with communication and portable small-sized digital electronic goods in recent years, is applicable to the encapsulation of high frequency, broadband, low noise, high heat conduction, small size, the middle small scale integrated circuit that electrically requires such as high-speed.The encapsulation of integrated circuit flat non-pin has effectively utilized the encapsulated space of terminal pin, thereby has improved packaging efficiency significantly.This encapsulation is because lead-in wire is short and small, the plastic-sealed body size is little, packaging body is thin, can make CPU volume-diminished 30%-50%.So it can provide remarkable electrical property, and outstanding heat dispersion also is provided simultaneously.
Common integrated circuit flat non-pin encapsulation encapsulation mainly has the following disadvantages: the integrated circuit flat non-pin encapsulating products of frame carrier need be according to chip size and circuit communication design framework figure, framework is processed into the figure that designs with methods such as corrosion again, design and fabrication cycle are long, and cost is than higher.And present integrated circuit flat non-pin encapsulate serial packaging part salient point arrange and the dense degree of I/O on also because Frame Design and framework manufacturing process and restriction to some extent.
Summary of the invention
In order to overcome the problem that above-mentioned prior art exists, the invention provides a kind of packaging part and manufacture craft thereof that adopts the bonding line interconnection technique based on framework, the present invention is by directly pressure welding on the metal salient point that is implanted with after the electrosilvering, also can by behind the electrosilvering directly the method for routing realize that the design of framework figure just finishes at frame manufacture period, shortened fabrication cycle, better must realize the interconnected of chip and carrier, make more crypto set of I/O, cost is lower.
A kind of packaging part based on framework employing bonding line interconnection technique includes chip, plastic-sealed body, silver coating and bonding line.Described silver coating is separate silver-plated interval, on the part silver coating chip is arranged, the part silver coating of described chip and chipless is connected by bonding line, and plastic-sealed body has surrounded chip, silver coating and bonding line, and chip, silver coating and bonding line have constituted power supply and the signalling channel of circuit.
A kind of packaging part based on framework employing bonding line interconnection technique also includes metal salient point.Described silver coating is separate silver-plated interval, on the part silver coating chip is arranged, on the part silver coating metal salient point is arranged, described chip is connected by bonding line with metal salient point, plastic-sealed body has surrounded metal salient point, chip, silver coating and bonding line, and metal salient point, chip, silver coating and bonding line have constituted power supply and the signalling channel of circuit.
A kind of technological process of the packaging part that adopts the bonding line interconnection technique based on framework is as follows: framework is silver-plated → wafer attenuate → scribing → go up core → do metal salient point → pressure welding → plastic packaging → corrosion framework → cutting → packing.
The described flow process of doing metal salient point can be omitted.
Description of drawings
Fig. 1 is the lead frame profile;
Fig. 2 is the silver-plated back of lead frame profile;
Fig. 3 is profile behind the core on the product;
Fig. 4 plants profile behind the metal salient point for framework;
Fig. 5 is profile after the product pressure welding;
Fig. 6 is profile behind the product plastic packaging;
Fig. 7 for product corrosion framework after profile;
Fig. 8 is the finished product profile;
Fig. 9 does not have profile after the metal salient point pressure welding for product;
Figure 10 does not have profile behind the metal salient point plastic packaging for product;
Figure 11 does not have profile behind the metal salient point corrosion framework for product;
Figure 12 does not have metal salient point finished product profile for product.
Among the figure, 1 is that lead frame, 2 is that metal salient point, 3 is that chip, 4 is that plastic-sealed body, 5 is that silver coating, 6 is bonding line.
Embodiment
The present invention is described further below in conjunction with description of drawings.
As shown in figure 12, a kind of packaging part based on framework employing bonding line interconnection technique includes chip 3, plastic-sealed body 4, silver coating 5 and bonding line 6.Described silver coating 5 is separate silver-plated interval, chip 3 is arranged on the part silver coating 5, the part silver coating 5 of described chip 3 and chipless 3 is connected by bonding line 6, plastic-sealed body 4 has surrounded chip 3, silver coating 5 and bonding line 6, and chip 3, silver coating 5 and bonding line 6 have constituted power supply and the signalling channel of circuit.
As shown in Figure 8, a kind of packaging part based on framework employing bonding line interconnection technique also includes metal salient point 2.Described silver coating 5 is separate silver-plated interval, chip 3 is arranged on the part silver coating 5, metal salient point 2 is arranged on the part silver coating 5, described chip 3 is connected by bonding line 6 with metal salient point 2, plastic-sealed body 4 has surrounded metal salient point 2, chip 3, silver coating 5 and bonding line 6, and metal salient point 2, chip 3, silver coating 5 and bonding line 6 have constituted power supply and the signalling channel of circuit.
A kind of technological process of the packaging part that adopts the bonding line interconnection technique based on framework is as follows: framework is silver-plated → wafer attenuate → scribing → go up core → do metal salient point → pressure welding → plastic packaging → corrosion framework → cutting → packing.
The described flow process of doing metal salient point can be omitted.
To shown in Figure 12, a kind of adopt the manufacture craft of the packaging part of bonding line interconnection technique based on framework as Fig. 1, carry out according to following steps:
The first step, framework are silver-plated: at the silver coating 5 of visuals plating one deck 3 ~ 20um of lead frame 1.In frame manufacture producer manufacturing process, design the figure of framework earlier, silver-plated then.Adopt that frame-generic is silver-plated can to carry out production, need not the multi-processing frame carrier, can realize circuit communication, shorten design and fabrication cycle, reduce cost.
Second step, wafer attenuate: thickness thinning 50 μ m～200 μ m, roughness Ra 0.10mm～0.05mm.
The 3rd step, scribing: the above wafer of 150 μ m is with common integrated circuit flat packaging part scribing process, but thickness uses double-pole scribing machine and technology thereof at the following wafer of 150 μ m.
The 4th goes on foot, goes up core: chip 3 is communicated with by silver coating 5 and lead frame 1.
The 5th the step, do metal salient point, pressure welding: the part at lead frame 1 silver coating 5 is done metal salient point 2, then in the direct keystroke zygonema 6 of the welding zone of chip 3 to metal salient point 2, need not the multi-processing frame carrier, can realize circuit communication.
This step can be under the situation of abridged, direct silver coating 5 pressure welding bonding lines 6 formation circuit communications from chip 3 nips to lead frame 1 behind the core on the product.
The 6th step, the same conventional method of plastic packaging.
The 7th step, framework corrosion: use chemical solution to erode whole lead frames 1 behind the product plastic packaging, the silver coating 5 that exposes can be realized line conduction.This method can shorten design and fabrication cycle, reduces cost.
The 8th goes on foot, cuts, packs same conventional method.
Arrange and the I/O number is not subjected to Frame Design and makes under the prerequisite of restriction at salient point, the present invention is by the method for core in the upside-down mounting after the electrosilvering, realized that the framework graphic designs can just finish at frame manufacture period, shortened fabrication cycle, better realize the interconnected of chip and carrier, make more crypto set of I/O, cost is lower.
Claims (4)
1. one kind is adopted the packaging part of bonding line interconnection technique based on framework, and it is characterized in that: described packaging part includes chip (3), plastic-sealed body (4), silver coating (5) and bonding line (6); Described silver coating (5) is separate silver-plated interval, chip (3) is arranged on the part silver coating (5), the part silver coating (5) of described chip (3) and chipless (3) is connected by bonding line (6), plastic-sealed body (4) has surrounded chip (3), silver coating (5) and bonding line (6), and chip (3), silver coating (5) and bonding line (6) have constituted power supply and the signalling channel of circuit.
2. a kind of packaging part that adopts the bonding line interconnection technique based on framework according to claim 1, it is characterized in that: described packaging part also includes metal salient point (2), metal salient point (2) is arranged on the described part silver coating (5), described chip (3) is connected by bonding line (6) with metal salient point (2), plastic-sealed body (4) has surrounded metal salient point (2), chip (3), silver coating (5) and bonding line (6), and metal salient point (2), chip (3), silver coating (5) and bonding line (6) have constituted power supply and the signalling channel of circuit.
3. one kind is adopted the manufacture craft of the packaging part of bonding line interconnection technique based on framework, it is characterized in that: carry out according to following steps: the first step, framework are silver-plated: at the silver coating (5) of visuals plating one deck 3 ~ 20um of lead frame (1); Second step, wafer attenuate: thickness thinning 50 μ m～200 μ m, roughness Ra 0.10mm～0.05mm; The 3rd step, scribing: the above wafer of 150 μ m is with common integrated circuit flat packaging part scribing process, but thickness uses double-pole scribing machine and technology thereof at the following wafer of 150 μ m; The 4th goes on foot, goes up core: chip (3) is communicated with by silver coating (5) and lead frame (1); The 5th step, do metal salient point, pressure welding: do metal salient point (2) in the part of lead frame (1) silver coating (5), then in chip (3) the direct keystroke zygonema of welding zone (6) to the metal salient point (2); The 6th step, the same conventional method of plastic packaging; The 7th step, framework corrosion: erode whole lead frames (1) with chemical solution, expose silver coating (5); The 8th goes on foot, cuts, packs same conventional method.
4. according to claim 3ly a kind ofly adopt the manufacture craft of the packaging part of bonding line interconnection technique based on framework, it is characterized in that: carry out according to following steps: described the 5th step is: pressure welding: the part silver coating (5) of chip (3) and chipless (3) is connected by bonding line (6) pressure welding.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201310231318 CN103346135A (en) | 2013-06-10 | 2013-06-10 | Package based on technology that frame is connected through bonding wires and manufacturing process of package |
| SG2013082201A SG2013082201A (en) | 2013-06-10 | 2013-11-06 | Packaging piece, based on framework and adopting bonding wire connecting technology, and manufacturing technology thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201310231318 CN103346135A (en) | 2013-06-10 | 2013-06-10 | Package based on technology that frame is connected through bonding wires and manufacturing process of package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103346135A true CN103346135A (en) | 2013-10-09 |
Family
ID=49280921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201310231318 Pending CN103346135A (en) | 2013-06-10 | 2013-06-10 | Package based on technology that frame is connected through bonding wires and manufacturing process of package |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103346135A (en) |
| SG (1) | SG2013082201A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103560122A (en) * | 2013-08-31 | 2014-02-05 | 华天科技（西安）有限公司 | Frame csp package with bumping optimization technology and production process thereof |
| CN105514079A (en) * | 2015-12-08 | 2016-04-20 | 广东气派科技有限公司 | Integrated circuit package structure and manufacturing technology thereof |
| CN105870100A (en) * | 2015-01-05 | 2016-08-17 | 广东气派科技有限公司 | Ultrathin packaging component and manufacturing technique thereof |
| CN106409689A (en) * | 2016-09-30 | 2017-02-15 | 乐依文半导体(东莞)有限公司 | High-density circuit chip packaging process |
| CN106449427A (en) * | 2016-09-30 | 2017-02-22 | 乐依文半导体(东莞)有限公司 | High-density circuit chip packaging technology |
| CN109599346A (en) * | 2018-12-11 | 2019-04-09 | 杰群电子科技（东莞）有限公司 | A kind of intelligent power mould group processing technology and power modules |
| CN112349673A (en) * | 2020-11-10 | 2021-02-09 | 江西芯世达微电子有限公司 | Ultrathin packaging part based on bonding wire connection and manufacturing process thereof |
-
2013
- 2013-06-10 CN CN 201310231318 patent/CN103346135A/en active Pending
- 2013-11-06 SG SG2013082201A patent/SG2013082201A/en unknown
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103560122A (en) * | 2013-08-31 | 2014-02-05 | 华天科技（西安）有限公司 | Frame csp package with bumping optimization technology and production process thereof |
| CN105870100A (en) * | 2015-01-05 | 2016-08-17 | 广东气派科技有限公司 | Ultrathin packaging component and manufacturing technique thereof |
| CN105514079A (en) * | 2015-12-08 | 2016-04-20 | 广东气派科技有限公司 | Integrated circuit package structure and manufacturing technology thereof |
| CN106409689A (en) * | 2016-09-30 | 2017-02-15 | 乐依文半导体(东莞)有限公司 | High-density circuit chip packaging process |
| CN106449427A (en) * | 2016-09-30 | 2017-02-22 | 乐依文半导体(东莞)有限公司 | High-density circuit chip packaging technology |
| CN106409689B (en) * | 2016-09-30 | 2019-11-01 | 乐依文半导体(东莞)有限公司 | High-density circuit chip packaging process |
| CN109599346A (en) * | 2018-12-11 | 2019-04-09 | 杰群电子科技（东莞）有限公司 | A kind of intelligent power mould group processing technology and power modules |
| CN112349673A (en) * | 2020-11-10 | 2021-02-09 | 江西芯世达微电子有限公司 | Ultrathin packaging part based on bonding wire connection and manufacturing process thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| SG2013082201A (en) | 2015-01-29 |
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Legal Events
| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: CHINA CHIPPACKING TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: SUN QINGXIU Effective date: 20141104 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 710018 XI'AN, SHAANXI PROVINCE TO: 518111 SHENZHEN, GUANGDONG PROVINCE |
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| TA01 | Transfer of patent application right |
Effective date of registration: 20141104 Address after: Longgang District of Shenzhen City, Guangdong province 518111 Pinghu Street Community Ping Wo Flower New Street No. 165 Building 1 floor 105 Hengshun Factory 1, 2-5 floor Applicant after: CHINA CHIPPACKING TECHNOLOGY CO., LTD. Address before: The essence of the door No. 50 Wenjing road 710018 Shaanxi province Weiyang District of Xi'an city 6-2206 room Applicant before: Sun Qingxiu |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20131009 |
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| RJ01 | Rejection of invention patent application after publication |