CN106449427A - High-density circuit chip packaging technology - Google Patents
High-density circuit chip packaging technology Download PDFInfo
- Publication number
- CN106449427A CN106449427A CN201610877442.3A CN201610877442A CN106449427A CN 106449427 A CN106449427 A CN 106449427A CN 201610877442 A CN201610877442 A CN 201610877442A CN 106449427 A CN106449427 A CN 106449427A
- Authority
- CN
- China
- Prior art keywords
- chip
- circuit
- circuits
- plating
- protective layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012536 packaging technology Methods 0.000 title abstract 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052802 copper Inorganic materials 0.000 claims abstract description 35
- 239000010949 copper Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000013078 crystal Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000011241 protective layer Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 15
- 238000003466 welding Methods 0.000 claims abstract description 12
- 239000011248 coating agent Substances 0.000 claims description 23
- 238000000576 coating method Methods 0.000 claims description 23
- 238000007747 plating Methods 0.000 claims description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- 239000003292 glue Substances 0.000 claims description 8
- 238000004806 packaging method and process Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 5
- 238000004026 adhesive bonding Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000001746 injection moulding Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004568 cement Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000011112 process operation Methods 0.000 description 2
- 238000004513 sizing Methods 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention provides a high-density circuit chip packaging technology, and relates to the technical field of a semiconductor packaging technology. The high-density circuit chip packaging technology comprises the following steps of electroplating, namely carrying out electroplating on the front surface of a copper substrate to form electroplated layers according to patterns of circuits of a chip and adopting the electroplated layers as the circuits; crystal bonding for energization, bonding crystal grains and bonding wires between the crystal grains and welding positions of the corresponding circuits to achieve electric connection; and plastic package, carrying out injection molding on the front surface of the copper substrate to form a plastic protective layer. According to the high-density circuit chip packaging technology provided by the invention, the circuits of the chips are manufactured in an electroplating manner and the high-density circuit chip packaging technology is not a traditional etching method on the copper substrate. Due to the characteristics of an electroplating technology, finer circuits can be manufactured, the circuits of the chip can be designed to be denser, the circuits of the chip can be more flexibly designed and high-density circuits of the chip are achieved.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation.
Background technology
In the existing chip package process with lead frame as substrate, it is the circuit etching chip using copper base, such as
The circuit of fruit chip is simple, density is low, and this kind of technique has no problem.However, for the high chip of complex circuit, density, profit
With copper base come the place's of etching chip circuit the drawbacks of just highlight.If circuit or pin son are too intensive, ensureing size
In the case of increasing not too much, circuit is accomplished by being made very carefully, and the technique etching is limited by copper material thickness bottom and etching factor,
The circuit etching gap of very little cannot be accomplished, which limits the density of the circuit of chip it is impossible to be designed to circuit too intensive,
Can not neatly design chips circuit.
Content of the invention
In view of this, the present invention proposes a kind of high-density line chip package process, and it can make the circuit of chip be designed to
More crypto set, is capable of the circuit of more neatly design chips.
For achieving the above object, the present invention provides technical scheme below.
High-density line chip package process, comprises the following steps：
Plating：Electroplate in copper base front according to the pattern of the circuit of chip and form electrodeposited coating, this electrodeposited coating is as described
Circuit；
Viscous brilliant energising：Bonding crystal grain and between crystal grain and the welding position of described circuit bonding wire to realize electrically connecting；
Plastic packaging：It is molded in copper base front and form plastic protection layer.
In the high-density line chip package process of the present invention, by the way of plating, to make the circuit of chip, rather than
Traditional mode etching on copper base, is therefore no longer limited by copper material thickness bottom and etching factor in etch process, due to electricity
The feature of depositing process, can make thinner circuit, therefore the circuit of chip can be made to be designed to more crypto set it is also possible to more neatly
The circuit of design chips, realizes the high-density line of chip.The circuit of chip includes wire, bonding wire welding position and tin ball bonding position.
It is preferred that plating step is：According to the pattern in die bonder region and the circuit of chip pattern in copper base just
Face plating formed electrodeposited coating, this plating layer segment as described circuit, partly as wafer base；
In viscous crystalline substance energizing step, by die bonder on wafer base.
It is preferred that before plastic packaging step, further comprising the steps of：
Microetch：Slight etching copper base front, the copper part etching off below described electrodeposited coating edge forms lock glue
Groove.
After forming lock glue groove, when being molded in follow-up plastic packaging step, sizing material can flow in lock glue groove, and solidification forms plastic cement
After protective layer, described electrodeposited coating will be clasped, after injection, plastic cement can preferably be combined with leadframe substrate (i.e. electrodeposited coating), keeps away
Exempt from that plastic protection layer and lead frame disengaging occur, plastic protection layer is so securely joined with electrodeposited coating, in follow-up bonding tin
Electrodeposited coating can be avoided during the process operations such as ball to come off it is ensured that encapsulating the reliability of the chip being formed.
It is preferred that microetching step is after the electroplating step, before gluing crystalline substance energizing step.Against corrosion using electrodeposited coating itself
Property it is not necessary to pad pasting, exposed and developed protecting electrodeposited coating.Microetching step before bonding crystal grain and bonding wire, with more reality
May and being worth of operation, will not cause to damage to crystal grain and the line being welded.
It is preferred that after plastic packaging step, further comprising the steps of：
Total eclipse：By whole for copper base etching offs；
Make back-protective layer：Armor coated in the relevant position of chip back, this protective layer is as back-protective layer；
Make outer pin：Make outer pin in the relevant position of chip back, outer pin is connected with the relevant position of described circuit.
It is preferred that described back-protective layer is solder mask, make outer step rapid specifically：Corresponding positions in chip back
Put stickup tin ball as outer pin, tin ball is connected with the relevant position of described circuit.
Brief description
Fig. 1 is the step schematic diagram of the high-density line chip package process of the present invention；
Fig. 2 is the enlarged diagram at A in Fig. 2；
Fig. 3 is the enlarged diagram at B in Fig. 2；
Fig. 4 is the schematic diagram of the part circuit of the chip made using the high-density line chip package process of the present invention.
Reference includes：
Copper base 1, the circuit 2 of chip, wire 21, bonding wire welding position 22, tin ball bonding position 23, wafer base 3, lock glue groove 4, brilliant
Grain 5, wire 6, plastic protection layer 7, solder mask 8, tin ball 9.
Specific embodiment
Below in conjunction with specific embodiment, the present invention is elaborated.
As shown in figure 1, the high-density line chip package process of the present embodiment comprises the steps：
Plating：Form the electrodeposited coating as circuit 2 in copper base 1 front according to the pattern plating of the circuit 2 of chip.Circuit
2 referring to Fig. 4, and circuit 2 includes wire 21 (different from the wire 6 of welding), bonding wire welding position 22 and tin ball bonding position 23, bonding wire welding position 22
For welding lead 6, tin ball bonding position 23 is used for bonding tin ball 9, is succinctly to illustrate technical process in Fig. 1, to the expression of circuit 2 not
Completely, circuit 2 is referring specifically to Fig. 4.In the present embodiment, in this step, formation wafer base 3 also can together be electroplated, specifically,
Electroplate in copper base 1 front according to the pattern of the pattern of crystal grain 5 bonding region (i.e. wafer base 3) and the circuit 2 of chip and formed
Electrodeposited coating, this plating layer segment as described circuit 2, partly as wafer base 3.
A in the corresponding Fig. 1 of plating step, concrete operations can be to stick light-sensitive surface on copper base 1 two sides, then expose,
Development, the pattern of the pattern of the circuit 2 on egative film and crystal grain 5 bonding region is transferred on the light-sensitive surface in copper base 1 front, so
After carry out plating formed electrodeposited coating.
The circuit 2 of chip is made by the way of plating, and the mode of unconventional etching on copper base 1, therefore
No longer it is limited by copper material thickness bottom and etching factor in etch process, due to electroplating technology, thinner circuit 2 can be made,
Therefore the circuit 2 of chip can be made to be designed to more crypto set.Referring to Fig. 4, circuit 2 is made using electroplating technology, can allow wire 21
Location and shape more flexible, can easily shuttle in narrow and small gap between tin ball bonding position 23, therefore, it is possible to more neatly
The circuit 2 of design chips, realizes the high-density line of chip.
It should be noted that formation wafer base 3 also can not be electroplated, to make the position of bonding crystal grain 5 using other modes
Put, for example, paste crystal grain 5 and paste gummed paper using insulation crystal grain, thus can be with designed lines 2 below crystal grain 5, thus realizing
More high density；Or plating forms variously-shaped wafer base 3 at copper base 1 back side, forms wafer base 3 after back of the body erosion.
Made using other modes bonding crystal grain 5 position when, also make accommodation in subsequent process steps, concrete regarding adopts
Depending on which kind of mode is to make the position of bonding crystal grain 5, here is not developed in details in explanation.
Microetch：Slight etching copper base 1 front, the copper part etching off below described electrodeposited coating edge forms lock glue
Groove 4.In conjunction with b and Fig. 2 in Fig. 1, by one layer of copper base 1 front etching off, so that the plating as circuit 2 and wafer base 3
Gap in the lower section at the edge of layer, and this gap is locks glue groove 4.
Viscous brilliant energising：Crystal grain 5 is bonded on wafer base 3, and welding lead between the welding position of crystal grain 5 and circuit 2
6, to realize the electrical connection between crystal grain 5 and circuit 2.As shown in c in Fig. 1.
Plastic packaging：It is molded in copper base 1 front and form plastic protection layer 7.As shown in d in Fig. 1.Sizing material during injection can flow into
Filling lock glue groove 4, forms, after solidification, the structure clasping electrodeposited coating, can clearly see, after injection, plastic cement can be more from Fig. 3
Good is combined with leadframe substrate (i.e. electrodeposited coating), it is to avoid plastic protection layer 7 and departs from lead frame, plastic protection layer 7 with
Electrodeposited coating is so securely joined with, and electrodeposited coating can be avoided to come off it is ensured that encapsulating shape in process operations such as follow-up bonding tin balls 9
The reliability of the chip becoming.
Total eclipse：By whole for copper base 1 etching offs.So circuit 2 can normal work, do not pass through copper base 1 and cause short circuit.This
Outward, because all of copper is all etched, do not have and lead to encapsulating products that the risk of copper and colloid layering occurs because of copper oxidation, make
The reliability of the chip that encapsulation is formed is higher.This step is as shown in e in Fig. 1.
Make back-protective layer：Armor coated in the relevant position of chip back, this protective layer is as back-protective layer.
In the present embodiment, back-protective layer is solder mask 8, is commonly called as green oil.Because copper base 1 is all etched, as circuit 2 and crystalline substance
The electrodeposited coating of round bottom seat 3 just exposes, after coated back surface protective layer, can protection circuit 2 and crystal grain 5.Back-protective layer is not
Cover the whole back side, only cover corresponding position, the position making outer pin need to be reserved, for this reason, when making back-protective layer, first existing
Chip back sticks light-sensitive surface, and then exposure imaging makes to need the position of coated back surface protective layer to expose, and coats weldering afterwards
Connect mask 8, after conventional treatment hardening.
Make outer pin：Make outer pin, specially bonding tin ball 9, the phase of tin ball 9 and circuit 2 in chip back relevant position
Position is answered to connect, to realize the connection of chip and external circuit.
Make back-protective layer and outer pin as shown in the f in Fig. 1.
The above disclosed preferred embodiment being only the invention, can not limit present invention wound with this certainly
The interest field made, the equivalent variations therefore made according to the invention claim, still belong to the invention and covered
Scope.
Claims (6)
1. high-density line chip package process, is characterized in that, comprises the following steps：
Plating：Electroplate in copper base front according to the pattern of the circuit of chip and form electrodeposited coating, this electrodeposited coating is as described circuit；
Viscous brilliant energising：Bonding crystal grain and between crystal grain and the welding position of described circuit bonding wire to realize electrically connecting；
Plastic packaging：It is molded in copper base front and form plastic protection layer.
2. high-density line chip package process according to claim 1, is characterized in that,
Plating step is：According to the pattern of the pattern in die bonder region and the circuit of chip, in copper base front, plating forms electricity
Coating, this plating layer segment as described circuit, partly as wafer base；
In viscous crystalline substance energizing step, by die bonder on wafer base.
3. high-density line chip package process according to claim 1 and 2, is characterized in that, before plastic packaging step, also
Comprise the following steps：
Microetch：Slight etching copper base front, the copper part etching off below described electrodeposited coating edge forms lock glue groove.
4. high-density line chip package process according to claim 3, is characterized in that, microetching step plating step it
Afterwards, before gluing crystalline substance energizing step.
5. high-density line chip package process according to claim 1, is characterized in that, after plastic packaging step, also wraps
Include following steps：
Total eclipse：By whole for copper base etching offs；
Make back-protective layer：Armor coated in the relevant position of chip back, this protective layer is as back-protective layer；
Make outer pin：Make outer pin in the relevant position of chip back, outer pin is connected with the relevant position of described circuit.
6. high-density line chip package process according to claim 5, is characterized in that, described back-protective layer is welding
Mask, makes outer step rapid specifically：Paste tin ball in the relevant position of chip back as outer pin, tin ball and described circuit
Relevant position connects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610877442.3A CN106449427A (en) | 2016-09-30 | 2016-09-30 | High-density circuit chip packaging technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610877442.3A CN106449427A (en) | 2016-09-30 | 2016-09-30 | High-density circuit chip packaging technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106449427A true CN106449427A (en) | 2017-02-22 |
Family
ID=58172015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610877442.3A Pending CN106449427A (en) | 2016-09-30 | 2016-09-30 | High-density circuit chip packaging technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106449427A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110600382A (en) * | 2018-06-12 | 2019-12-20 | 深圳市环基实业有限公司 | Chip packaging process and product |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7064012B1 (en) * | 2004-06-11 | 2006-06-20 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a pillar and a routing line using multiple etch steps |
| US20100029046A1 (en) * | 2008-08-04 | 2010-02-04 | Zigmund Ramirez Camacho | Integrated circuit package system with concave terminal |
| US20100129964A1 (en) * | 2008-11-26 | 2010-05-27 | Infineon Technologies Ag | Method of manufacturing a semiconductor package with a bump using a carrier |
| CN102842515A (en) * | 2011-06-23 | 2012-12-26 | 飞思卡尔半导体公司 | Method for assembling semiconductor device |
| CN103311205A (en) * | 2013-05-16 | 2013-09-18 | 华天科技（西安）有限公司 | Encapsulating piece for preventing chip salient point from being short-circuited and manufacturing process thereof |
| CN103346135A (en) * | 2013-06-10 | 2013-10-09 | 孙青秀 | Package based on technology that frame is connected through bonding wires and manufacturing process of package |
| CN103474406A (en) * | 2013-09-27 | 2013-12-25 | 华天科技（西安）有限公司 | Copper-free flat packaging piece of AAQFN frame product and manufacturing process thereof |
-
2016
- 2016-09-30 CN CN201610877442.3A patent/CN106449427A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7064012B1 (en) * | 2004-06-11 | 2006-06-20 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a pillar and a routing line using multiple etch steps |
| US20100029046A1 (en) * | 2008-08-04 | 2010-02-04 | Zigmund Ramirez Camacho | Integrated circuit package system with concave terminal |
| US20100129964A1 (en) * | 2008-11-26 | 2010-05-27 | Infineon Technologies Ag | Method of manufacturing a semiconductor package with a bump using a carrier |
| CN102842515A (en) * | 2011-06-23 | 2012-12-26 | 飞思卡尔半导体公司 | Method for assembling semiconductor device |
| CN103311205A (en) * | 2013-05-16 | 2013-09-18 | 华天科技（西安）有限公司 | Encapsulating piece for preventing chip salient point from being short-circuited and manufacturing process thereof |
| CN103346135A (en) * | 2013-06-10 | 2013-10-09 | 孙青秀 | Package based on technology that frame is connected through bonding wires and manufacturing process of package |
| CN103474406A (en) * | 2013-09-27 | 2013-12-25 | 华天科技（西安）有限公司 | Copper-free flat packaging piece of AAQFN frame product and manufacturing process thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110600382A (en) * | 2018-06-12 | 2019-12-20 | 深圳市环基实业有限公司 | Chip packaging process and product |
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| C06 | Publication | ||
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170222 |
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| RJ01 | Rejection of invention patent application after publication |