CN106409689B - High-density circuit chip packaging process - Google Patents
High-density circuit chip packaging process Download PDFInfo
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- CN106409689B CN106409689B CN201610871160.2A CN201610871160A CN106409689B CN 106409689 B CN106409689 B CN 106409689B CN 201610871160 A CN201610871160 A CN 201610871160A CN 106409689 B CN106409689 B CN 106409689B
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- electroplated
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- outer foot
- layer
- copper base
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- 238000012858 packaging process Methods 0.000 title abstract 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 53
- 239000010949 copper Substances 0.000 claims abstract description 50
- 229910052802 copper Inorganic materials 0.000 claims abstract description 50
- 239000013078 crystal Substances 0.000 claims abstract description 22
- 238000007747 plating Methods 0.000 claims abstract description 16
- 238000003466 welding Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 238000004806 packaging method and process Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 16
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 13
- 239000011241 protective layer Substances 0.000 claims description 12
- 239000003292 glue Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000009713 electroplating Methods 0.000 abstract description 5
- 238000001746 injection moulding Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000004568 cement Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004513 sizing Methods 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/858—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A high-density circuit chip packaging process relates to the technical field of semiconductor packaging processes, and comprises the following steps: electroplating: electroplating on the front surface of the copper substrate according to the circuit pattern of the chip to form an electroplated layer, wherein the electroplated layer is used as the circuit, and the electroplated layer of the outer pin is electroplated on the back surface of the copper substrate according to the pattern of the outer pin; crystal bonding and electrifying: bonding the crystal grains and welding wires between the crystal grains and welding positions of the circuit to realize electric connection; plastic packaging: forming a plastic protection layer on the front surface of the copper substrate by injection molding; manufacturing an outer leg: the copper substrate is etched from the back surface thereof, and the portions of the copper substrate not covered with the outer leg plating layer are etched away, and the portions of the copper substrate not covered with the outer leg plating layer and the outer leg plating layer serve as outer legs.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation.
Background technique
It is existing using lead frame in the chip package process of substrate, to be the route for etching chip using copper base, such as
The route of fruit chip is simple, density is low, and such technique has no problem.However, the chip high for complex circuit, density, benefit
With copper base come the place's of etching chip route the drawbacks of just highlight.If route or foot son are too intensive, guaranteeing size
In the case where not increasing excessively, route just needs to be made very thin, and the technique etched is limited by copper material thickness bottom and etching factor,
Route can not be designed too intensive which limits the density of the route of chip by the circuit etching gap that can not accomplish very little,
Cannot neatly design chips route.
Summary of the invention
In view of this, the present invention proposes a kind of high-density line chip package process, the route of chip can be made to be designed
More crypto set is capable of the route of more flexible ground design chips.
To achieve the above object, the present invention provides following technical scheme.
High-density line chip package process, comprising the following steps:
Plating: being electroplated to form electroplated layer according to the pattern of the route of chip in copper base front, described in electroplated layer conduct
Route is electroplated to form outer foot electroplated layer according to the pattern of outer foot in copper-based back；
Viscous brilliant energization: it is bonded crystal grain and bonding wire is electrically connected between crystal grain and the welding position of the route with realizing；
Plastic packaging: it is molded to form plastic protection layer in copper base front；
It makes outer foot: from copper base back etched copper base, the part of copper base not covered by outer foot electroplated layer being lost
It goes, the part not being etched of copper base covered by outer foot electroplated layer and outer foot electroplated layer are as outer foot.
In high-density line chip package process of the invention, the route of chip is made by the way of plating, rather than
Traditional mode etched on copper base, therefore it is no longer limited by copper material thickness bottom and etching factor in etch process, due to electricity
The characteristics of depositing process, can make thinner route, therefore the route of chip can be made to be designed more crypto set, also can more flexiblely
The route of design chips realizes the high-density line of chip.The route of chip includes conducting wire, bonding wire welding position and outer foot connection position.
Preferably, in plating step, according to the pattern and chip in die bonder region route pattern copper base just
Face is electroplated to form electroplated layer, which is partially used as wafer pedestal as the route；
In viscous crystalline substance energizing step, by die bonder on wafer pedestal.
Preferably, before plastic packaging step, it is further comprising the steps of:
Microetch: the copper part etching off below the electroplated layer edge is formed lock glue by slight etching copper base front
Slot.
After forming lock glue groove, when being molded in subsequent plastic packaging step, sizing material can be flowed into lock glue groove, and solidification forms plastic cement
After protective layer, the electroplated layer will be clasped, after injection molding, plastic cement can be tied preferably with leadframe substrate (i.e. positive electroplated layer)
It closes, avoids the occurrence of plastic protection layer and lead frame is detached from, plastic protection layer is securely joined in this way with electroplated layer, guarantees encapsulation shape
At chip reliability.
Preferably, microetching step is after the electroplating step, before viscous crystalline substance energizing step.Utilize the against corrosion of electroplated layer itself
Property, pad pasting, exposure and imaging are not needed to protect electroplated layer.Microetching step is before bonding crystal grain and bonding wire, with more practical
The possibility and value of operation will not cause to damage to crystal grain and the line welded.
Preferably, after the outer step of production is rapid, it is further comprising the steps of:
Production back-protective layer: being molded to form back-protective layer in chip back, and outer sole end is exposed from back-protective layer.
Detailed description of the invention
Fig. 1 is the step schematic diagram of high-density line chip package process of the invention；
Fig. 2 is the enlarged diagram in Fig. 2 at A；
Fig. 3 is the enlarged diagram in Fig. 2 at B；
Fig. 4 is the schematic diagram using the part route of chip made of high-density line chip package process of the invention.
Appended drawing reference includes:
Copper base 1, the route 2 of chip, conducting wire 21, bonding wire welding position 22, outer foot connection position 23, wafer pedestal 3 lock glue groove 4,
Crystal grain 5, conducting wire 6, plastic protection layer 7, back-protective layer 8, outer foot electroplated layer 9, outer foot 10.
Specific embodiment
It elaborates below in conjunction with specific embodiment to the present invention.
As shown in Figure 1, the high-density line chip package process of the present embodiment includes the following steps:
Plating: the electroplated layer to be formed as route 2 is electroplated according to the pattern of the route 2 of chip in 1 front of copper base.Route
2 referring to fig. 4, and route 2 includes conducting wire 21 (different from the conducting wire 6 of welding), bonding wire welding position 22 and outer foot connection position 23, bonding wire welding position
22 are used for welding lead 6, and outer foot connection position 23 is for connecting outer foot 10, it should be noted that is succinctly to show technique mistake in Fig. 1
Journey, it is not necessarily complete to route 2 and its with the expression of the relationship of outer foot 10, route 2 referring specifically to Fig. 4, outer foot connection position 23
Lower section is fabricated to outer foot 10.It is electroplated to form outer foot electroplated layer 9 according to the pattern of outer foot 10 at 1 back side of copper base.In the present embodiment,
In this step, also wafer pedestal 3 can be formed in 1 front plating of copper base together, specifically, (i.e. according to 5 bonding region of crystal grain
Wafer pedestal 3) pattern and the pattern of route 2 of chip form electroplated layer in the plating of the front of copper base 1, which makees
For the route 2, it is partially used as wafer pedestal 3.
A in plating step corresponding diagram 1, concrete operations can be to stick light-sensitive surface on 1 two sides of copper base, then expose,
Development, the pattern of 5 bonding region of the pattern of the route 2 on egative film and crystal grain is transferred on the positive light-sensitive surface of copper base 1, will
The pattern of outer foot 10 on egative film is transferred on the light-sensitive surface at 1 back side of copper base, is then carried out plating and is formed electroplated layer.
Make the route 2 of chip by the way of plating, and the unconventional mode etched on copper base 1, therefore
It is no longer limited by copper material thickness bottom and etching factor in etch process, the characteristics of due to electroplating technology, thinner route 2 can be made,
Therefore can make the route 2 of chip design more crypto set and flexibly.Referring to fig. 4, route 2, Neng Gourang is made of electroplating technology
The location and shape of conducting wire 21 are more flexible, in the narrow gap between outer foot link bit 23 that can easily shuttle, therefore can be more
The route 2 for adding neatly design chips, realizes the high-density line of chip.
It should be noted that can not also be electroplated to form wafer pedestal 3, the position of bonding crystal grain 5 is made of other modes
Set, such as paste crystal grain 5 and paste gummed paper using insulation crystal grain, thus can with designed lines 2 in crystal grain 5 in the following, to realizing
More high density；Or plating forms wafer pedestal 3 of various shapes at 1 back side of copper base, forms wafer pedestal 3 after back erosion.
It when making the position of bonding crystal grain 5 using other modes, is also adaptively adjusted in subsequent process steps, specific view uses
Depending on position of which kind of mode to make bonding crystal grain 5, explanation is not developed in details herein.
Microetch: 1 front of slight etching copper base, by the copper part below the electroplated layer (positive electroplated layer) edge
Etching off forms lock glue groove 4.In conjunction with the b and Fig. 2 in Fig. 1, by one layer of 1 front etching off of copper base, to make as route 2 and crystalline substance
There is gap below the edge of the electroplated layer of round bottom seat 3, which is to lock glue groove 4.
Viscous brilliant energization: crystal grain 5 is bonded on wafer pedestal 3, and the welding lead between crystal grain 5 and the welding position of route 2
6, to realize being electrically connected between crystal grain 5 and route 2.As shown in figure 1 shown in c.
Plastic packaging: plastic protection layer 7 is formed in 1 front injection molding of copper base.As shown in figure 1 shown in d.Sizing material when injection molding can flow into
Filling lock glue groove 4, forms the structure for clasping electroplated layer, can clearly see from Fig. 3, after injection molding, plastic cement can be more after solidification
Good combines with leadframe substrate (i.e. electroplated layer), avoids the occurrence of plastic protection layer 7 and lead frame is detached from, guarantee what encapsulation was formed
The reliability of chip.
Make outer foot: from 1 back etched copper base 1 of copper base, by the portion of copper base 1 not covered by outer foot electroplated layer 9
Divide etching off, the part not being etched of copper base 1 covered by outer foot electroplated layer 9 and outer foot electroplated layer 9 are used as outer foot 10.Such as
In Fig. 1 shown in e.It is electroplated to form outer foot electroplated layer 9 using the corrosion stability of electroplated layer, while at the back side of copper base 1, etch later
Fall the part of copper base 1 not covered by outer foot electroplated layer 9, thus production forms outer foot 10, this is to be different from traditional viscous tin
The outer foot production method of another kind of ball during manufacturing chip, reduces processing step without viscous tin ball.
Production back-protective layer: being molded to form back-protective layer 8 in chip back, and outer 10 bottom end of foot is from back-protective layer 8
Middle exposing.As shown in figure 1 shown in f.When due to making outer foot 10, copper base 1 is by part etching off, as route 2 and wafer pedestal 3
Electroplated layer be possible to have exposed (actual conditions might not be as shown in fig. 1), after making back-protective layer, can protect
Route 2 and crystal grain 5.
Above disclosed is only the preferred embodiment of the invention, cannot limit wound of the present invention certainly with this
The interest field made, therefore according to equivalent variations made by the invention claim, still belong to the invention and is covered
Range.
Claims (4)
1. high-density line chip package process, characterized in that the following steps are included:
Plating: being electroplated to form electroplated layer according to the pattern of the route of chip in copper base front, the electroplated layer as the route,
Route includes conducting wire, bonding wire welding position and outer foot connection position, and the conducting wire one terminates the bonding wire welding position, another termination outer foot
Connection position is electroplated to form outer foot electroplated layer, wherein make the photosensitive of the electroplated layer according to the pattern of outer foot in copper-based back
With the pattern of the route on film；
Viscous brilliant energization: it is bonded crystal grain and bonding wire is electrically connected between crystal grain and the bonding wire welding position with realizing；
Plastic packaging: it is molded to form plastic protection layer in copper base front；
Make outer foot: from copper base back etched copper base, by the part etching off of copper base not covered by outer foot electroplated layer, copper
The part not being etched of substrate covered by outer foot electroplated layer and outer foot electroplated layer are as outer foot；
Production back-protective layer: being molded to form back-protective layer in chip back, and outer sole end is exposed from back-protective layer.
2. high-density line chip package process according to claim 1, characterized in that
In plating step, it is electroplated to form electricity in copper base front according to the pattern of the route of the pattern and chip in die bonder region
Coating, the electroplated layer part are partially used as wafer pedestal as the route；
In viscous crystalline substance energizing step, by die bonder on wafer pedestal.
3. high-density line chip package process according to claim 1 or 2, characterized in that before plastic packaging step, also
The following steps are included:
Microetch: the copper part etching off below the electroplated layer edge is formed lock glue groove by slight etching copper base front.
4. high-density line chip package process according to claim 3, characterized in that microetching step plating step it
Afterwards, before viscous brilliant energizing step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610871160.2A CN106409689B (en) | 2016-09-30 | 2016-09-30 | High-density circuit chip packaging process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610871160.2A CN106409689B (en) | 2016-09-30 | 2016-09-30 | High-density circuit chip packaging process |
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| CN106409689A CN106409689A (en) | 2017-02-15 |
| CN106409689B true CN106409689B (en) | 2019-11-01 |
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| CN108899308B (en) * | 2018-06-26 | 2020-07-17 | 苏州日月新半导体有限公司 | Semiconductor packaging process and semiconductor package |
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| US7157791B1 (en) * | 2004-06-11 | 2007-01-02 | Bridge Semiconductor Corporation | Semiconductor chip assembly with press-fit ground plane |
| US7838332B2 (en) * | 2008-11-26 | 2010-11-23 | Infineon Technologies Ag | Method of manufacturing a semiconductor package with a bump using a carrier |
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|---|---|---|---|---|
| US7319265B1 (en) * | 2000-10-13 | 2008-01-15 | Bridge Semiconductor Corporation | Semiconductor chip assembly with precision-formed metal pillar |
| CN203260570U (en) * | 2012-09-19 | 2013-10-30 | 孙青秀 | Carrier-free novel package based on frame corrosion bump |
| CN103311205A (en) * | 2013-05-16 | 2013-09-18 | 华天科技（西安）有限公司 | Encapsulating piece for preventing chip salient point from being short-circuited and manufacturing process thereof |
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| CN106409689A (en) | 2017-02-15 |
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Effective date of registration: 20220510 Address after: 523000 No. 7, Zhenyuan West Road, Chang'an Town, Dongguan City, Guangdong Province Patentee after: Liance Youte semiconductor (Dongguan) Co.,Ltd. Address before: 523000 Zhen'an science and Technology Industrial Park, Chang'an Town, Dongguan City, Guangdong Province Patentee before: Lewin semiconductor (Dongguan) Co.,Ltd. |