CN106158742A - A kind of planar salient point type is without Metal Cutting packaging technology and encapsulating structure thereof - Google Patents
A kind of planar salient point type is without Metal Cutting packaging technology and encapsulating structure thereof Download PDFInfo
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- CN106158742A CN106158742A CN201610763616.3A CN201610763616A CN106158742A CN 106158742 A CN106158742 A CN 106158742A CN 201610763616 A CN201610763616 A CN 201610763616A CN 106158742 A CN106158742 A CN 106158742A
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- metal
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 130
- 239000002184 metal Substances 0.000 title claims abstract description 130
- 238000005520 cutting process Methods 0.000 title claims abstract description 51
- 238000012536 packaging technology Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 210000003205 muscle Anatomy 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052737 gold Inorganic materials 0.000 claims abstract description 10
- 239000010931 gold Substances 0.000 claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 239000000047 product Substances 0.000 claims description 24
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- 229910052709 silver Inorganic materials 0.000 claims description 15
- 239000004332 silver Substances 0.000 claims description 15
- 239000011265 semifinished product Substances 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910000831 Steel Inorganic materials 0.000 claims description 8
- 239000010959 steel Substances 0.000 claims description 8
- 241000218202 Coptis Species 0.000 claims description 7
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 7
- 230000009286 beneficial effect Effects 0.000 claims description 6
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 5
- 230000005496 eutectics Effects 0.000 claims description 4
- 238000004220 aggregation Methods 0.000 claims description 3
- 230000002776 aggregation Effects 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- PQTCMBYFWMFIGM-UHFFFAOYSA-N gold silver Chemical compound [Ag].[Au] PQTCMBYFWMFIGM-UHFFFAOYSA-N 0.000 claims description 3
- 238000011112 process operation Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims 1
- 238000002360 preparation method Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 5
- 238000005299 abrasion Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000005022 packaging material Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- -1 routing Sheet Substances 0.000 description 2
- 206010044565 Tremor Diseases 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Materials For Medical Uses (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a kind of planar salient point type without Metal Cutting packaging technology and encapsulating structure thereof, belong to field of semiconductor manufacture.Step is as follows: 1) take metal basal board;2) photopolymer layer is each sticked at metal basal board front, the back side;3) part photopolymer layer removes;4) prepare the Ji Dao of formation, even muscle on metallic substrates, the front of pin field plates front metal layer, even silver-plated at muscle;5) remove photopolymer layer, spill etching region;6) half-etching, forms the half-etched regions of depression on metallic substrates, forms Ji Dao and pin;7) implanted chip;8) routing;9) encapsulating, solidifies afterwards;10) photopolymer layer is again being pasted;11) gold photopolymer layer is removed;12) at the metal basal board back side, region to not covered by dry film carries out total eclipse quarter, and Shi Ji island and pin protrude plastic-sealed body surface;13) photopolymer layer is removed;14) pin metal level is formed;15) cutting.It is high that it can realize reliability, the advantage that tool wear is low.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, it relates to a kind of planar salient point type encapsulates without Metal Cutting
Technique and encapsulating structure thereof.
Background technology
Recent decades, integrated antenna package technology follows the development of integrated circuit always, and people are always little
Best equilibrium point is sought between volume and high-performance.It is encapsulated into the encapsulation of SOP surface patch formula from the DIP plug-in type of the seventies,
QFP Flat type patch to the eighties encapsulates again, and the encapsulation volume of chip is always towards miniaturization, and structural behaviour is not yet
Promote disconnectedly.To the nineties, the appearance that QFN flat-four-side encapsulates without foot formula, it is will be original at packaging body on the basis of QFP
Output pin folding and unfolding around is to package bottom, thus greatly reduces shared space when paster operation.But QFN often has
The problems such as interior foot solder joint shakiness, flash, frequency of doing over again are high, encapsulation yield is on the low side.The encapsulation of FBP planar salient point type is then for improving
Problems in QFN production process and the new packaging form independently developed.
The encapsulation of FBP (Flat Bump Package) planar salient point type is the newest research results of long electricity science and technology.At volume
On, FBP can be less than QFN, thinner, really meets the compact market demand.Its stable unfailing performance, outstanding is low
Impedance, high heat radiation, superconduct performance and meet present IC designer trends simultaneously.Button type pin design unique for FBP also makes
Welding more simply, more firm.But at present discrete device product (DFN QFN FBP), cutting uses resin cutter, and cutting process will produce
Product are separated to be needed to excise substantial amounts of metal material.It is primarily present following not foot point:
A, product are relatively big by stress, cause product layering occur, affect product reliability;
B, excising a large amount of metals due to cutting, cause tool wear very fast, cutter changing frequency is higher.
Chinese patent application, application number 200510040262.1, publication date on February 1st, 2006, disclose a kind of integrated electricity
Road or discrete component flat bump package technics, comprise the following steps that: depletion belongs to substrate material, on the two sides of substrate each
Sticking photopolymer layer, the two sides correspondence at substrate removes part dry film, prepares to form Ji Dao and pin on substrate, accurate on substrate
The standby two sides forming Ji Dao and pin field all plates metal level, removes the remaining dry film of substrate front side, and half-etching, on substrate
Form the partially etching area of depression, relatively form Ji Dao and pin with entering, remove the remaining dry film of substrate back, at Ji Dao front gold
Belonging to layer and implant chip, break metal wire, encapsulate plastic-sealed body, front print, partially etching area remaining part metal is etched again, moulds
Glued membrane is sticked in envelope body front, cutting.Sexuality is strong, best in quality, cost is relatively low, it is smooth and easy to produce in this invention weldering, the suitability is relatively strong,
All puzzlements that multi-chip arrangement is flexible, plastic packaging material will not be occurred to permeate.But when producing, cutting attrition is big, cutting
Time product relatively big by stress, affect product reliability.
Summary of the invention
1. to solve the technical problem that
For product present in prior art, the problem that layering, poor reliability, tool wear are fast, the present invention easily occur
Provide a kind of planar salient point type without Metal Cutting packaging technology and encapsulating structure thereof.It is high that it can realize reliability, and cutter grinds
Damage low advantage.
2. technical scheme
The purpose of the present invention is achieved through the following technical solutions.
1, a kind of planar salient point type is without Metal Cutting packaging technology, and its step is as follows:
1) one piece of metal basal board is taken;
2) photopolymer layer is each sticked at metal basal board front, the back side to protect follow-up etch process operation;
3) the part photopolymer layer in metal basal board front is removed, prepare on metallic substrates to form Ji Dao, even muscle, pin;
4) prepare the Ji Dao of formation, even muscle, the front of pin field on metallic substrates and plate front metal layer, be beneficial to
During follow-up bonding wire, metal wire pin in chip region and routing is combined closely, even silver-plated for follow-up plated conductive pin at muscle
Tin plating;
5) remove the remaining photopolymer layer in metal basal board upper strata, spill etching region;
6) the dry film region removing step 5 carries out half-etching, forms the half-etched regions of depression on metallic substrates, with
Time relatively form Ji Dao and pin;
7) on the base island front metal layer of metal basal board, carry out implanted chip, form integrated circuit or the row of discrete component
Configuration aggregation semi-finished product;
8) semi-finished product being complete implanted chip operation are carried out routing;
9) encapsulating, solidifies afterwards;
10) photopolymer layer is again pasted at the metal basal board back side;
11) photopolymer layer at the metal basal board half-etched regions back side is removed, to expose the region of follow-up needs etching;
12) at the metal basal board back side, region to not covered by dry film carries out total eclipse quarter, and Shi Ji island and pin protrude plastic packaging
Surface;
13) remove the remaining photopolymer layer in the metal basal board back side and be beneficial to follow-up electroplating technology operation;
14) at the Ji Dao protruded, pin plated metal, pin metal level is formed;
15) carrying out cutting operation after plastic-sealed body front being sticked UV film, product separates.
Further, it is characterised in that: step 7) use eutectic welding load to implant on the front metal layer of base island
Chip.
Further, the front metal layer of Ji Dao and pin uses gold silver, copper, nickel or NiPdAu to belong to.
Further, the semi-finished product of implanted chip operation carry out routing, and the metal wire of routing is gold thread, silver wire, copper cash
Or aluminum steel.
Further, step 4 is silver-plated at even muscle, and on the basis of step 4, plastic-sealed body is leaked outside pin by step 14
Plated metal stannum, forms pin metal level.
A kind of planar salient point type is without Metal Cutting encapsulating structure, including foot bearing base, core in chip bearing substrate, routing
Sheet, metal wire and plastic-sealed body, described chip bearing substrate includes Ji Dao and base island front metal layer, in described routing
Foot bearing base includes the front metal layer of pin and pin, even has metal level on muscle, the front metal of chip bearing substrate
Implant chip, chip front side and pin front metal layer on Ceng to be connected with metal wire two ends respectively and make encapsulating structure semi-finished product,
Encapsulating structure semi-finished product front and neighboring plastic-sealed body are encapsulated, and the back side of Bing Shiji island and pin protrudes from plastic packaging body surface
Face, the protrusion Ji Dao of plastic-sealed body, pin surface are coated with pin metal level.
Further, described pin metal level is tin layers, and company's muscle of chip is silver layer.Cutting is had only to when cutting
Stannum and silver, due to stannum and silver soft, cutting stress is little, and cutting abrasion is little, and chip reliability improves.
Further, the front metal layer of Ji Dao and pin is gold, silver, copper, nickel or nickel palladium.Capsulation material and gold, silver,
Copper, nickel or nickel palladium binding ability are good, it is not easy to cause layering.
Further, the metal wire that chip is connected with pin routing is gold thread, silver wire, copper cash or aluminum steel.Material is lazy
Property material, the holding time is long, and conductivity and thermal diffusivity are good.
3. beneficial effect
Compared to prior art, it is an advantage of the current invention that:
(1) using this programme, product is through operation 10,11,12,13, and all Copper base material are all corroded, and cuts in operation 15
Cut process, belong to without Metal Cutting, directly the metallic substrates of chip chamber is first removed, when cutting separating chips, cutter
Have only to cut plastic packaging material, suffered by cutting process product stress reduce by more than 90%, it is to avoid product occur layering, improve product
Reliability;
(2) having only to when cutting cut stannum and silver, owing to stannum and silver ground are soft, cutting stress is little, and cutting is worn and torn little, core
Sheet reliability improves, it is possible to reduce the abrasion of cutting tool;
(3) original cutting resin cutter is readily modified as steel edge cutting, and cutting process product surface is more smooth, tool wear
Reduction can use the cutter that mesh number is bigger, and cutter mesh number is the biggest, and chip is less, cutting process product surface more light
Sliding, chip is less, and product design product design more attractive in appearance is more attractive in appearance;
(4) eutectic welding load is used so that chip is installed more faster, and efficiency is high, good reliability;
(5) prepare the Ji Dao of formation, even muscle, the front of pin field on metallic substrates and plate front metal layer, in order to
When follow-up bonding wire, metal wire pin in chip region and routing is combined closely, even silver-plated for follow-up plated conductive pipe at muscle
Foot is tin plating, and operation is simple, and cost reduces;
(6) front metal layer of Ji Dao and pin is gold, silver, copper, nickel or nickel palladium, capsulation material and gold, silver, copper, nickel or
Nickel palladium binding ability is good, it is not easy to cause layering;
(7) metal wire that chip is connected with pin routing is gold thread, silver wire, copper cash or aluminum steel, and material is inert material, protects
Time of depositing is long, and conductivity and thermal diffusivity are good.
Accompanying drawing explanation
Chip structure schematic diagram after each operation of Fig. 1-9 respectively this programme step 1-9;
Figure 10 is chip structure schematic diagram after step this programme 10,11,12,13 operation;
Figure 11 is chip structure schematic diagram after step this programme 14 operation;
Figure 12 is chip structure schematic diagram after step this programme 15 operation;
Figure 13 is chip structure schematic diagram after prior art step 6 operation;
Figure 14 is chip structure schematic diagram after prior art step 10,11,12,13 operations;
Figure 15 is chip structure schematic diagram after prior art step 14 operation;
Figure 16 is chip structure schematic diagram after prior art step 15 operation.
Label declaration in figure:
1, metal basal board;2, photopolymer layer;3, front metal layer;4, etching region;5, pin;6, Ji Dao;7, chip;8, plastic packaging
Body;9, pin metal level.
Detailed description of the invention
Below in conjunction with Figure of description and specific embodiment, the present invention is described in detail.
Embodiment 1
Such as Fig. 1-12, a kind of planar salient point type is without Metal Cutting packaging technology, and its step is as follows:
1) one piece of metal basal board 1 is taken;
2) in metal basal board 1 front, the back side each stick photopolymer layer 2 to protect follow-up etch process operation;
3) the part photopolymer layer 2 in metal basal board 1 front is removed, metal basal board 1 prepares form base island 6, even muscle, draw
Foot 5;
4) on metal basal board 1, prepare the base island 6 of formation, even muscle, the front in pin 5 region plate front metal layer 3, base
The front metal layer 3 of island 6 and pin 5 uses gold, silver, copper, nickel or NiPdAu to belong to.It is beneficial to metal wire and chip during follow-up bonding wire
In district and routing, pin combines closely, even silver-plated tin plating for follow-up plated conductive pin at muscle;
5) remove the remaining photopolymer layer in metal basal board 1 upper strata 2, spill etching region 4;
6) the dry film region removing step 5 carries out half-etching, forms the half-etched regions of depression on metal basal board 1,
The most relatively form base island 6 and pin 5;
7) on base island 6 front metal layer 3 of metal basal board 1, carry out chip 7 to implant, form integrated circuit or discrete component
Array type aggregation semi-finished product;Eutectic welding load is used to implant chip 7.
8) semi-finished product being complete chip 7 and implanting operation are carried out routing;The metal wire of routing is gold thread, silver wire, copper
Line or aluminum steel
9) encapsulating, solidifies afterwards;
10) photopolymer layer 2 is again pasted in Metal Substrate backboard 1 face;
11) photopolymer layer 2 at the metal basal board 1 half-etched regions back side is removed, to expose the region of follow-up needs etching;
12) at metal basal board 1 back side, region to not covered by dry film carries out total eclipse quarter, and Shi Ji island 6 and pin 5 protrude to be moulded
Envelope body 8 surface;
13) remove the remaining photopolymer layer in metal basal board 1 back side 2 and be beneficial to follow-up electroplating technology operation;
14) at the base island 6 protruded, pin (5) plated metal, pin metal level 9 is formed;Silver-plated at plastic-sealed body connecting at muscle
The pin plated metal stannum that leaks outside of 8, forms pin metal level 9.
15) carrying out cutting operation after plastic-sealed body 8 front being sticked UV film, product separates.
Such as Figure 13, in prior art, 6 steps only carry out pin and Ji Dao plating;Such as Figure 14,10-13 step in prior art
Part metals is only removed in original etching, and this programme removes all unwanted copper materials.Such as Figure 15, in prior art, 14 steps are with gold
Belonging to base material is that even pin, the Ji Dao of product are electroplated by muscle.Form chip as shown in figure 16.Through our scheme, product
Through operation 10,11,12,13, all Copper base material are all corroded, and at operation 15 cutting process, belong to without Metal Cutting, directly
The metallic substrates of chip chamber first being removed, when cutting separating chips, cutter have only to cut plastic packaging material, cutting process product
Suffered stress reduces by more than 90%, it is to avoid layering occurs in product, improves product reliability;Have only to when cutting cut stannum
And silver, due to stannum and silver soft, cutting stress is little, and cutting abrasion is little, and chip reliability improves, it is possible to reduce cutting tool
Abrasion.
Embodiment 2
A kind of planar salient point type is without Metal Cutting encapsulating structure, including foot bearing base, core in chip bearing substrate, routing
Sheet 7, metal wire and plastic-sealed body 8, described chip bearing substrate includes base island 6 and base island front metal layer 3, and described beats
In line, foot bearing base includes the front metal layer 3 of pin 5 and pin, even has metal level 3 on muscle, and chip bearing substrate is just
Implanting chip 7 on face metal level 3, chip 7 front and pin 5 front metal layer 3 are connected with metal wire two ends respectively makes encapsulation
Structure semi-finished product, encapsulating structure semi-finished product front and neighboring plastic-sealed body 8 are encapsulated, Bing Shiji island 6 and the back side of pin 5
Protruding from plastic-sealed body 8 surface, the protrusion base island 6 of plastic-sealed body 8, pin 6 surface are coated with pin metal level 9.Described pin metal
Layer 9 is tin layers, and company's muscle of chip 3 is silver layer.The front metal layer 3 of base island 6 and pin 5 is gold silver, copper, nickel or nickel palladium.Chip 7
The metal wire being connected with pin 5 routing is gold thread, silver wire, copper cash or aluminum steel.
Below being schematically described the invention and embodiment thereof, this description does not has restricted, not
In the case of deviating from the spirit or essential characteristics of the present invention, it is possible to realize the present invention in other specific forms.Institute in accompanying drawing
Show is also one of embodiment of the invention, and actual structure is not limited thereto, any attached in claim
Figure labelling should not limit involved claim.So, if those of ordinary skill in the art is enlightened by it, without departing from
In the case of this creation objective, design the frame mode similar to this technical scheme and embodiment without creative, all should
Belong to the protection domain of this patent.
Claims (9)
1. planar salient point type is without a Metal Cutting packaging technology, and its step is as follows:
1) one piece of metal basal board (1) is taken;
2) in metal basal board (1) front, the back side each stick photopolymer layer (2) to protect follow-up etch process operation;
3) the part photopolymer layer (2) in metal basal board (1) front is removed, form Ji Dao (6) upper preparation of metal basal board (1), connect
Muscle, pin (5);
4) front metal layer is plated in the upper Ji Dao (6) of formation, even muscle, the front in pin (5) region of preparing of metal basal board (1)
(3), silver-plated at company's muscle;
5) remove the remaining photopolymer layer in metal basal board (1) upper strata (2), spill etching region (4);
6) the dry film region removing step 5 carries out half-etching, above forms the half-etched regions of depression at metal basal board (1), with
Time relatively form Ji Dao (6) and pin (5);
7) on Ji Dao (6) front metal layer (3) of metal basal board (1), carry out chip (7) implant, form integrated circuit or discrete
The array type aggregation semi-finished product of element;
8) semi-finished product being complete chip (7) implantation operation are carried out routing;
9) encapsulating, solidifies afterwards;
10) photopolymer layer (2) is again pasted in Metal Substrate backboard (1) face;
11) photopolymer layer (2) at metal basal board (1) the half-etched regions back side is removed, to expose the region of follow-up needs etching;
12) at metal basal board (1) back side, region to not covered by dry film carries out total eclipse quarter, and Shi Ji island (6) and pin (5) protrude
Plastic-sealed body (8) surface;
13) remove the remaining photopolymer layer in metal basal board (1) back side (2) and be beneficial to follow-up electroplating technology operation;
14) at the Ji Dao (6) protruded, pin (5) plated metal, pin metal level (9) is formed;
15) carrying out cutting operation after plastic-sealed body (8) front being sticked UV film, product separates.
A kind of planar salient point type the most according to claim 1 is without Metal Cutting packaging technology, it is characterised in that: step 7)
Ji Dao (6) front metal layer (3) is upper uses eutectic welding load to implant chip (7).
A kind of planar salient point type the most according to claim 1 is without Metal Cutting packaging technology, it is characterised in that: Ji Dao (6)
And the front metal layer (3) of pin (5) uses gold, silver, copper, nickel or NiPdAu to belong to.
4. according to a kind of planar salient point type described in claim 1 or 2 or 3 without Metal Cutting packaging technology, it is characterised in that: core
Sheet (7) is implanted the semi-finished product of operation and is carried out routing, and the metal wire of routing is gold thread, silver wire, copper cash or aluminum steel.
A kind of planar salient point type the most according to claim 1 is without Metal Cutting packaging technology, it is characterised in that: step 4 exists
Even silver-plated at muscle, on the basis of step 4, plastic-sealed body (8) is leaked outside pin plated metal stannum by step 14, forms pin metal
Layer (9).
6. a planar salient point type is without Metal Cutting encapsulating structure, it is characterised in that: in including chip bearing substrate, routing, foot holds
Carrying base, chip (7), metal wire and plastic-sealed body (8), described chip bearing substrate includes Ji Dao (6) and Ji Dao front
Metal level (3), in described routing, foot bearing base includes the front metal layer (3) of pin (5) and pin, even has gold on muscle
Belong to layer (3), the front metal layer (3) of chip bearing substrate is implanted chip (7), chip (7) front and pin (5) front metal
Layer (3) is connected with metal wire two ends respectively makes encapsulating structure semi-finished product, and encapsulating structure semi-finished product front and neighboring are used
Plastic-sealed body (8) is encapsulated, and the back side of Bing Shiji island (6) and pin (5) protrudes from plastic-sealed body (8) surface, protrudes the base of plastic-sealed body (8)
Island (6), pin (6) surface are coated with pin metal level (9).
A kind of planar salient point type the most according to claim 6 is without Metal Cutting encapsulating structure, it is characterised in that: described pipe
Foot metal level (9) is tin layers, and company's muscle of chip (3) is silver layer.
A kind of planar salient point type the most according to claim 6 is without Metal Cutting encapsulating structure, it is characterised in that: Ji Dao (6)
And the front metal layer (3) of pin (5) is gold silver, copper, nickel or nickel palladium.
A kind of planar salient point type the most according to claim 6 is without Metal Cutting packaging technology, it is characterised in that: chip (7)
The metal wire being connected with pin (5) routing is gold thread, silver wire, copper cash or aluminum steel.
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