CN208903998U - A kind of high reliability planar salient point type encapsulating structure - Google Patents
A kind of high reliability planar salient point type encapsulating structure Download PDFInfo
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- CN208903998U CN208903998U CN201820629893.XU CN201820629893U CN208903998U CN 208903998 U CN208903998 U CN 208903998U CN 201820629893 U CN201820629893 U CN 201820629893U CN 208903998 U CN208903998 U CN 208903998U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The utility model discloses a kind of high reliability planar salient point type encapsulating structures, belong to field of semiconductor package.For in back-protective technique existing in the prior art; simple brush ink technique not can guarantee the effective of metal pin and grab glue surface product, and after cutting, the area of pin is small; probe contacts the problem of effect difference, and the utility model provides a kind of high reliability planar salient point type encapsulating method and structure.Including foot bearing base, chip, lead and plastic-sealed body in chip bearing substrate, routing, the chip bearing substrate includes the front metal layer of Ji Dao and Ji Dao, foot bearing base includes the front metal layer of pin and pin in the routing, in addition to the back side excess metal region of pin metal layer is ink layer.It may be implemented to grab that glue effect is good, the low effect of poor contact rate, and when detection after finished product, contact effect is good, and detectivity is high.
Description
Technical field
The utility model relates to field of semiconductor package, seal more specifically to a kind of high reliability planar salient point type
Assembling structure.
Background technique
For decades, integrated antenna package technology follows always the development of integrated circuit, and people are always small
Seek best equalization point between volume and high-performance.It is encapsulated into the encapsulation of SOP surface patch formula from the DIP plug-in type of the seventies,
It is encapsulated again to the QFP Flat type patch of the eighties, always towards miniaturization, structural behaviour also exists the encapsulation volume of chip
Constantly promoted.The appearance encapsulated to the nineties, QFN flat-four-side without foot formula will be originally being encapsulated on the basis of QFP
Output pin folding and unfolding around body is to package bottom, to greatly reduce shared space in patch operation.But QFN is normal
There is the problems such as interior foot solder joint shakiness, flash, frequency of doing over again are high, encapsulation yield is relatively low.The encapsulation of FBP planar salient point type is then to improve
Problems in QFN production process and the new packaging form independently developed.
QFN encapsulation efficiently utilizes the encapsulated space of terminal pin, so that packaging efficiency be significantly increased.But at present
It is puzzled that some techniques are all suffered from the manufacturing process of most of semiconductor packages manufacturer QFN, the reason is that existing QFN technique is to avoid
Plastic packaging resin spills over terminal pin when encapsulating, and packet is generally blocked using the method for high temperature resistance diaphragm is sticked at the back side lead frame (L/F)
The random flowing of resin when envelope, and this method results in another series of technique while solving the above problems and asks
Topic, the shape of FBP is close with QFN, and foot position can also correspond, and the main difference for being different from QFN in appearance is:
The terminal pin of traditional QFN and plastic cement bottom are in same plane, and the terminal pin of FBP then protrudes from plastic cement bottom, to make SMT
When solder and the faying face of IC become three-dimensional from plane, therefore the possibility of rosin joint is effectively reduced in the assembly technology of PCB
Property；FBP can be achieved with reliably welding while realizing unleaded using craft of gilding without raising temperature at present simultaneously
It connects, to reduce the related puzzlement of circuit board assembly plant, keeps the reliability of circuit board higher.
Critical process in FBP process flow is pad pasting, exposure and etching and FBP technique and traditional IC package work
The maximum difference of skill, other processes are then similar with traditional IC packaging technology.Since the outer lead foot of FBP is by gold
Belong to and being etched in plane, therefore the coplanarity at outer lead angle is substantially uniform；And since the L/F structure of FBP is changed, I
Know that the bottom surface of FBP frame has one layer of metal to link together, ensure that each terminal pin of FBP frame has foot in this way
Enough mechanical strengths, therefore each terminal pin can design any part in entire encapsulating face, but outer lead foot is to pass through
It is etched on metal flat, it is exposed when on SMT to result in existing FBP package metals, attached pin and chip
Distance is close between Ji Dao, there is the risk of short circuit, and after cutting, the area of pin is small, pin to grab glue ability weak.The prior art
In corresponding design has also been carried out for pin short circuit.Existing patent is shielded accordingly for brush ink on the pin at the back side
With prevent short circuit.
Chinese patent application, application number 201410203916.7, publication date on September 10th, 2014, one kind being based on AAQFN
Re-expose and flip-clip packaging part and its manufacture craft, the packaging part is mainly by lead frame, lower chip, upper core
Piece, glue film, bonding line, plastic-sealed body, green oil and plant ball composition.Lower chip is welded on the lead frame, lower chip passes through glue
Film and upper die bonding, bonding line connect upper chip and lead frame, plastic-sealed body enclose the part of lead frame, lower chip,
Upper chip, glue film and bonding line, green oil is filled between the lead frame, and lead frame is connected with plant ball.The manufacture craft
Main flow is as follows: → scribing → upper core → pressure welding → plastic packaging → rear solidification → printing photosensitive-ink → exposure development is thinned in wafer
→ pin separation → striping → is greenwashed oil → exposure development → plant ball.The packaging part and manufacture craft significantly improve packaging part
Reliability, and this method is easy, high production efficiency.But this scheme is directed to how to be designed ink layer and not do specifically
It is bright.
U.S. Patent application, application number US14794715 publication date on 2 7th, 2017, are disclosed with cloth line tracking
Semiconductor packages, including etching the first side of sheet metal with formed have one or more wire bonds lead frame,
Second side of the first protective layer, etching sheet metal is coated on first side to form one or more conductive terminals, and second
The second protective layer is coated on side.Semiconductor packages includes the conducting wire engagement in the rod structure around the bare die for being attached to lead frame
Pad, one or more exits in the bottom side of semiconductor packages.But this scheme is directed to how to be designed to protective layer
It does not elaborate.
But above scheme is since the structure setting of ink layer is unreasonable, and since simple brush ink technique not can guarantee
Metal pin effectively grabs glue surface product, and pin is low, generally require to increase after brush ink layer higher Jin Shu at or use
Tin sweat(ing), whole pin grab that glue surface product is small, and grabbing colloidality can be poor, and poor contact rate is high, and when flaw detection after finished product, contact is imitated
Fruit is poor, and detectivity is low.
Summary of the invention
1. technical problems to be solved
For in back-protective technique existing in the prior art, simple brush ink technique not can guarantee metal pin
Glue surface product is effectively grabbed, after cutting, the area of pin is small, when flaw detection, contacts the problem of effect difference, the utility model provides one kind
High reliability planar salient point type encapsulating structure.It may be implemented to grab that glue effect is good, the low lower effect of poor contact rate, and at
When flaw detection after product, contact effect is good, and detectivity is high.
2. technical solution
The purpose of this utility model is achieved through the following technical solutions.
A kind of high reliability planar salient point type packaging method is etched using planar salient point type packaging method in substrate back
The extra metallic region setting ink layer overleaf etched after step, ink layer are covered on metallic region surface and Metal Substrate
Plate pin side, metal substrate pin protrude from ink layer.
Further, the step of ink layer is arranged is:
A, in one layer of ink of substrate back brush；
B, after once toasting, one-step solidification ink；First guarantee that the ink of brush will not fall off, guarantees that subsequent technique is suitable
Benefit carries out；
C, the ink after solidification is showed metal pin by exposure, development；It eliminates and needs subsequent increase metal pin
The ink of position；
D, secondary baking carries out secondary curing ink.So that it is ink curing, it is fixed on substrate, and due to this baking
Roasting, ink shrinks 40% or so, so that pin protrudes from ink layer.
Further, the ink is liquid photo-imaging solder mask.
Further, further include that the substrate after brush ink is placed in vacuum tank in step A, vacuumized.
Further, a baking temperature is at 75 ± 5 DEG C, and the time is 50 ± 10min, and secondary baking temperature is 165 ± 5
DEG C, time 6h.
According to a kind of high reliability planar salient point type packaging method described above, overall step is as follows:
1) one piece of metal substrate is taken；
2) photopolymer layer is sticked respectively at metal substrate front, the back side to protect subsequent etch process operation；
3) the positive part photopolymer layer of metal substrate is removed, prepares to form Ji Dao, even muscle, pin on metallic substrates；
4) prepare on metallic substrates the Ji Dao to be formed, even muscle, pin field front plate front metal layer, even at muscle
It is silver-plated；
5) the remaining photopolymer layer in metal substrate upper layer is removed, etching region is exposed；
6) half-etching is carried out to the dry film region that step 5 removes, forms the half-etched regions of recess on metallic substrates, together
When opposite form Ji Dao and pin；
7) implanted chip is carried out on the base island front metal layer of metal substrate, forms the column of integrated circuit or discrete component
Configuration aggregate semi-finished product；
8) routing is carried out to the semi-finished product for having completed implanted chip operation, forms lead；
9) it encapsulates, it is rear to solidify, form encapsulating；
10) photopolymer layer is pasted again at the metal substrate back side；
11) photopolymer layer at the metal substrate half-etched regions back side is removed, to expose the subsequent region for needing to etch；
12) region not covered by dry film is carried out total eclipse quarter at the metal substrate back side, the island Shi Ji and pin protrude plastic packaging
Body surface face；
13) the extra metallic region setting ink layer overleaf etched after substrate back etching step, using exposure,
Developing process removes metal substrate back side excess ink layer in favor of subsequent electroplating technology operation；
14) in the Ji Dao of protrusion, pin plating metal, pin metal layer is formed；
15) cutting operation, product separation are carried out after UV film being sticked in plastic-sealed body front.
The substrate back of a kind of high reliability planar salient point type encapsulating structure, encapsulating structure etches the region in addition to pin,
It is provided with ink layer, ink layer is covered on metallic region surface and metal substrate pin side, metal substrate pin protrude from
Ink layer.
Further, foot bearing base, chip, lead and plastic-sealed body including in chip bearing substrate, routing, it is described
Chip bearing substrate include Ji Dao and Ji Dao front metal layer, in the routing foot bearing base include pin and
The front metal layer of pin even has front metal layer on muscle, chip, chip is provided on the front metal layer of chip bearing substrate
Front and front metal layer are connect with metal wire both ends respectively, and chip front side and front metal layer front and neighboring are arranged
There is an encapsulating, the back side of Ji Dao and pin protrudes from plastic-sealed body surface, protrudes the Ji Dao at the back side, pin surface is provided with pin metal
Layer, ink layer is covered on metallic region surface and metal substrate pin side, metal substrate pin protrude from ink layer.
Further, the front metal layer of Ji Dao and pin is gold and silver, copper, nickel or nickel palladium.Capsulation material and gold, silver,
Copper, nickel or nickel palladium binding ability are good, it is not easy to cause to be layered.
Further, the lead that chip is connect with pin routing is gold thread, silver wire, copper wire or aluminum steel.Material is inertia
Material, the holding time is long, and conductivity and thermal diffusivity are good.
3. beneficial effect
Compared with the prior art, utility model has the advantages that
(1) this programme uses the method that ink layer is added in substrate back on the basis of planar salient point type encapsulates, and has
Effect solves metal pin of the back substrate due to directly etching since the regional metal of etching is exposed, causes to carry out patch
When pin between distance it is close, have short circuit risk, after cutting, the area of pin is small, and pin grabs the weak problem of glue ability,
Ensure that will not occur short circuit after installing, and pin grabs the strong effect of glue ability；
(2) this programme is using secondary curing and the method for exposure development, it is ensured that ink will not fall off, and guarantee subsequent
Technique eliminate and need the subsequent ink for increasing metal pin position while go on smoothly, and secondary baking makes ink
Hardening, is fixed on substrate, and due to this baking, ink shrinks 40% or so, so that pin protrudes from ink layer, increasing
After adding pin metal layer, effectively increase it is whole grab glue surface product, and bigger is to increase side to grab glue surface product, and brush coating when brushes
Glue surface product is big, and fastness is more preferable, and leakage brush rate reduces, and whole solderability is more outstanding, also increases the face of electroplated metal layer
Product, is effectively ensured pin metal layer and is firmly fixed on pin, reduces pin metal liftoff rate, guarantees that whole pin is secured
Degree and product quality, pin protrusion seal survey when, since pin is higher than plastic-sealed body, probe contact is more preferable when test, connects
Touching bad probability can be greatly reduced, and improve test UPH, reduce cost；Pin is protruded in pcb board on product SMT, increases pipe
Thrust of the product on pcb board can be improved in the contact area of foot and tin cream, improves the reliability of product after upper plate, electrically；Pin
It protrudes, on product after PCB, product and PCB have certain gap, are more conducive to the heat dissipation of product.
(3) during brush ink, since bubble can be generated in ink printing process, the substrate after brush ink is placed on
It in vacuum tank, is vacuumized, effectively prevent the generation of interiors of products bubble, ensure that the quality of product, prevent from introducing newly
Defect；And due to the baking procedure of two step of front and back, the step of vacuumizing, was also effectively prevent in the baking stage, when bubble leads to baking
The fragmentation and out-of-flatness for waiting ink layer, influence overall performance, height when can also prevent ink from shrinking is inconsistent, causes pin
Protrusion height is inconsistent, will cause brush coating defect in the subsequent process, introduces new circuit defect；
(4) original encapsulation step only carries out pin and Ji Dao plating；The existing original etching of step only removes part metals, this
Scheme removes all unwanted copper materials, is in the prior art that even pin, the Ji Dao of product is electroplated in muscle with metal base,
By our scheme, all Copper base materials of product are all corroded, and no Metal Cutting are belonged in cutting process, directly by chip chamber
Metallic substrates first remove, when cutting separating chips, cutter only need to cut plastic packaging material, tin, silver and ink layer, and
And conventionally, as there is metal layer, cutting stress hair, in cutting, ink layer is crushed and shifts frequent occurrence, makes
At the decline of quality, bad product rate rises after ink layer is added, not very practical, using this programme, cutting process product institute
The stress received reduces by 90% or more, and product is avoided to be layered, and improves product reliability, and cutting when only needs to cut due to tin
With silver soft, cutting stress is small, and cutting abrasion is small, and chip reliability improves, it is possible to reduce the abrasion of cutting tool, Er Qieyou
Effect ensure that the fly-cutting of ink layer, and separation will not occur and the broken of ink layer falls off, will not after dicing metal layer according to
It is so exposed, the quality of product has been effectively ensured；
(5) original cutting resin knife is readily modified as steel edge cutting, and cutting process product surface is more smooth, tool wear
Cutter that can be bigger using mesh number are reduced, cutter mesh number is bigger, and chip is smaller, cutting process product surface more light
Sliding, chip is smaller, and product shape is more beautiful, and product shape is more beautiful；
(6) prepare on metallic substrates the Ji Dao to be formed, even muscle, pin field front plate front metal layer, with benefit
Metal wire is closely combined with pin in chip region and routing when subsequent bonding wire, even silver-plated at muscle to be used for subsequent plated conductive pipe
Foot is tin plating, and process is simple, and cost reduces；
(7) front metal layer of Ji Dao and pin is gold, silver, copper, nickel or nickel palladium, capsulation material and gold, silver, copper, nickel or
Nickel palladium binding ability is good, it is not easy to cause to be layered；
(8) metal wire that chip is connect with pin routing is gold thread, silver wire, copper wire or aluminum steel, and material is inert material, is protected
Deposit that the time is long, and conductivity and thermal diffusivity are good.
(9) this programme is used, short-circuit ratio can be reduced to 0PPM；It ensure that the situation of 0 short circuit occurs, shape pin face
Increase brush ink, pin fastness can be improved 30% or more；
(10) packaging method and structure of this programme with respect to DFN QFN the encapsulating products integrated level such as MIS it is higher, cost is more
It is low, 20% or more save the cost.
Detailed description of the invention
Fig. 1 is structural schematic diagram after the load of the utility model；
Fig. 2 is structural schematic diagram after the ball bonding of the utility model；
Fig. 3 is structural schematic diagram after the encapsulating of the utility model；
Fig. 4 is structural schematic diagram after the back etched of the utility model；
Fig. 5 is structural schematic diagram after the utility model brush ink；
Fig. 6 is structural schematic diagram after the utility model exposure development；
Fig. 7 is structural schematic diagram after the utility model plating；
Fig. 8 is structural schematic diagram after the utility model cutting.
Figure label explanation:
1, substrate；2, front metal layer；3, chip；4, lead；5, encapsulated layer；6, back etched area；7, ink layer； 8,
Pin metal layer.
Specific embodiment
With reference to the accompanying drawings of the specification and specific embodiment, the utility model is described in detail.
Embodiment 1
As shown in figures 1-8, a kind of high reliability planar salient point type packaging method, using planar salient point type packaging method,
The extra metallic region setting ink layer overleaf etched after substrate back etching step, ink layer 7 are covered on metallic region
1 pin side of surface and metal substrate, 1 pin of metal substrate protrude from ink layer 7.Ink layer 7 can guarantee welding procedure
In, prevent the short circuit generated by bridging；It is only welded in the part that must be welded, solder is avoided to waste；Reduce butt welding splicing
The Cu-W ore deposit of slot；Degradation of insulation, corrosion caused by preventing because of outside environmental elements such as dust, moisture content；With high-insulativity, make circuit
Densification be possibly realized.The ink layer 7 of protrusion effectively increases entirety and grabs glue surface product after increasing pin metal layer 8,
And bigger is to increase side to grab glue surface product, brush coating area is big when brush coating, and fastness is more preferable, and leakage brush rate reduces, whole
Solderability is more outstanding, also increases the area of electroplated metal layer, and pin metal layer 8 is effectively ensured and is firmly fixed to pin
On, 8 expulsion rate of pin metal layer is reduced, guarantees whole pin firmness and product quality, when sealing survey, due to pin height
The area of Du Genggao, especially side is bigger, and probe contact performance is more preferable when test, and poor contact rate rate is greatly reduced, inspection
Lower error rate is surveyed, the testing cost in later period is reduced, pin protrusion, since pin is higher than plastic-sealed body, is surveyed when sealing survey
Probe contact is more preferable when examination, and poor contact probability can be greatly reduced, and improves test UPH, reduces cost, PCB on product SMT
When plate, the contact area of pin and tin cream is increased, thrust of the product on pcb board can be improved, product can after raising upper plate
By property, electrically；On product after PCB, product and PCB have certain gap, are more conducive to the heat dissipation of product.
Overall step is as follows:
1) one piece of metal substrate 1 is taken；
2) photopolymer layer is respectively sticked at 1 front of metal substrate, the back side；
3) the positive part photopolymer layer of metal substrate 1 is removed, prepares to form Ji Dao on metal substrate 1, connects muscle, draws
Foot；
4) prepare on metal substrate 1 Ji Dao to be formed, even muscle, pin field front plate front metal layer 2, even muscle
Locate silver-plated；
5) the remaining photopolymer layer in 1 upper layer of metal substrate is removed, etching region is exposed；
6) half-etching is carried out to the dry film region that step 5 removes, forms the half-etched regions of recess on metal substrate 1,
It is opposite simultaneously to form Ji Dao and pin；
7) chip 3 is carried out on the base island front metal layer 2 of metal substrate 1 to be implanted into, form integrated circuit or discrete component
Array type aggregate semi-finished product；
8) routing is carried out to the semi-finished product for having completed the implantation operation of chip 3, forms lead 4；
9) it encapsulates, it is rear to solidify, form encapsulating 5；
10) photopolymer layer is pasted again in 1 face of Metal Substrate backboard；
11) photopolymer layer at the 1 half-etched regions back side of metal substrate is removed, to expose the subsequent region for needing to etch；
12) at 1 back side of metal substrate is carried out to the region not covered by dry film total eclipse quarter, forms back etched area 6, makes base
Island and pin protrude plastic-sealed body surface；
13) the extra metallic region setting ink layer 7 overleaf etched after substrate back etching step；
The step of ink layer 7 are arranged is:
A, in one layer of ink of substrate back brush；SMT gluing equipment can be used directly herein and carry out brush ink, ink is photosensitive material
Material, is a kind of liquid photo-imaging solder mask, a series of spies such as electrical property, heat resisting temperature, anti-flammability, reliability according to product
Property choose suitable ink, use green oil in the present embodiment.Green oil, that is, liquid photo-imaging solder mask is that a kind of acrylic acid is oligomeric
Object.It as a kind of protective layer, is not required to coated in printed circuit board on the route and substrate of welding, or is used as solder resist, it is therefore an objective to
Digital preservation is formed by line pattern.
B, after once toasting, one-step solidification ink；For baking temperature at 75 ± 5 DEG C, the time is 50 ± 10min；
C, the ink after solidification is showed metal pin by exposure, development；Using the liquid medicine that develops for carbonic acid when development
Sodium.
D, secondary baking carries out secondary curing ink.Secondary baking temperature is at 165 ± 5 DEG C, time 6h.Secondary baking
So that ink curing, be fixed on substrate, and due to this baking, ink shrinks 40% or so, using secondary curing and
The method of exposure development, it is ensured that ink will not fall off, while guaranteeing that subsequent technique is gone on smoothly, after eliminating needs
The continuous ink for increasing metal pin position.Back etched region metal area extra after etching is covered according to product design shape
Domain forms target design shape.Using exposure, developing process removal 1 back side excess ink layer 2 of metal substrate in favor of subsequent
Electroplating technology operation.
14) in the Ji Dao of protrusion, pin plating metal, pin metal layer 8 is formed；
15) cutting operation, product separation are carried out after UV film being sticked in plastic-sealed body front.
Original encapsulation step only carries out pin and Ji Dao plating；The existing original etching of step only removes part metals, we
Case removes all unwanted copper materials, is in the prior art that even pin, the Ji Dao of product is electroplated in muscle with metal base, passes through
Our scheme is crossed, all Copper base materials of product are all corroded, and no Metal Cutting are belonged in cutting process, directly by chip chamber
Metallic substrates first remove, and when cutting separating chips, cutter only need to cut plastic packaging material, tin, silver and ink layer, and
Conventionally, as there is metal layer, cutting stress hair, in cutting, ink layer is crushed and shifts frequent occurrence, causes
The decline of quality, bad product rate rises after ink layer is added, not very practical, using this programme, suffered by cutting process product
Stress reduce by 50% or more, avoid product from being layered, improve product reliability, cutting when only need to cut due to tin and
Silverly soft, cutting stress is small, and cutting abrasion is small, and chip reliability improves, it is possible to reduce the abrasion of cutting tool, and effectively
It ensure that the fly-cutting of ink layer, separation will not occur and the broken of ink layer falls off, it will not metal layer be still after dicing
It is exposed, the quality of product has been effectively ensured.And ensure that the integrated level of height, relative to existing QFN encapsulate, it is original if it is
The chip of 2.6mm length and width needs to make the package size of 9*9mm, and density is low, and welding wire consumption is more, using this programme, it is only necessary to
Using 4.5*5mm package size, purpose increases, and size is reduced, and welding wire consumption also reduces, and short-circuit probability is 0, is effectively ensured
Yields.
This programme uses the method that ink layer is added in substrate back on the basis of planar salient point type encapsulates, and effectively solves
Metal pin of the back substrate due to directly etching determined since the regional metal of etching is exposed, when leading to carry out patch
Distance is close between pin, there is the risk of short circuit, and after cutting, the area of pin is small, and pin grabs the weak problem of glue ability, guarantees
It will not occur short circuit after installation, and pin grabs the strong effect of glue ability.The ink layer 7 of protrusion is increasing pin metal layer 8
Afterwards, effectively increase it is whole grab glue surface product, and bigger is to increase side to grab glue surface product, and brush coating area is big when brush coating, jail
Solidity is more preferable, and leakage brush rate reduces, and whole solderability is more outstanding, also increases the area of electroplated metal layer, is effectively ensured
Pin metal layer 8 is firmly fixed on pin, reduces 8 expulsion rate of pin metal layer, guarantees whole pin firmness and product
Quality, seal survey when, since pin height is higher, the area of especially side is bigger, probe contact performance when test
More preferably, poor contact rate rate is greatly reduced, and detects lower error rate, reduces the testing cost in later period.Pin protrusion is surveyed in envelope
When, since pin is higher than plastic-sealed body, probe contact is more preferable when test, and poor contact probability can be greatly reduced, and improves and surveys
UPH is tried, cost is reduced, on product SMT when pcb board, increases the contact area of pin and tin cream, product can be improved in pcb board
On thrust, improve upper plate after product reliability, electrically；On product after PCB, product and PCB have certain gap, more
Be conducive to the heat dissipation of product.
Embodiment 2
Embodiment 2 is substantially the same manner as Example 1, also resides in, it is preferred that in step A further includes by the substrate after brush ink
It is placed in vacuum tank, is vacuumized.When vacuumizing, select 0.08-0.1MPa, the time in 5-10min, in brush ink
During, due to having bubble in ink, the substrate after brush ink is placed in vacuum tank, is vacuumized, effectively prevent producing
The generation of product air entrapment ensure that the quality of product, prevent from introducing new defect.And due to the baking procedure of two step of front and back,
The step of vacuumizing also effectively prevent in the baking stage, and bubble leads to the fragmentation and out-of-flatness of ink layer when baking, influenced whole
Body performance, height when can also prevent ink from shrinking is inconsistent, causes pin protrusion height inconsistent, in the subsequent process can
Brush coating defect is caused, new circuit defect is introduced, such as tin amount difference on several pins, will appear after leading to product SMT Reflow Soldering
The security risks such as slide, set up a monument.
Embodiment 3
Based on the above method, a kind of high reliability planar salient point type encapsulating structure, including in chip bearing substrate, routing
Foot bearing base, chip 3, lead 4 and plastic-sealed body, the chip bearing substrate include the front metal of Ji Dao and Ji Dao
Layer 2, foot bearing base includes the front metal layer 3 of pin and pin in the routing, even has front metal layer 2 on muscle,
Chip 3 is implanted on the front metal layer 2 of chip bearing substrate, 3 front of chip and front metal layer 2 connect with metal wire both ends respectively
It connects and encapsulating structure semi-finished product is made, encapsulating structure semi-finished product front and neighboring form the encapsulating island 5, Bing Shiji and pin
The back side protrudes from plastic-sealed body surface, protrudes the Ji Dao at the back side, pin surface is coated with pin metal layer 8, in addition to pin metal layer 8
Back side excess metal region is ink layer.The front metal layer 2 of Ji Dao and pin is gold and silver, copper, nickel or nickel palladium.Chip 3 with draw
The lead 4 of foot routing connection is gold thread, silver wire, copper wire or aluminum steel.
Schematically the invention and embodiments thereof are described above, description is not limiting, not
In the case where spirit or essential characteristics of the invention, the utility model can be realized in other specific forms.Attached drawing
Shown in also be the invention one of embodiment, actual structure is not limited to this, in claim appoint
What appended drawing reference should not limit the claims involved.So if those of ordinary skill in the art are inspired by it, not
In the case where being detached from this creation objective, frame mode similar with the technical solution and embodiment are not inventively designed,
It should belong to the protection scope of this patent.In addition, one word of " comprising " is not excluded for other elements or step, before the component "one"
One word is not excluded for including " multiple " element.The multiple element stated in claim to a product can also be passed through soft by an element
Part or hardware are realized.The first, the second equal words are used to indicate names, and are not indicated any particular order.
Claims (5)
1. a kind of high reliability planar salient point type encapsulating structure, it is characterised in that: the substrate back etching of encapsulating structure removes pin
Outer region is provided with ink layer (7), and ink layer (7) is covered on metallic region surface and metal substrate (1) pin side,
Metal substrate (1) pin protrudes from ink layer (7).
2. a kind of high reliability planar salient point type encapsulating structure according to claim 1, it is characterised in that: held including chip
Foot bearing base, chip (3), lead (4) and plastic-sealed body, the chip bearing substrate include Ji Dao in load pedestal, routing
And the front metal layer (2) of Ji Dao, foot bearing base includes the front metal layer of pin and pin in the routing
(2), even have front metal layer (2) on muscle, be provided with chip (3) on the front metal layer (2) of chip bearing substrate, chip (3)
Front and front metal layer (2) are connect with metal wire both ends respectively, and chip (3) front and front metal layer (2) are positive and outer
Circumferential edges are provided with encapsulating (5), and the back side of Ji Dao and pin protrudes from plastic-sealed body surface, protrude Ji Dao, the pin surface at the back side
It is provided with pin metal layer (8), ink layer (7) is covered on metallic region surface and metal substrate (1) pin side, Metal Substrate
Plate (1) pin protrudes from ink layer (7).
3. a kind of high reliability planar salient point type encapsulating structure according to claim 2, it is characterised in that: Ji Dao and pin
Front metal layer (2) be gold and silver, copper, nickel or nickel palladium.
4. a kind of high reliability planar salient point type encapsulating structure according to claim 2, it is characterised in that: chip (3) with
The lead (4) of pin routing connection is gold thread, silver wire, copper wire or aluminum steel.
5. a kind of high reliability planar salient point type encapsulating structure according to claim 1, it is characterised in that: the ink
The ink of layer is liquid photo-imaging solder mask.
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| CN108389805A (en) * | 2018-04-28 | 2018-08-10 | 长电科技（滁州）有限公司 | A kind of high reliability planar salient point type encapsulating method and structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389805A (en) * | 2018-04-28 | 2018-08-10 | 长电科技（滁州）有限公司 | A kind of high reliability planar salient point type encapsulating method and structure |
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