CN108389805A - A kind of high reliability planar salient point type encapsulating method and structure - Google Patents

A kind of high reliability planar salient point type encapsulating method and structure Download PDF

Info

Publication number
CN108389805A
CN108389805A CN201810399646.XA CN201810399646A CN108389805A CN 108389805 A CN108389805 A CN 108389805A CN 201810399646 A CN201810399646 A CN 201810399646A CN 108389805 A CN108389805 A CN 108389805A
Authority
CN
China
Prior art keywords
pin
layer
ink
metal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810399646.XA
Other languages
Chinese (zh)
Inventor
吴奇斌
吴靖宇
范荣定
吴莹莹
吴涛
吕磊
汪阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changjiang Electronics Technology Chuzhou Co Ltd
Original Assignee
Changjiang Electronics Technology Chuzhou Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changjiang Electronics Technology Chuzhou Co Ltd filed Critical Changjiang Electronics Technology Chuzhou Co Ltd
Priority to CN201810399646.XA priority Critical patent/CN108389805A/en
Publication of CN108389805A publication Critical patent/CN108389805A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4922—Bases or plates or solder therefor having a heterogeneous or anisotropic structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention discloses a kind of high reliability planar salient point type encapsulating method and structures, belong to field of semiconductor package.For in back-protective technique existing in the prior art; simple brush ink technique can not ensure that the glue surface of effectively grabbing of metal pin is accumulated, and after cutting, the area of pin is small; probe contacts the problem of effect difference, and the present invention provides a kind of high reliability planar salient point type encapsulating method and structure.Including foot bearing base, chip, lead and plastic-sealed body in chip bearing substrate, routing, the chip bearing substrate includes the front metal layer of Ji Dao and Ji Dao, foot bearing base includes the front metal layer of pin and pin in the routing, in addition to the back side excess metal region of pin metal layer is ink layer.It may be implemented to grab that glue effect is good, the low effect of poor contact rate, and when detection after finished product, contact effect is good, and detectivity is high.

Description

A kind of high reliability planar salient point type encapsulating method and structure
Technical field
The present invention relates to field of semiconductor package, more specifically to a kind of high reliability planar salient point type encapsulation side Method and encapsulating structure.
Background technology
Recent decades, integrated antenna package technology follow always the development of integrated circuit, and people are always small Seek best equalization point between volume and high-performance.It is encapsulated into the encapsulation of SOP surface patch formulas from the DIP plug-in types of the seventies, It is encapsulated again to the QFP Flat type patchs of the eighties, the encapsulation volume of chip is always towards miniaturization, and structural behaviour is not yet It is promoted disconnectedly.The appearance encapsulated to the nineties, QFN flat-four-sides without foot formula, being will be originally in packaging body on the basis of QFP The output pin folding and unfolding of surrounding is to package bottom, to greatly reduce shared space in patch operation.But QFN often has The problems such as interior foot solder joint shakiness, flash, frequency of doing over again are high, encapsulation yield is relatively low.The encapsulation of FBP planar salient point types is then to improve Problems in QFN production processes and the new packaging form independently developed.
QFN encapsulates the encapsulated space for efficiently utilizing terminal pin, to which packaging efficiency be significantly increased.But at present Some techniques puzzlement is all suffered from the manufacturing process of most of semiconductor packages manufacturer QFN, the reason is that existing QFN techniques are to avoid Plastic packaging resin spills over terminal pin when encapsulating, general to block packet using the method for high temperature resistance diaphragm is sticked at the back side lead frame (L/F) The random flowing of resin when envelope, and this method results in another series of technique while solving the above problems and asks Topic, the shape of FBP is close with QFN, and foot position can also correspond, and the main difference for being different from QFN in appearance is：It passes The terminal pin of system QFN and plastic cement bottom are in same plane, and the terminal pin of FBP then protrudes from plastic cement bottom, is welded when to make SMT The faying face of material and IC becomes three-dimensional from plane, therefore the possibility of rosin joint is effectively reduced in the assembly technology of PCB；Together When current FBP using craft of gilding, do not have to raise temperature while realizing unleaded and can be achieved with reliably welding, from And reduce the related puzzlement of circuit board assembly plant, make the reliability higher of circuit board.
Critical process in FBP technological processes is pad pasting, exposure and etching and FBP techniques and traditional IC package work The maximum difference of skill, other processes are then similar with traditional IC packaging technology.Since the outer lead foot of FBP is by gold Belong to and being etched in plane, therefore the coplanarity at outer lead angle is substantially uniform；And since the L/F structures of FBP are changed, I Know that the bottom surface of FBP frames has one layer of metal to link together, ensure that each terminal pin of FBP frames has foot in this way Enough mechanical strengths, therefore each terminal pin can design any part in entire encapsulating face, but outer lead foot is to pass through It is etched on metal flat, it is exposed when on SMT to result in existing FBP package metals, attached pin and chip Distance is close between Ji Dao, there is the risk of short circuit, and after cutting, the area of pin is small, pin to grab glue ability weak.The prior art In corresponding design has also been carried out for pin short circuit.Existing patent is shielded accordingly for brush ink on the pin at the back side With prevent short circuit.
Chinese patent application, application number 201410203916.7, publication date September in 2014 10 days are a kind of based on AAQFN's The packaging part and its manufacture craft of re-expose and flip-clip, the packaging part is mainly by lead frame, lower chip, upper core Piece, glued membrane, bonding line, plastic-sealed body, green oil and plant ball composition.Lower chip is welded on the lead frame, lower chip passes through glue Film and upper die bonding, the upper chip of bonding line connection and lead frame, plastic-sealed body enclose the part of lead frame, lower chip, Upper chip, glued membrane and bonding line, green oil is filled between the lead frame, and lead frame is connected with plant ball.The manufacture craft Main flow is as follows：→ scribing → upper core → pressure welding → plastic packaging → rear solidification → printing photosensitive-ink → exposure imaging is thinned in wafer → pin separation → striping → is greenwashed oil → exposure imaging → plant ball.The packaging part and manufacture craft significantly improve packaging part Reliability, and this method is easy, and production efficiency is high.But this scheme is directed to how to be designed ink layer and not do specifically It is bright.
U.S. Patent application, application number US14794715, publication date on 2 7th, 2017 are disclosed with cloth line tracking Semiconductor packages, including the first side of etching sheet metal with formed carry one or more wire bonds lead frame, The second side of the first protective layer, etching sheet metal is coated on first side to form one or more conductive terminals, and second The second protective layer is coated on side.Semiconductor packages is included in the conducting wire engagement in the rod structure for the bare die for being attached to lead frame Pad, one or more exits in the bottom side of semiconductor packages.But how this scheme is designed protective layer if being directed to It does not elaborate.
But said program is since the structure setting of ink layer is unreasonable, and since simple brush ink technique can not ensure Metal pin effectively grabs glue surface product, and pin is low, generally require to increase after brush ink layer higher Jin Shu at or use Tin sweat(ing), whole pin to grab glue surface product small, grab glue poor performance, poor contact rate is high, and when flaw detection after finished product, contact effect Fruit is poor, and detectivity is low.
Invention content
1. technical problems to be solved
For in back-protective technique existing in the prior art, simple brush ink technique can not ensure metal pin Effectively grab glue surface product, after cutting, the area of pin is small, when flaw detection, contacts the problem of effect difference, present invention offer it is a kind of it is high can By property planar salient point type encapsulating method and structure.It may be implemented to grab that glue effect is good, the low lower effect of poor contact rate, And when flaw detection after finished product, contact effect is good, and detectivity is high.
2. technical solution
The purpose of the present invention is achieved through the following technical solutions.
A kind of high reliability planar salient point type packaging method is etched using planar salient point type packaging method in substrate back The extra metallic region setting ink layer overleaf etched after step, ink layer are covered in metallic region surface and Metal Substrate Plate pin side, metal substrate pin protrude from ink layer.
Further, the step of ink layer is arranged is：
A, in one layer of ink of substrate back brush；
B, after once toasting, one-step solidification ink；First ensure that the ink of brush will not fall off, ensures that subsequent technique is suitable Profit carries out；
C, the ink after solidification is showed metal pin by exposing, developing；Eliminate the follow-up increase metal pin of needs The ink of position；
D, secondary baking carries out secondary curing ink.So that it is ink curing, it is fixed on substrate, and due to this baking Roasting, ink shrinks 40% or so so that pin protrudes from ink layer.
Further, the ink is liquid photo-imaging solder mask.
Further, further include that the substrate after brush ink is placed in vacuum tank in step A, vacuumized.
Further, a baking temperature is at 75 ± 5 DEG C, and the time is 50 ± 10min, and secondary baking temperature is 165 ± 5 DEG C, time 6h.
According to a kind of high reliability planar salient point type packaging method described above, overall step is as follows：
1) one piece of metal substrate is taken；
2) photopolymer layer is respectively sticked to protect subsequent etch process operation at metal substrate front, the back side；
3) the positive part photopolymer layer of metal substrate is removed, prepares to form Ji Dao, even muscle, pin on metallic substrates；
4) prepare on metallic substrates the Ji Dao to be formed, even muscle, pin field front plate front metal layer, even at muscle It is silver-plated；
5) the remaining photopolymer layer in metal substrate upper layer is removed, etching region is exposed；
6) half-etching is carried out to the dry film region that step 5 removes, forms the half-etched regions of recess on metallic substrates, together When opposite form Ji Dao and pin；
7) implanted chip is carried out on the base island front metal layer of metal substrate, forms the row of integrated circuit or discrete component Configuration aggregate semi-finished product；
8) routing is carried out to the semi-finished product for having completed implanted chip operation, forms lead；
9) it encapsulates, it is rear to cure, form encapsulating；
10) photopolymer layer is pasted again at the metal substrate back side；
11) photopolymer layer at the removal metal substrate half-etched regions back side, to expose the region for subsequently needing to etch；
12) region not by dry film covering is carried out total eclipse quarter at the metal substrate back side, the islands Shi Ji and pin protrude plastic packaging Body surface face；
13) the extra metallic region setting ink layer overleaf etched after substrate back etching step, using exposure, Developing process removes metal substrate back side excess ink layer in favor of subsequent electroplating technology operation；
14) in the Ji Dao of protrusion, pin plating metal, pin metal layer is formed；
15) cutting operation, product separation are carried out after UV films being sticked in plastic-sealed body front.
The substrate back of a kind of high reliability planar salient point type encapsulating structure, encapsulating structure etches the region in addition to pin, It is provided with ink layer, ink layer is covered in metallic region surface and metal substrate pin side, metal substrate pin protrude from Ink layer.
Further, foot bearing base, chip, lead and plastic-sealed body including in chip bearing substrate, routing, it is described Chip bearing substrate include Ji Dao and Ji Dao front metal layer, in the routing foot bearing base include pin and The front metal layer of pin even has metal layer on muscle, is implanted into chip on the front metal layer of chip bearing substrate, chip front side and Front metal layer connect with metal wire both ends encapsulating structure semi-finished product are made respectively, encapsulating structure semi-finished product front and outer periphery Edge, which is formed, to be encapsulated, and the back side of the islands Bing Shiji and pin protrudes from plastic-sealed body surface, protrudes the Ji Dao at the back side, pin surface is coated with pipe Foot metal layer, ink layer is covered in metallic region surface and metal substrate pin side, metal substrate pin protrude from ink Layer.
Further, the front metal layer of Ji Dao and pin is gold and silver, copper, nickel or nickel palladium.Capsulation material and gold, silver, Copper, nickel or nickel palladium binding ability are good, it is not easy to cause to be layered.
Further, the lead that chip is connect with pin routing is gold thread, silver wire, copper wire or aluminum steel.Material is inertia Material, the holding time is long, and conductivity and thermal diffusivity are good.
3. advantageous effect
Compared with the prior art, the advantage of the invention is that：
(1) this programme uses the method that ink layer is added in substrate back on the basis of planar salient point type encapsulates, and has Effect solves metal pin of the back substrate due to directly etching since the regional metal of etching is exposed, causes to carry out patch When pin between distance it is close, have short circuit risk, after cutting, the area of pin is small, and pin grabs the weak problem of glue ability, Ensure that will not occur short circuit after installing, and pin grabs the strong effect of glue ability；
(2) this programme is using secondary curing and the method for exposure imaging, it is ensured that ink will not fall off, and ensure follow-up Technique while be smoothed out, eliminate and need the follow-up ink for increasing metal pin position, and secondary baking makes ink Hardening, is fixed on substrate, and due to this baking, and ink shrinks 40% or so so that pin protrudes from ink layer, is increasing After adding pin metal layer, effectively increase it is whole grab glue surface product, and glue surface product is grabbed in the side that is the increase in of bigger, and brush coating when brushes Glue surface product is big, and fastness is more preferable, and leakage brush rate reduces, and whole solderability is more outstanding, also increases the face of electroplated metal layer Product, is effectively ensured pin metal layer and is firmly fixed on pin, reduces pin metal liftoff rate, ensures that whole pin is secured Degree and product quality, pin protrusion seal survey when, since pin is higher than plastic-sealed body, probe contact is more preferable when test, connects Touching bad probability can be greatly reduced, and improve test UPH, reduce cost；Pin is protruded in pcb board on product SMT, increases pipe Thrust of the product on pcb board can be improved in the contact area of foot and tin cream, improves the reliability of product after upper plate, electrically；Pin It protrudes, on product after PCB, product has certain gap with PCB, is more conducive to the heat dissipation of product.
(3) during brush ink, due to will produce bubble in ink printing process, the substrate after brush ink is placed on It in vacuum tank, is vacuumized, effectively prevent the generation of interiors of products bubble, ensure that the quality of product, prevent from introducing newly Defect；And due to the baking procedure of front and back two step, the step of vacuumizing, also effectively prevent in the baking stage, when bubble leads to baking The fragmentation and out-of-flatness for waiting ink layer, influence overall performance, height when can also prevent ink from shrinking is inconsistent, causes pin Protrusion height is inconsistent, can cause brush coating defect in the subsequent process, introduces new circuit defect；
(4) original encapsulation step only carries out pin and Ji Dao plating；The existing original etching of step only removes part metals, this Scheme removes all unwanted copper materials, is in the prior art that even pin, the Ji Dao of product is electroplated in muscle with metal base, By our scheme, all Copper base materials of product are all corroded, and no Metal Cutting is belonged in cutting process, directly by chip chamber Metallic substrates first remove, when cutting separating chips, cutter only need to cut plastic packaging material, tin, silver and ink layer, and And conventionally, as there is metal layer, cutting stress hair, in cutting, ink layer is crushed and shifts frequent occurrence, makes At the decline of quality, bad product rate rises after ink layer is added, and practicability is not strong, using this programme, cutting process product institute The stress received reduces by 90% or more, and product is avoided to be layered, and improves product reliability, and cutting when only needs cutting due to tin With silver soft, cutting stress is small, and cutting abrasion is small, and chip reliability improves, it is possible to reduce the abrasion of cutting tool, Er Qieyou Effect ensure that the fly-cutting of ink layer, and separation will not occur and the broken of ink layer falls off, will not after dicing metal layer according to It is so exposed, the quality of product has been effectively ensured；
(5) original cutting resin knife is readily modified as steel edge cutting, and cutting process product surface is more smooth, tool wear The cutter that mesh number bigger may be used are reduced, cutter mesh number is bigger, chip smaller, cutting process product surface more light Sliding, chip smaller, product design is more beautiful, and product design is more beautiful；
(6) prepare on metallic substrates the Ji Dao to be formed, even muscle, pin field front plate front metal layer, with profit Metal wire is closely combined with pin in chip region and routing when follow-up bonding wire, even silver-plated at muscle to be used for follow-up plated conductive pipe Foot is tin plating, and process is simple, cost reduction；
(7) front metal layer of Ji Dao and pin is gold, silver, copper, nickel or nickel palladium, capsulation material and gold, silver, copper, nickel or Nickel palladium binding ability is good, it is not easy to cause to be layered；
(8) metal wire that chip is connect with pin routing is gold thread, silver wire, copper wire or aluminum steel, and material is inert material, is protected Deposit that the time is long, and conductivity and thermal diffusivity are good.
(9) use this programme, short-circuit ratio that can be reduced to 0PPM；It ensure that the situation of 0 short circuit occurs, shape pin face Increase brush ink, pin fastness can be improved 30% or more；
(10) packaging method and structure of this programme with respect to DFN QFN the encapsulating products integrated level higher such as MIS, cost is more It is low, cost-effective 20% or more.
Description of the drawings
Fig. 1 is structural schematic diagram after the load of the present invention；
Fig. 2 is structural schematic diagram after the ball bonding of the present invention；
Fig. 3 is structural schematic diagram after the encapsulating of the present invention；
Fig. 4 is structural schematic diagram after the back etched of the present invention；
Fig. 5 is structural schematic diagram after brush ink of the present invention；
Fig. 6 is structural schematic diagram after exposure imaging of the present invention；
Fig. 7 is structural schematic diagram after present invention plating；
Fig. 8 is structural schematic diagram after present invention cutting.
Figure label explanation：
1, substrate；2, front metal layer；3, chip；4, lead；5, encapsulated layer；6, back etched area；7, ink layer；8, it manages Foot metal layer.
Specific implementation mode
With reference to the accompanying drawings of the specification and specific embodiment, the present invention is described in detail.
Embodiment 1
As shown in figures 1-8, a kind of high reliability planar salient point type packaging method, using planar salient point type packaging method, The extra metallic region setting ink layer overleaf etched after substrate back etching step, ink layer 7 are covered in metallic region 1 pin side of surface and metal substrate, 1 pin of metal substrate protrude from ink layer 7.Ink layer 7 can ensure welding procedure In, prevent the short circuit generated by bridging；It is only welded in the part that must be welded, solder is avoided to waste；Reduce butt welding splicing The Cu-W ore deposit of slot；Prevent degradation of insulation, corrosion caused by the outside environmental elements such as dust, moisture content；With high-insulativity, make circuit Densification be possibly realized.The ink layer 7 of protrusion effectively increases whole glue surface of grabbing and accumulates after increasing pin metal layer 8, And glue surface product is grabbed in the side that is the increase in of bigger, brush coating area is big when brush coating, and fastness is more preferable, and leakage brush rate reduces, whole Solderability is more outstanding, also increases the area of electroplated metal layer, and pin metal layer 8 is effectively ensured and is firmly fixed to pin On, 8 expulsion rate of pin metal layer is reduced, ensures whole pin firmness and product quality, when sealing survey, due to pin height The area bigger for spending higher, especially side, probe contact performance is more preferable when test, and poor contact rate rate is greatly reduced, inspection Lower error rate is surveyed, the testing cost in later stage is reduced, pin protrusion, since pin is higher than plastic-sealed body, is surveyed when sealing survey Probe contact is more preferable when examination, and poor contact probability can be greatly reduced, and improves test UPH, reduces cost, pcb board on product SMT When, the contact area of pin and tin cream is increased, can be improved thrust of the product on pcb board, improves the reliable of product after upper plate Property, electrically；On product after PCB, product has certain gap with PCB, is more conducive to the heat dissipation of product..
Overall step is as follows：
1) one piece of metal substrate 1 is taken；
2) photopolymer layer is respectively sticked at 1 front of metal substrate, the back side；
3) 1 positive part photopolymer layer of metal substrate is removed, prepares to form Ji Dao on metal substrate 1, connects muscle, draws Foot；
4) prepare on metal substrate 1 Ji Dao to be formed, even muscle, pin field front plate front metal layer 2, even muscle Locate silver-plated；
5) the remaining photopolymer layer in 1 upper layer of metal substrate is removed, etching region is exposed；
6) half-etching is carried out to the dry film region that step 5 removes, forms the half-etched regions of recess on metal substrate 1, It is opposite simultaneously to form Ji Dao and pin；
7) chip 3 is carried out on the base island front metal layer 2 of metal substrate 1 to be implanted into, form integrated circuit or discrete component Array type aggregate semi-finished product；
8) semi-finished product that operation is implanted into having completed chip 3 carry out routing, form lead 4；
9) it encapsulates, it is rear to cure, form encapsulating 5；
10) photopolymer layer is pasted again in 1 face of Metal Substrate backboard；
11) photopolymer layer at the 1 half-etched regions back side of removal metal substrate, to expose the region for subsequently needing to etch；
12) at 1 back side of metal substrate is carried out to the region not by dry film covering total eclipse quarter, forms back etched area 6, makes base Island and pin protrusion plastic-sealed body surface；
13) the extra metallic region setting ink layer 7 overleaf etched after substrate back etching step；
The step of ink layer 7 are arranged is：
A, in one layer of ink of substrate back brush；SMT gluing equipments can be used directly herein and carry out brush ink, ink is photosensitive material Material, is a kind of liquid photo-imaging solder mask, a series of spies such as electrical property, heat resisting temperature, anti-flammability, reliability according to product Property choose suitable ink, use green oil in the present embodiment.Green oil, that is, liquid photo-imaging solder mask is that a kind of acrylic acid is oligomeric Object.It as a kind of protective layer, is not required to coated in printed circuit board on the circuit and base material of welding, or is used as solder resist, it is therefore an objective to Digital preservation is formed by line pattern.
B, after once toasting, one-step solidification ink；For baking temperature at 75 ± 5 DEG C, the time is 50 ± 10min；
C, the ink after solidification is showed metal pin by exposing, developing；Using the liquid medicine that develops for carbonic acid when development Sodium.
D, secondary baking carries out secondary curing ink.Secondary baking temperature is at 165 ± 5 DEG C, time 6h.Secondary baking So that ink curing, be fixed on substrate, and due to this baking, ink shrinks 40% or so, using secondary curing and The method of exposure imaging, it is ensured that ink will not fall off, while ensureing that subsequent technique is smoothed out, after eliminating needs The continuous ink for increasing metal pin position.Back etched region metal area extra after etching is covered according to product design shape Domain forms target design shape.1 back side excess ink layer 2 of metal substrate is removed in favor of subsequent using exposure, developing process Electroplating technology operation.
14) in the Ji Dao of protrusion, pin plating metal, pin metal layer 8 is formed；
15) cutting operation, product separation are carried out after UV films being sticked in plastic-sealed body front.
Original encapsulation step only carries out pin and Ji Dao plating；The existing original etching of step only removes part metals, we Case removes all unwanted copper materials, is in the prior art that even pin, the Ji Dao of product is electroplated in muscle with metal base, passes through Our scheme is crossed, all Copper base materials of product are all corroded, and no Metal Cutting are belonged in cutting process, directly by chip chamber Metallic substrates first remove, and when cutting separating chips, cutter only need to cut plastic packaging material, tin, silver and ink layer, and Conventionally, as there is metal layer, cutting stress hair, in cutting, ink layer is crushed and shifts frequent occurrence, causes The decline of quality, bad product rate rises after ink layer is added, and practicability is not strong, using this programme, suffered by cutting process product Stress reduce by 50% or more, avoid product from being layered, improve product reliability, cutting when only need cutting due to tin and Silverly soft, cutting stress is small, and cutting abrasion is small, and chip reliability improves, it is possible to reduce the abrasion of cutting tool, and effectively It ensure that the fly-cutting of ink layer, separation will not occur and the broken of ink layer falls off, it will not metal layer be still after dicing It is exposed, the quality of product has been effectively ensured.And ensure that the integrated level of height, relative to existing QFN encapsulate, it is original if it is The chip of 2.6mm length and width needs to make the package size of 9*9mm, and density is low, and welding wire consumption is more, using this programme, it is only necessary to Using 4.5*5mm package sizes, purpose increases, and size is reduced, and welding wire consumption also reduces, and short-circuit probability is 0, is effectively ensured Yields.
This programme uses the method that ink layer is added in substrate back on the basis of planar salient point type encapsulates, and effectively solves Metal pin of the back substrate due to directly etching determined since the regional metal of etching is exposed, when leading to carry out patch Distance is close between pin, there is the risk of short circuit, and after cutting, the area of pin is small, and pin grabs the weak problem of glue ability, ensures It will not occur short circuit after installation, and pin grabs the strong effect of glue ability.The ink layer 7 of protrusion is increasing pin metal layer 8 Afterwards, effectively increase it is whole grab glue surface product, and glue surface product is grabbed in the side that is the increase in of bigger, and brush coating area is big when brush coating, jail Solidity is more preferable, and leakage brush rate reduces, and whole solderability is more outstanding, also increases the area of electroplated metal layer, is effectively ensured Pin metal layer 8 is firmly fixed on pin, reduces 8 expulsion rate of pin metal layer, ensures whole pin firmness and product Quality, seal survey when, due to the area bigger of pin height higher, especially side, probe contact performance when test More preferably, poor contact rate rate is greatly reduced, and detects lower error rate, reduces the testing cost in later stage.Pin protrusion is surveyed in envelope When, since pin is higher than plastic-sealed body, probe contact is more preferable when test, and poor contact probability can be greatly reduced, and improves and surveys UPH is tried, reduces cost, on product SMT when pcb board, the contact area of pin and tin cream is increased, product can be improved in pcb board On thrust, improve upper plate after product reliability, electrically；On product after PCB, product has certain gap with PCB, more Be conducive to the heat dissipation of product.
Embodiment 2
Embodiment 2 is substantially the same manner as Example 1, also resides in, it is preferred that in step A further includes by the substrate after brush ink It is placed in vacuum tank, is vacuumized.When vacuumizing, select 0.08-0.1MPa, the time in 5-10min, in brush ink During, due to having bubble in ink, the substrate after brush ink is placed in vacuum tank, is vacuumized, effectively prevent producing The generation of product air entrapment ensure that the quality of product, prevent from introducing new defect.And due to the baking procedure of front and back two step, The step of vacuumizing also effectively prevent in the baking stage, and bubble leads to the fragmentation and out-of-flatness of ink layer when baking, influences whole Body performance, height when can also prevent ink from shrinking is inconsistent, causes pin protrusion height inconsistent, in the subsequent process can Brush coating defect is caused, new circuit defect is introduced, such as tin amount difference on several pins, will appear after leading to product SMT Reflow Solderings The security risks such as slide, set up a monument.
Embodiment 3
Based on the above method, a kind of high reliability planar salient point type encapsulating structure, including in chip bearing substrate, routing Foot bearing base, chip 3, lead 4 and plastic-sealed body, the chip bearing substrate include the front metal of Ji Dao and Ji Dao Layer 2, foot bearing base includes the front metal layer 3 of pin and pin in the routing, even has metal layer 2, chip on muscle Chip 3 is implanted on the front metal layer 2 of bearing base, 3 front of chip and front metal layer 2 connect system with metal wire both ends respectively At encapsulating structure semi-finished product, encapsulating structure semi-finished product front and neighboring form the back side for encapsulating the islands 5, Bing Shiji and pin Plastic-sealed body surface is protruded from, protrudes the Ji Dao at the back side, pin surface is coated with pin metal layer 8, in addition to the back side of pin metal layer 8 Excess metal region is ink layer.The front metal layer 2 of Ji Dao and pin is gold and silver, copper, nickel or nickel palladium.Chip 3 is beaten with pin The lead 4 of line connection is gold thread, silver wire, copper wire or aluminum steel.
Schematically the invention and embodiments thereof are described above, description is not limiting, not In the case of the spirit or essential characteristics of the present invention, the present invention can be realized in other specific forms.Institute in attached drawing What is shown is also one of the embodiment of the invention, and actual structure is not limited to this, any attached in claim Icon note should not limit the claims involved.So if those skilled in the art are enlightened by it, do not departing from In the case of this creation objective, frame mode similar with the technical solution and embodiment are not inventively designed, it should all Belong to the protection domain of this patent.In addition, one word of " comprising " is not excluded for other elements or step, "one" word before the component It is not excluded for including " multiple " element.The multiple element stated in claim to a product can also by an element by software or Person hardware is realized.The first, the second equal words are used to indicate names, and are not represented any particular order.

Claims (10)

1. a kind of high reliability planar salient point type packaging method, uses planar salient point type packaging method, it is characterised in that：In substrate The extra metallic region setting ink layer (7) overleaf etched after back etched step, ink layer (7) are covered in metallic region Surface and metal substrate (1) pin side, metal substrate (1) pin protrude from ink layer (7).
2. a kind of high reliability planar salient point type packaging method according to claim 1, it is characterised in that：Ink layer is set The step of be：
A, in one layer of ink of substrate back brush；
B, after once toasting, one-step solidification ink；
C, the ink after solidification is showed metal pin by exposing, developing；
D, secondary baking carries out secondary curing ink, and ink is shunk, and pin protrudes from ink layer (7).
3. a kind of high reliability planar salient point type packaging method according to claim 2, it is characterised in that：The ink For liquid photo-imaging solder mask.
4. a kind of high reliability planar salient point type packaging method according to claim 2, it is characterised in that：Step A also Including the substrate after brush ink to be placed in vacuum tank, vacuumized.
5. a kind of high reliability planar salient point type packaging method according to claim 2, it is characterised in that：Primary baking temperature For degree at 75 ± 5 DEG C, the time is 50 ± 10min, and secondary baking temperature is at 165 ± 5 DEG C, time 6h.
6. according to a kind of any high reliability planar salient point type packaging methods of claim 1-5, overall step is as follows：
1) one piece of metal substrate (1) is taken；
2) photopolymer layer is respectively sticked at metal substrate (1) front, the back side；
3) the positive part photopolymer layer of metal substrate (1) is removed, prepares to form Ji Dao on metal substrate (1), connects muscle, draws Foot；
4) prepare on metal substrate (1) Ji Dao to be formed, even muscle, pin field front plate front metal layer (2), even muscle Locate silver-plated；
5) the remaining photopolymer layer in metal substrate (1) upper layer is removed, etching region is exposed；
6) half-etching is carried out to the dry film region that step 5 removes, forms the half-etched regions of recess on metal substrate (1), together When opposite form Ji Dao and pin；
7) chip (3) is carried out on the base island front metal layer (2) of metal substrate (1) to be implanted into, form integrated circuit or discrete member The array type aggregate semi-finished product of part；
8) semi-finished product that operation is implanted into having completed chip (3) carry out routing, form lead (4)；
9) it encapsulates, it is rear to cure, form encapsulating (5)；
10) photopolymer layer is pasted again in Metal Substrate backboard (1) face；
11) photopolymer layer for removing metal substrate (1) half-etched regions back side, to expose the region for subsequently needing to etch；
12) region not by dry film covering is carried out total eclipse quarter at metal substrate (1) back side, the islands Shi Ji and pin protrude plastic-sealed body Surface；
13) the extra metallic region setting ink layer overleaf etched after substrate back etching step；
14) in the Ji Dao of protrusion, pin plating metal, pin metal layer (8) is formed；
15) cutting operation, product separation are carried out after UV films being sticked in plastic-sealed body front.
7. a kind of high reliability planar salient point type encapsulating structure, it is characterised in that：The substrate back etching of encapsulating structure removes pin Outer region is provided with ink layer (7), and ink layer (7) is covered in metallic region surface and metal substrate (1) pin side, Metal substrate (1) pin protrudes from ink layer (7).
8. a kind of high reliability planar salient point type encapsulating structure according to claim 7, it is characterised in that：It is held including chip Foot bearing base, chip (3), lead (4) and plastic-sealed body, the chip bearing substrate include Ji Dao in load pedestal, routing And the front metal layer (2) of Ji Dao, foot bearing base includes the front metal layer of pin and pin in the routing (3), even have metal layer (2) on muscle, implantation chip (3) on the front metal layer (2) of chip bearing substrate, chip (3) front and Front metal layer (2) connect with metal wire both ends encapsulating structure semi-finished product are made respectively, and encapsulating structure semi-finished product are positive and outer Circumferential edges, which are formed, encapsulates (5), and the back side of the islands Bing Shiji and pin protrudes from plastic-sealed body surface, protrudes Ji Dao, the pin table at the back side Face is coated with pin metal layer (8), and ink layer (7) is covered in metallic region surface and metal substrate (1) pin side, Metal Substrate Plate (1) pin protrudes from ink layer (7).
9. a kind of high reliability planar salient point type encapsulating structure according to claim 8, it is characterised in that：Ji Dao and pin Front metal layer (2) be gold and silver, copper, nickel or nickel palladium.
10. a kind of high reliability planar salient point type encapsulating structure according to claim 8, it is characterised in that：Chip (3) with The lead (4) of pin routing connection is gold thread, silver wire, copper wire or aluminum steel.
CN201810399646.XA 2018-04-28 2018-04-28 A kind of high reliability planar salient point type encapsulating method and structure Pending CN108389805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810399646.XA CN108389805A (en) 2018-04-28 2018-04-28 A kind of high reliability planar salient point type encapsulating method and structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810399646.XA CN108389805A (en) 2018-04-28 2018-04-28 A kind of high reliability planar salient point type encapsulating method and structure

Publications (1)

Publication Number Publication Date
CN108389805A true CN108389805A (en) 2018-08-10

Family

ID=63065018

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810399646.XA Pending CN108389805A (en) 2018-04-28 2018-04-28 A kind of high reliability planar salient point type encapsulating method and structure

Country Status (1)

Country Link
CN (1) CN108389805A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112831809A (en) * 2020-12-31 2021-05-25 广东杰信半导体材料股份有限公司 Lead frame processing method
CN113192921A (en) * 2021-06-25 2021-07-30 江苏长晶浦联功率半导体有限公司 Packaging frame structure, manufacturing method and chip packaging structure
CN113299565A (en) * 2021-07-28 2021-08-24 江苏长晶浦联功率半导体有限公司 Chip packaging method and chip packaging structure
CN113354449A (en) * 2021-07-16 2021-09-07 上海富乐华半导体科技有限公司 Method for preventing silver on copper side wall of ceramic copper-clad substrate during chemical silver deposition
CN115719713A (en) * 2023-01-09 2023-02-28 江苏长晶浦联功率半导体有限公司 Flat pin-free element and packaging method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050287710A1 (en) * 2004-06-29 2005-12-29 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package and method for manufacturing the same
CN102005432A (en) * 2010-09-30 2011-04-06 江苏长电科技股份有限公司 Packaging structure with four pin-less sides and packaging method thereof
US20110159643A1 (en) * 2009-12-31 2011-06-30 Siliconware Precision Industries Co., Ltd. Fabrication method of semiconductor package structure
CN102543937A (en) * 2011-12-30 2012-07-04 北京工业大学 Flip chip on-chip package and manufacturing method thereof
CN105228363A (en) * 2015-08-28 2016-01-06 江门崇达电路技术有限公司 A kind of manufacture method of solder mask
CN106158742A (en) * 2016-08-30 2016-11-23 长电科技（滁州）有限公司 A kind of planar salient point type is without Metal Cutting packaging technology and encapsulating structure thereof
CN208903998U (en) * 2018-04-28 2019-05-24 长电科技（滁州）有限公司 A kind of high reliability planar salient point type encapsulating structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050287710A1 (en) * 2004-06-29 2005-12-29 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package and method for manufacturing the same
US20110159643A1 (en) * 2009-12-31 2011-06-30 Siliconware Precision Industries Co., Ltd. Fabrication method of semiconductor package structure
US20110156227A1 (en) * 2009-12-31 2011-06-30 Siliconware Precision Industries Co., Ltd. Semiconductor package structure
CN102005432A (en) * 2010-09-30 2011-04-06 江苏长电科技股份有限公司 Packaging structure with four pin-less sides and packaging method thereof
CN102543937A (en) * 2011-12-30 2012-07-04 北京工业大学 Flip chip on-chip package and manufacturing method thereof
CN105228363A (en) * 2015-08-28 2016-01-06 江门崇达电路技术有限公司 A kind of manufacture method of solder mask
CN106158742A (en) * 2016-08-30 2016-11-23 长电科技（滁州）有限公司 A kind of planar salient point type is without Metal Cutting packaging technology and encapsulating structure thereof
CN208903998U (en) * 2018-04-28 2019-05-24 长电科技（滁州）有限公司 A kind of high reliability planar salient point type encapsulating structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112831809A (en) * 2020-12-31 2021-05-25 广东杰信半导体材料股份有限公司 Lead frame processing method
CN113192921A (en) * 2021-06-25 2021-07-30 江苏长晶浦联功率半导体有限公司 Packaging frame structure, manufacturing method and chip packaging structure
CN113354449A (en) * 2021-07-16 2021-09-07 上海富乐华半导体科技有限公司 Method for preventing silver on copper side wall of ceramic copper-clad substrate during chemical silver deposition
CN113299565A (en) * 2021-07-28 2021-08-24 江苏长晶浦联功率半导体有限公司 Chip packaging method and chip packaging structure
CN115719713A (en) * 2023-01-09 2023-02-28 江苏长晶浦联功率半导体有限公司 Flat pin-free element and packaging method thereof
CN115719713B (en) * 2023-01-09 2023-05-30 江苏长晶浦联功率半导体有限公司 Flat pin-free element and packaging method thereof

Similar Documents

Publication Publication Date Title
CN108389805A (en) A kind of high reliability planar salient point type encapsulating method and structure
CN102005432B (en) Packaging structure with four pin-less sides and packaging method thereof
TW526598B (en) Manufacturing method of semiconductor device and semiconductor device
KR100720607B1 (en) Semiconductor device
KR102082941B1 (en) Resin-encapsulated semiconductor device and method of manufacturing the same
TWI380500B (en) Integrated circuit device having antenna conductors and the mothod for the same
US8749035B2 (en) Lead carrier with multi-material print formed package components
TW200834859A (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
CN102339809B (en) QFN (quad flat non-lead) package with multiple circles of pins and manufacturing method thereof
CN103843133B (en) Leaded carriers with thermal welding package parts
CN106158742B (en) Plane bump type metal-free cutting packaging process and packaging structure thereof
JP2001077278A (en) Semiconductor package, lead frame thereof, manufacture of semiconductor package and mold thereof
TW511401B (en) Method for manufacturing circuit device
CN101814446A (en) Island expose and multi-salient-point island expose lead frame structure and carving and plating method thereof
CN103794587A (en) Embedded type rewiring line packaging structure of chip with good heat dissipation performance and manufacturing method thereof
TW456008B (en) Flip chip packaging process with no-flow underfill method
TWI479580B (en) Quad flat no-lead package and method for forming the same
CN108281397A (en) Chip-packaging structure and packaging method
CN208903998U (en) A kind of high reliability planar salient point type encapsulating structure
CN103887256A (en) High-cooling-performance chip-embedded type electromagnetic shielding encapsulating structure and manufacturing method thereof
CN103531549A (en) Semiconductor chip packaging structure and packaging method
WO2016107298A1 (en) Molding packaged mini mobile phone intelligent card, and packing method
CN108364928B (en) Integrated circuit packaging structure and processing method thereof
CN203787410U (en) High radiating chip embedded electromagnetic shielding packaging structure
CN106409689B (en) High-density circuit chip packaging process

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination