CN116207057A - Processing structure and processing method of microminiature package - Google Patents

Processing structure and processing method of microminiature package Download PDF

Info

Publication number
CN116207057A
CN116207057A CN202310306198.5A CN202310306198A CN116207057A CN 116207057 A CN116207057 A CN 116207057A CN 202310306198 A CN202310306198 A CN 202310306198A CN 116207057 A CN116207057 A CN 116207057A
Authority
CN
China
Prior art keywords
metal
metal base
base island
chip
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202310306198.5A
Other languages
Chinese (zh)
Other versions
CN116207057B (en
Inventor
张博威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Xinyou Microelectronics Technology Co ltd
Original Assignee
Shenzhen Xinyou Microelectronics Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Xinyou Microelectronics Technology Co ltd filed Critical Shenzhen Xinyou Microelectronics Technology Co ltd
Priority to CN202310306198.5A priority Critical patent/CN116207057B/en
Publication of CN116207057A publication Critical patent/CN116207057A/en
Application granted granted Critical
Publication of CN116207057B publication Critical patent/CN116207057B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention discloses a processing structure and a processing method of a microminiature package, wherein the processing structure comprises a metal base island, a chip is arranged on part or part of the metal base island, a plastic package body wraps the surfaces of the metal base island and the chip, a removable substrate structure is arranged at the bottom of the metal base island, and a temporary barrier layer or a metal lead layer is arranged at the periphery of the bottom of the metal base island, so that the bottom of the metal base island is lower than the bottom of the plastic package body. The method comprises the steps of arranging a metal base island on a strippable substrate structure, arranging a temporary barrier layer or a metal lead layer on the periphery of the bottom of the metal base island, dividing plastic packaging processing into two operations, respectively arranging the two operations after the connection steps of the metal base island and a chip, and finally removing the strippable part of the bottom of the metal base island, so that the bottom of the metal base island is lower than the bottom of a plastic packaging body, and a convex metal electrode is the position to be processed, thereby reducing the difficulty of processing and aligning a pattern circuit, reducing the difficulty of a processing technology of an electronic device and improving the yield of a product.

Description

Processing structure and processing method of microminiature package
Technical Field
The invention relates to the technical field of chip packaging, in particular to a processing structure and a processing method of a microminiature package.
Background
The traditional chip package adopts a lead frame, and the manufacturing process comprises techniques such as surface mounting, wire bonding and the like, so that the technology has the defects of low efficiency and high cost, and cannot conform to the development trend of miniaturization, intellectualization, high performance and high reliability of electronic products, so that the board-level package is produced. Board level packaging, also called secondary microelectronic packaging, is called secondary packaging for short, i.e. discrete components with packaging are assembled on a substrate (PCB or other wiring substrate) by adopting surface mount technology (Surface Mount Techology, SMT) and other technologies, and the whole power density, current tolerance and the like are improved by replacing the traditional wire bonding technology with the process flow of a Printed Circuit Board (PCB) or packaging substrate.
However, when the electronic device is gradually miniaturized, the device dimensions of 1.0mm by 0.6mm, 0.6mm by 0.3mm, etc. are appeared, and the existing board-level package chip is adopted, since the metal electrode of the existing board-level package is flush with the surface dimensions of the surrounding package shell, when the package is processed into the electronic device, there is a higher requirement on the line processing and alignment capability of the pattern, so that the ultra-small device is difficult to process and realize in the original structure.
Disclosure of Invention
In order to solve the problem that the existing device structure is difficult to process and realize due to the fact that the metal electrodes of the existing board-level package are flush with the package structure, the invention provides a processing structure and a processing method of a microminiature package, and on the premise that electrode metals for welding are buried in a plastic package body, the end parts of the metal electrodes are protruded out of the peripheral plastic package body, and the protruded metal electrodes are positions to be processed, so that the difficulty of processing and aligning of a pattern circuit is reduced, the difficulty of a processing technology of an electronic device is reduced, and the yield of products is improved.
The technical scheme of the invention is as follows:
a processing structure of a microminiature package comprises a metal base island, wherein a chip is arranged on part or part of the metal base island, a plastic package body wraps the surfaces of the metal base island and the chip, a removable substrate structure is arranged at the bottom of the metal base island, a temporary barrier layer or a metal lead layer is arranged at the periphery of the bottom of the metal base island, and the bottom of the metal base island is lower than the bottom of the plastic package body.
The metal base island is arranged on the basis of the removable base structure, the base structure can be directly removed after the surface of the metal base island is wrapped by the plastic package body in the later period, so that the electrode part and the chip part of the metal base island can be embedded in the plastic package body, meanwhile, the bottom of the metal base island is lower than the bottom of the plastic package body due to the existence of the temporary barrier layer and the metal lead wire layer, after the temporary barrier layer is removed or after the metal base island and the bottom of the metal lead wire layer form a metal protection layer through electroplating, the bottom of the metal base island protrudes out of the bottom of the plastic package body, and the metal base island is processed in the later period, such as metal base island welding and the like, without considering the alignment problem.
The processing structure of the microminiature package comprises a first plastic package body and a second plastic package body from bottom to top, wherein the first plastic package body is attached to the substrate structure and wraps the metal base island and the chip, and the second plastic package body wraps the first plastic package body and the connection structure between the chip and the metal base island.
The processing structure of the microminiature package comprises a carrier and a peelable layer from bottom to top, wherein the peelable layer is made of a metal material.
Further, the peelable layer is of a double-layer metal structure and comprises a first metal layer and a second metal layer from bottom to top, and the surface of the first metal layer is of a smooth surface structure.
Still further, the second metal layer has a thickness of 3-10 microns.
In the processing structure of the microminiature package, the occupied area of the metal base island and the occupied area of the temporary barrier layer cover the surface of the base structure, and the occupied area of the metal base island and the occupied area of the temporary barrier layer are of complementary structures.
Further, the bottom of the metal base island is lower than the bottom of the temporary barrier layer.
Further, the thickness of the metal base island is 20-100 micrometers, and the surface of the metal base island is at least 10 micrometers higher than the surface of the temporary barrier layer or the metal lead layer.
In the processing structure of the microminiature package, the thickness of the temporary barrier layer is 3-50 micrometers.
Further, the temporary barrier layer has a thickness of 10-15 microns.
In the processing structure of the microminiature package, the thickness of the metal base island is 20-100 micrometers.
In the processing structure of the microminiature package, the bottom of the metal base island is connected with the metal lead layer, and the metal lead layer is respectively connected with two adjacent metal base islands which are not connected with each other.
The chip is a plurality of devices which are arranged in an array and are arranged on the same carrier when being packaged, in the invention, the chip is orderly arranged on a large substrate structure to form the arrangement of a plurality of devices, one end of a metal lead layer is in contact connection with a metal base used as a bearing disc, the other end of the metal lead layer is in contact connection with a metal base used for arranging the chip of another device, the two metal bases connected by the metal lead layer are not metal bases of the same device, and are metal bases of two adjacent devices positioned on the same carrier.
The existence of the metal lead wire layer enables the bottom of the metal base island to be lower than the bottom of a part of the plastic package body, although the bottoms of the metal lead wire layer, the metal base island and the plastic package body of the other part are flush after the peelable layer is removed, under the condition, after the metal protection layer is formed through electroplating, the surfaces of the bottoms of the metal lead wire layer and the metal base island form the metal protection layer protruding out of the bottom of the plastic package body, and finally, the plane to be processed of the metal base island in the later stage is lower than the bottom of the plastic package body without alignment.
Further, the thickness of the metal lead layer is 3-40 micrometers, and the width of the electroplated lead is 50-250 micrometers.
A processing method of microminiature package is to set a metal base island on a strippable base structure, set a temporary barrier layer or a metal lead layer around the bottom of the metal base island, divide the plastic package processing into two operations and place the two operations separately after the steps of mounting the metal base island and the chip and connecting the metal base island and the chip, finally remove the strippable part of the bottom of the metal base island so that the bottom of the metal base island is lower than the bottom of the plastic package body.
Firstly, the peelable substrate structure at the bottom of the metal base island and the peelable temporary barrier layer or the metal lead layer with a blocking function are processed, and then the plastic packaging operation is carried out, so that the metal base island is naturally higher than the bottom of the metal base island under the blocking of the temporary barrier layer or the metal lead layer, and the metal base island protrudes out of the plastic packaging body (at least part of the plastic packaging body) to avoid the metal base island and the metal base island to be in the same plane, thereby the alignment operation is not needed in the subsequent processing. And the processing action of plastic package is divided into two steps, and the two steps are respectively arranged in the working procedures after the metal base island and the chip are installed and the metal base island and the chip are connected, so that the electrode part of the metal base island for welding is completely embedded in the plastic package body, and the stability of the device is ensured.
According to the processing method of the microminiature package, the substrate structure is covered with the material capable of being exposed and developed, the area where the non-temporary barrier layer is located is exposed after exposure and development, and the temporary barrier layer is left after etching.
According to the processing method of the miniature package, the metal base island and the temporary barrier layer are formed on the substrate structure in an electroplating manner, the metal base island and the temporary barrier layer are formed in steps by electroplating, the surface of the substrate structure is coated with the plating resist film, the area where the metal base island or the temporary barrier layer is not arranged is shielded, the area where the metal base island to be electroplated is located or the area where the temporary barrier layer is located is exposed through an exposure and development method, and the metal base island or the temporary barrier layer is formed after electroplating.
The metal base island comprises a first metal base island used for arranging a chip and a second metal base island used as a lead-out bearing disc of a chip electrode, wherein a metal solder layer is arranged on the surface of the first metal base island.
Further, the chip is connected with the first metal base island through the metal solder layer through welding, or is connected with the first metal base island through ultrasonic heating friction.
In the processing method of the microminiature package, after plastic packaging, a first plastic packaging body and a second plastic packaging body are respectively formed, wherein the processing procedure of the first plastic packaging body is positioned after the mounting procedure of the metal base island and the chip, and the processing procedure of the second plastic packaging body is positioned after the connecting procedure of the metal base island and the chip.
Further, after the processing procedure of the first plastic package body is completed, laser holes are formed above the chip by laser, and through the metallized holes, or the electroplated holes, or the printed conductive adhesive, chip electrode outgoing lines are arranged on the chip and connected with the metal base islands serving as outgoing receiving discs, so that the metal base islands are connected with the chip.
According to the processing method of the microminiature package, after the substrate structure and the temporary barrier layer are removed, the bottom of the metal base island is coated with the metal protective layer.
According to the processing method of the miniature package, the metal lead layer is formed on the surface of the substrate structure through the pattern electroplating method, and then the metal base island is formed on the surface of the metal lead layer through the pattern electroplating method.
In the processing method of the microminiature package, after the substrate structure is removed, a metal protection layer is formed by electroplating at the bottoms of the metal base island and the metal lead layer.
The processing process of the microminiature package comprises the following steps:
and S1, providing a carrier.
The carrier material is a material with high rigidity.
S2, attaching a layer of peelable layer on the surface of the carrier.
The peelable layer is of a double-layer metal structure and comprises a first metal layer and a second metal layer from bottom to top, and the first metal layer is connected with the second metal layer. The thickness of the second metal layer is 3-10 microns, and the surface of the second metal layer is of a smooth surface structure.
S3, processing the surface of the peelable layer to form a temporary barrier layer or a metal lead layer.
The processing modes of the temporary barrier layer comprise:
in the first mode, the surface of the strippable layer is covered with an exposable and developable material, the electrode area with electroplating is exposed by the exposable and developable method according to the design of a chip circuit, a temporary barrier layer is formed on the conductive strippable layer by electroplating through electroplating processing, and finally the exposable and developable material is removed.
And secondly, electroplating the surface of the peelable layer to form a temporary structure covering the surface of the peelable layer, covering the temporary structure with an exposable and developable material, exposing and developing the temporary structure to expose part of the non-temporary barrier layer, removing the exposed non-electrode area part in an etching mode, completely removing all temporary structures in the area, and leaving the electrode area which is needed to finish the processing of the temporary barrier layer, and finally removing the exposable and developable material.
According to the third mode, a temporary barrier layer is formed on the surface of the peelable layer through a mode of printing a metal material and then baking.
The temporary barrier layer is made of a metal material. The temporary barrier layer is made of tin, titanium or nickel.
The thickness of the temporary barrier layer is 3-50 microns, preferably 10-15 microns.
In the processing of the metal lead layer, a latticed metal lead layer is formed on the surface of the peelable layer in a pattern plating mode, the surface of the peelable layer is covered with an exposable and developable material, the electrode area with plating is exposed by an exposal and developing method according to the chip circuit design, the metal lead layer is formed on the conductive peelable layer in a plating mode through the plating processing, and finally the exposal and developable material is removed.
The leads of the metal lead layer are distributed in a grid shape and are respectively connected with the metal base islands of two different devices, the thickness is 3-40 micrometers, and the width is 50-250 micrometers.
S4, processing the surface of the peelable layer or the metal lead layer to form a plurality of metal base islands.
The surface of the strippable layer is also provided with a temporary barrier layer, on the basis, an anti-plating film is adhered on the surface of the strippable layer, an electrode area to be electroplated is exposed through an exposure and development method, and then a plurality of metal base islands are formed through an electroplating method, wherein the number of the metal base islands is two or more. In another case, a metal lead layer is arranged on the surface of the strippable layer, a plating resist film is adhered on the surface of the metal lead layer, an electrode area to be electroplated is exposed through an exposure and development method, and then a plurality of metal base islands are formed through an electroplating method.
The thickness of the metal base island is 20-100 micrometers, which is at least 10 micrometers higher than the surface of the temporary barrier layer or the metal lead layer.
The metal base island and the temporary barrier layer are mutually complemented and do not interfere with each other, and the metal base island and the temporary barrier layer are overlapped to cover the surfaces of all the strippable layers.
Part of the metal base islands are used for placing chips, and part of the metal base islands are used as carrying discs for leading out electrodes on the front surfaces of the chips.
The metal-based islands are of two types according to the surface structure, wherein one type is a basic metal surface formed after electroplating, and the surface is free of metal solder and is used as a leading-out bearing disc of a front electrode of a chip; another type is a type of metal base island for placing chips, where a layer of metal solder is preformed on the surface of the metal base island, the preformed metal solder is usually gold or tin, the thickness of the metal solder is about 1-20 microns, and the preformed metal solder is formed during electroplating.
And S5, carrying out chip mounting on the metal base island.
When the chip is transferred, the chip is fixed on the surface of the prefabricated solder of the metal base island through soldering paste, solidification is completed through reflow, and the electrical property of the chip is led out, or the chip is fixed on the surface of the prefabricated solder of the metal base island through an ultrasonic heating friction mode, and the solidification of the chip and the leading-out of the electrical property are completed simultaneously. Both the above two methods are the existing methods for transferring chips.
S6, processing the first plastic package body, and enabling the first plastic package body to be wrapped on the surface of the carrier.
And (3) the first plastic package body wraps the surface of the carrier processed in the step (S5), and the peelable layer, the temporary barrier layer, the metal base island and the chip are wrapped in the first plastic package body.
The first plastic package is higher than the front electrode of the chip, i.e. the surface of the chip is completely wrapped, and the thickness of the first plastic package above the front electrode of the chip is 20-200 micrometers.
And S7, processing the first plastic package body to expose the surfaces of the chips and the metal base islands, and completing connection between the chips and connection between the metal base islands and the chips.
And penetrating the surface of the first plastic package body according to the positions of the metal base island and the chip by a laser perforation method, so that the front electrode of the chip and the surface of the metal base island serving as a bearing disc are exposed, or the front electrodes of the two connected chips or the back electrodes of the chip are exposed. In this way, a hole structure is arranged above the chip and the metal base island or the chip and the chip to be communicated with the outside, and chemical copper, sputtered copper and the like are matched with an electroplating process through a hole metallization process, or the front electrode of the chip is connected with the surface of the metal base island for leading out the bearing disc in a manner of printing conductive adhesive, or the front electrode of the chip is connected with the front electrode of the chip, or the back electrode of the chip is connected with the back electrode of the chip.
S8, processing to form a second plastic package body, and enabling the second plastic package body to be wrapped on the surface of the first plastic package body.
The second plastic package body covers the surface of the first plastic package body, and covers all structures on the upper part of the carrier, wherein the structures comprise a peelable layer, a temporary barrier layer, a metal base island, a metal lead layer, the first plastic package body, and an interconnection structure formed by a chip, a chip front electrode, a chip back electrode and a chip outgoing line are all inside the second plastic package body.
The second plastic package can be regarded as a reinforcing layer of all the above structures.
The second plastic package body is made of black material containing a glass fiber cloth structure, or can be made of yellow material containing the glass fiber cloth structure and black resin which are physically mixed.
Step S9, gradually removing the carrier, the peelable layer and the temporary barrier layer from bottom to top to expose the bottom of the metal base island, or gradually removing the carrier and the peelable layer from bottom to top to expose the bottom surfaces of the metal base island and the metal lead layer.
The carrier and the peelable layer are connected in a peelable structure, and after the carrier is removed by a physical jig force application method, or by heat peeling or chemical corrosion and etching, the peelable layer metal material is exposed.
And removing the metal layer by a physical or chemical method to expose the temporary barrier layer and the bottom of the metal base island. The peelable layer of the metal material may be removed by a physical method of grinding, such as grinding the peelable layer metal using a cloth, nylon, abrasive belt, or the like, or by etching the peelable layer metal with a chemical liquid to remove a double-layered metal structure of the peelable layer.
The temporary barrier layer is removed by a chemical processing method, or by laser ablation, and UV light (commonly referred to as ultraviolet) or carbon dioxide laser is used to remove the temporary barrier layer, wherein the bottom and the side surfaces of the metal base island are exposed.
When the first plastic package body is processed, the bottom of the metal base island in the step S9 is higher than the bottom of the first plastic package body due to the blocking of the temporary blocking layer, and the side surfaces and the bottom surface of the metal base island are exposed. In another case, after the carrier and the strippable layer are removed, the bottom surfaces of the metal lead layer and the metal base island are exposed and blocked by the metal lead layer, and the bottom surface of the first plastic package body above the metal lead layer is higher than the bottom surface of the metal base island, so that the bottom surface of the first plastic package body of the other part is flush with the bottom surfaces of the metal base island and the metal lead layer.
And S10, forming a metal protection layer on the side surface and the bottom surface of the metal base island.
The metal protection layer is substantially a metal protection layer, and a metal protection layer with oxidation resistance is formed on the surface (bottom surface+side surface) of the metal base island by a chemical method. The material of the metal protection layer is gold, silver or tin.
In another case, after electroplating, the bottom surface of the metal lead layer and the bottom surface of the metal base island form a metal protection layer, and the exposed metal lead is used as a current conducting path. In this case, all metal leads except the positions of the metal islands can be removed by physical or pattern etching according to the original pattern design.
After the above step S10 is completed, the product is cut to form individual devices, and the packaging process is completed.
According to the scheme, the invention has the beneficial effects that,
1. the electrode for welding is buried in the plastic package body, so that the stability of chip connection and the product quality are ensured.
2. Because the plastic packaging process is limited by the temporary barrier layer or the metal lead layer after the metal base island and the temporary barrier layer are formed, the bottom of the metal base island is lower than the bottom of the plastic packaging body, the temporary barrier layer is removed to form a metal protection layer or after the metal protection layer is electroplated on the surface of the metal base island, the metal base island protrudes out of the surface of the plastic packaging body, so that the welding effectiveness of a device is facilitated, the difficulty of processing and aligning a pattern circuit is reduced, the difficulty of a processing technology of an electronic device is reduced, and the yield of a product is improved.
3. The part of the metal base island protruding plastic package body comprises a bottom surface and a side surface, so that the weldable area of the later process is increased, and the strength of the multi-surface three-dimensional welding is higher than that of the single-surface welding, and the stability and the connectivity are better.
4. The parts of the metal base islands protruding out of the plastic package body are coated with metal protection layers, the sizes of the metal protection layers and the metal base islands are consistent, and the coating processing is not needed to be aligned.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a processing structure of a micro-package structure.
FIG. 2 is a schematic diagram of a structure for completing metal island processing.
FIG. 3 is a schematic view of the structure with the carrier, peelable layer, and temporary barrier removed.
Fig. 4 is a schematic diagram of the structure of a single device.
Fig. 5 is a schematic structural diagram of a chip of the same column on the same carrier connected to a chip lead wire through a metal lead layer.
Fig. 6 is a schematic diagram of the structure of all chip connections on the same carrier.
Fig. 7 is a schematic structural diagram of the second embodiment.
Fig. 8 is a schematic diagram of the structure of two independent chip connections.
Fig. 9 is a schematic diagram of a chip having two bonding pads.
Wherein, each reference sign in the figure:
1. a carrier; 2. a peelable layer; 3. a metal base island; 4. a temporary barrier layer; 5. a first plastic package body; 6. a chip; 7. a second plastic package body; 8. a metal protective layer; 9. a device; 10. a metal lead layer; 11. and (5) a chip outgoing line.
Description of the embodiments
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Examples
The processing structure of the microminiature package comprises a carrier 1 and a peelable layer 2 from bottom to top as shown in fig. 1. At least two metal base islands 3 are arranged on the surface of the peelable layer 2, temporary barrier layers 4 are arranged between the metal base islands 3 at the bottom positions of the metal base islands 3, the temporary barrier layers 4 and the metal base islands 3 are of complementary structures, and the overlapped areas of the temporary barrier layers 4 and the metal base islands 3 cover the surface of the whole peelable layer 2. The surfaces of the metal base island 3 and the temporary barrier layer 4 are wrapped by a first plastic package body 5, and a certain thickness exists in the first plastic package body 5 above the metal base island 3. Two metal base islands 3 are taken as a group, metal solder is attached to one metal base island 3, a chip 6 is installed through the metal solder, and a chip outgoing line 11 upwards bypasses the surface of the first plastic package body 5 and then downwards connects with the other metal base island 3. The second plastic package body 7 is attached to the surface of the chip outgoing line 11, and the second plastic package body 7 wraps all parts on the carrier 1, so that structural reinforcement is realized.
A processing method of a microminiature package comprises
Step S1, providing a carrier 1. The carrier 1 is made of a harder material, and since the encapsulated devices 9 are formed by processing a plurality of devices 9 on one carrier 1, and finally the individual devices 9 are formed by cutting, the carrier 1 is sized to carry the encapsulated devices 9 to be processed at the same time.
S2, attaching a layer of peelable layer 2 on the surface of the carrier 1. The peelable layer 2 is made of a metal material, and the double-layer metal of the peelable layer 2 is arranged on the surface of the carrier 1 by means of coating, electroplating and the like, so that the peelable layer 2 covers all areas of the surface of the carrier 1.
And S3, processing the surface of the peelable layer 2 to form a temporary barrier layer 4. The temporary barrier layer 4 is galvanically formed or etched to form the peelable layer 2 by means of electroplating or etching.
And S4, processing the surface of the peelable layer 2 to form a plurality of metal base islands 3, as shown in fig. 2. The metal islands 3 are formed by electroplating in the remaining areas of the peelable layer 2, the upper surfaces of the metal islands 3 being higher than the upper surfaces of the temporary barrier layers 4. During processing, the temporary barrier layer 4 prevents plating accumulation on the temporary barrier layer 4 by the plating resist.
And S5, mounting the chip 6 on the metal base island 3. The device 9 comprises two metal islands 3 in a group, wherein one metal island 3 is formed into a metal solder layer by electroplating, and then the chip 6 is mounted on the surface of the metal solder layer by welding or ultrasonic heating friction process, so that the chip 6 is mounted on the metal islands 3.
S6, processing the first plastic package body 5, and enabling the first plastic package body 5 to be wrapped on the surface of the carrier 1. At this time, the first plastic package body 5 is coated with the metal base island 3, the temporary barrier layer 4 and the chip 6, and the bottom surface of the first plastic package body 5 is higher than the bottom surface of the metal base island 3 due to the existence of the temporary barrier layer 4.
And S7, processing the first plastic package body 5 to expose the front electrode of the chip 6 and the surface of the metal base island 3 of the bearing disc for leading out the chip 6, and connecting the front electrode of the chip 6 and the metal base island 3. And laser perforation is carried out, a hole communicated with the upper part of the metal base island 3 and the chip 6 is formed, and then the chip outgoing line 11 is connected with the metal base island 3 in the modes of hole metallization, electroplating, conductive adhesive filling and the like.
And S8, processing to form a second plastic package body 7, and enabling the second plastic package body 7 to be wrapped on the surface of the first plastic package body 5. And (5) performing plastic packaging again to form a second plastic package body 7, and wrapping the chip outgoing line 11, the chip 6, the metal base island 3 and the first plastic package body 5.
Step S9, gradually removing the carrier 1, the peelable layer 2 and the temporary barrier layer 4 from bottom to top to expose the bottom and the side surfaces of the metal base island 3, as shown in fig. 3. The carrier 1 and the peelable layer 2 below the metal base island 3 are removed by physical grinding (such as grinding of non-woven cloth, nylon, abrasive belt and the like) or chemical biting of liquid medicine, and the temporary barrier layer 4 is removed by chemical liquid medicine or laser, so that the bottom surface and the side surface of the metal base island 3 and the bottom surface of the first plastic package body 5 are exposed.
And S10, forming a metal protection layer 8 on the side surface and the bottom surface of the metal base island 3.
Finally, dicing is performed to form individual devices 9, as shown in fig. 4.
Examples
A processing structure of a microminiature package comprises a carrier 1 and a peelable layer 2 from bottom to top. A latticed metal lead layer 10 and at least two metal islands 3 are provided on the surface of the peelable layer 2, and the two metal islands 3 are a group and form part of the same device 9. The upper surface of the metal lead layer 10 is lower than the upper surface of the metal base island 3, the bottom surfaces of the metal lead layer 10 and the metal base island 3 are flush, the metal lead layer 10 is arranged between two adjacent metal base islands 3 belonging to different devices 9, and the metal lead layer 10 is connected with the metal base islands 3 of the two different devices 9. The surfaces of the metal base island 3 and the metal lead layer 10 are wrapped by the first plastic package body 5, and a certain thickness exists on the first plastic package body 5 above the metal base island 3. Two metal base islands 3 of the same device 9 are taken as a group, metal solder is attached to one metal base island 3, a chip 6 is installed through the metal solder, and a chip outgoing line 11 upwards bypasses the surface of the first plastic package body 5 and then downwards connects with the other metal base island 3. Thus, along the same column of chips 6 in a certain direction of the carrier 1, the bottom metal islands 3 are connected by the metal lead layers 10, the surface metal islands 3 are connected by the chip lead lines 11, the chips 6 in this column are connected, and then, in the direction perpendicular to the direction, the two rows of chips 6 on both sides of the carrier 1 are connected by the chip lead lines 11, so that all the chips 6 on the same carrier 1 are connected. As shown in the figure, the chips 6 in two adjacent identical devices 9 along the vertical direction are connected by the chip outgoing line 11, and the chips 6 in two adjacent different devices 9 are connected by the metal lead layer 10, so that the chips 6 on the same column are connected in the vertical direction, and then the connection is realized by the chip outgoing line 11 in the two rows at the uppermost and the lowermost of the carrier 1, so that all the chips 6 in the same row are connected, and the connection of all the chips 6 on the carrier 1 is completed, as shown in fig. 5 and 6. And the second plastic package body 7 is attached to the surfaces of all the chip outgoing lines 11 on the same carrier 1, and the second plastic package body 7 wraps all the parts on the carrier 1, so that the reinforcement of the structure is realized.
A processing method of a microminiature package comprises
Step T1. Providing a carrier 1. The carrier 1 is made of a harder material, and since the encapsulated devices 9 are formed by processing a plurality of devices 9 on one carrier 1, and finally the individual devices 9 are formed by cutting, the carrier 1 is sized to carry the encapsulated devices 9 to be processed at the same time.
Step T2. A layer of peelable layer 2 is attached to the surface of the carrier 1. The peelable layer 2 is made of a metal material, and the double-layer metal of the peelable layer 2 is arranged on the surface of the carrier 1 by means of coating, electroplating and the like, so that the peelable layer 2 covers all areas of the surface of the carrier 1.
Step T3, processing and forming the metal lead layer 10 on the surface of the peelable layer 2. The plated lead layer 10 is formed by electroplating or etching the pattern or the peelable layer 2 is formed by etching. And step T4, processing and forming a plurality of metal base islands 3 on the surface of the electroplated lead layer 10. The metal islands 3 are formed by pattern plating on the surface of the plated lead layer 10, and the upper surfaces of the metal islands 3 are higher than the upper surfaces of the metal lead layer 10. During processing, the metal lead layer 10 prevents plating accumulation on the metal lead layer 10 by plating resistance.
And step T5, mounting the chip 6 on the metal base island 3. The device 9 comprises two metal islands 3 in a group, wherein one metal island 3 is formed into a metal solder layer by electroplating, and then the chip 6 is mounted on the surface of the metal solder layer by welding or ultrasonic heating friction process, so that the chip 6 is mounted on the metal islands 3.
And step T6, processing the first plastic package body 5, and wrapping the first plastic package body 5 on the surface of the carrier 1. At this time, the first plastic package body 5 is coated with the metal base island 3, the metal lead layer 10 and the chip 6, and the bottom surface of the first plastic package body 5 is higher than the bottom surface of the metal base island 3 due to the metal lead layer 10.
And step T7, processing the first plastic package body 5 to expose the front electrode of the chip 6 and the surface of the metal base island 3 of the bearing disc for leading out the chip 6, and connecting the front electrode of the chip 6 and the metal base island 3. And laser perforation is carried out, a hole communicated with the upper part of the metal base island 3 and the chip 6 is formed, and then the chip outgoing line 11 is connected with the metal base island 3 in the modes of hole metallization, electroplating, conductive adhesive filling and the like. At the same time, the chips 6 of the first and last row on the carrier 1 are connected.
Step T8. is processed to form a second plastic package body 7, so that the second plastic package body 7 is wrapped on the surface of the first plastic package body 5. And (5) performing plastic packaging again to form a second plastic packaging body 7, and packaging the chip outgoing lines 11 to form an interconnection structure, the chip 6, the metal base island 3 and the first plastic packaging body 5.
Step T9., the carrier 1 and the peelable layer 2 are gradually removed from bottom to top, so that the metal islands 3 and the bottom of the metal lead layer 10 are exposed. The carrier 1 and the peelable layer 2 below the metal base island 3 are removed by physical grinding or chemical biting of liquid medicine, and the temporary barrier layer 4 is removed by chemical liquid medicine or laser, so that the bottom surfaces of the metal base island 3, the bottom surface of the metal lead layer 10 and the bottom surface of the first plastic package body 5 are exposed, and the bottom surfaces of the metal base island 3, the metal lead layer 10 and the first plastic package body are flush.
Step t10. A metal protective layer 8 is formed on the bottom surface of both the metal islands 3 and the metal lead layer 10, as shown in fig. 7. The metal protection layer 8 is not formed on the surface of the first plastic package body 5 by electroplating, so that the metal protection layer 8 is used as a part of the metal base island 3 and the metal lead layer 10, and the bottom of the metal protection layer is lower than the bottom of the first plastic package body 5.
Step T11 the metal protective layer 8 on the surface of the metal lead layer 10 is removed by pattern etching, so that the bottom of the metal base island 3 (including the metal protective layer 8) is highlighted, as shown in FIG. 7. This step may or may not be performed.
Finally, dicing is performed to form individual devices 9.
Examples
A processing structure of a microminiature package comprises a carrier 1 and a peelable layer 2 from bottom to top. At least two metal base islands 3 are arranged on the surface of the peelable layer 2, temporary barrier layers 4 are arranged between the metal base islands 3 at the bottom positions of the metal base islands 3, the temporary barrier layers 4 and the metal base islands 3 are of complementary structures, and the overlapped areas of the temporary barrier layers 4 and the metal base islands 3 cover the surface of the whole peelable layer 2. The surfaces of the metal base island 3 and the temporary barrier layer 4 are wrapped by a first plastic package body 5, and a certain thickness exists in the first plastic package body 5 above the metal base island 3. All the metal islands 3 are attached with metal solder, the chips 6 are installed through the metal solder, the chip outgoing lines 11 upwards bypass the surface of the first plastic package body 5 and then downwards connect the chips 6 on the other metal islands 3, at least two chips 6 are connected, and the chip outgoing lines 11 form an interconnection structure on the surface of the first plastic package body 5. The second plastic package body 7 is attached to the surface of the chip outgoing line 11, and the second plastic package body 7 wraps all parts on the carrier 1, so that structural reinforcement is realized.
A processing method of a microminiature package comprises
Step p1. Providing a carrier 1. The carrier 1 is made of a harder material, and since the encapsulated devices 9 are formed by processing a plurality of devices 9 on one carrier 1, and finally the individual devices 9 are formed by cutting, the carrier 1 is sized to carry the encapsulated devices 9 to be processed at the same time.
Step P2. A layer of peelable layer 2 is attached to the surface of the carrier 1. The peelable layer 2 is made of a metal material, and the double-layer metal of the peelable layer 2 is arranged on the surface of the carrier 1 by means of coating, electroplating and the like, so that the peelable layer 2 covers all areas of the surface of the carrier 1.
Step p3. Forming a temporary barrier layer 4 on the surface of the peelable layer 2. The temporary barrier layer 4 is galvanically formed or etched to form the peelable layer 2 by means of electroplating or etching.
Step p4. Processing the surface of the peelable layer 2 to form a plurality of metal islands 3. The metal islands 3 are formed by electroplating in the remaining areas of the peelable layer 2, the upper surfaces of the metal islands 3 being higher than the upper surfaces of the temporary barrier layers 4. During processing, the temporary barrier layer 4 prevents plating accumulation on the temporary barrier layer 4 by the plating resist.
Step P5. mounts the chip 6 on the metal island 3. The metal base islands 3 are electroplated to form a metal solder layer, and then the chips 6 are mounted on the surfaces of the metal solder layer through welding or ultrasonic heating friction technology, so that the chips 6 are mounted on the metal base islands 3, and the chips 6 are attached to the surfaces of the metal base islands 3. The mounted chips 6 may be relatively independent, as shown in fig. 8, or may be a group of two metal islands 3, where two metal islands 3 are mounted with a chip 6 having two bonding pads, as shown in fig. 9, and the chip 6 needs to be flip-chip bonded, so that the bonding pads face the metal islands 3.
And step P6, processing the first plastic package body 5, and wrapping the first plastic package body 5 on the surface of the carrier 1. At this time, the first plastic package body 5 is coated with the metal base island 3, the temporary barrier layer 4 and the chip 6, and the bottom surface of the first plastic package body 5 is higher than the bottom surface of the metal base island 3 due to the existence of the temporary barrier layer 4.
And step P7, processing the first plastic package body 5 to expose the surface of the chip 6, and connecting the chip 6 and the chip 6 through the outgoing line. And laser perforation is carried out, communicated holes are formed above the chip 6, and then the chip outgoing lines 11 are connected with the other chip 6 in the modes of hole metallization, electroplating, conductive adhesive filling and the like. After the opening, the front electrode is exposed to the individual chip 6, and the back electrode is exposed to the chip 6 having two pads.
And step P8, processing to form a second plastic package body 7, and wrapping the second plastic package body 7 on the surface of the first plastic package body 5. And (5) performing plastic packaging again to form a second plastic packaging body 7, and packaging the chip outgoing lines 11 to form an interconnection structure, the chip 6, the metal base island 3 and the first plastic packaging body 5.
Step P9, removing the carrier 1, the peelable layer 2 and the temporary barrier layer 4 gradually from bottom to top to expose the bottom and the side surfaces of the metal base island 3. The carrier 1 and the peelable layer 2 below the metal base island 3 are removed by physical grinding or chemical biting of liquid medicine, and the temporary barrier layer 4 is removed by chemical liquid medicine or laser, so that the bottom surface and the side surface of the metal base island 3 and the bottom surface of the first plastic package body 5 are exposed.
Step p10. Forming a metal protection layer 8 on the side and bottom surfaces of the metal islands 3.
Finally, dicing is performed to form individual devices 9.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (10)

1. The processing structure of the microminiature package is characterized by comprising a metal base island, wherein a chip is arranged on part or part of the metal base island, a plastic package body wraps the surfaces of the metal base island and the chip, a removable substrate structure is arranged at the bottom of the metal base island, a temporary barrier layer or a metal lead layer is arranged at the periphery of the bottom of the metal base island, and the bottom of the metal base island is lower than the bottom of the plastic package body.
2. The processing structure of a micro-miniature package of claim 1, wherein the plastic package body comprises a first plastic package body and a second plastic package body from bottom to top, the first plastic package body is attached to the base structure and wraps the metal base island and the chip, and the second plastic package body wraps the first plastic package body and the connection structure between the chip and the metal base island.
3. The micro-miniature package processing structure of claim 1, wherein the occupied area of the metal base island and the occupied area of the temporary barrier layer cover the surface of the base structure, and the occupied area of the metal base island and the occupied area of the temporary barrier layer are complementary structures.
4. The processing structure of a miniature package according to claim 1, wherein the bottom of the metal islands is connected to a metal lead layer, and each of the metal lead layers is connected to two adjacent metal islands that are not connected to each other.
5. A processing method of microminiature packaging is characterized in that a metal base island is arranged on a strippable substrate structure, a temporary barrier layer or a metal lead layer is arranged on the periphery of the bottom of the metal base island, plastic packaging processing is divided into two operations and is respectively arranged after the steps of mounting the metal base island and a chip and connecting the metal base island and the chip, and finally, the strippable part of the bottom of the metal base island is removed, so that the bottom of the metal base island is lower than the bottom of a plastic package body.
6. The processing method of the microminiature package according to claim 5, wherein the metal islands and the temporary barrier layer are formed on the substrate structure by electroplating, the metal islands and the temporary barrier layer are formed by electroplating step by step, a plating resist is adhered to the surface of the substrate structure, the areas where the metal islands or the temporary barrier layer are not arranged are shielded, the areas where the metal islands to be electroplated are located or the areas where the temporary barrier layer is located are exposed by exposing and developing methods, and the metal islands or the temporary barrier layer is formed after electroplating.
7. The method of claim 5, wherein the metal islands comprise a first metal island for providing a chip and a second metal island as a lead-out pad for a chip electrode, and wherein a metal solder layer is provided on a surface of the first metal island.
8. The method of claim 5, wherein the first molding body and the second molding body are formed after molding, the first molding body is processed after the mounting process of the metal base island and the chip, and the second molding body is processed after the connecting process of the metal base island and the chip.
9. The method of claim 8, wherein after the first molding step, laser holes are formed above the chip and the chip electrode lead wires are arranged to connect the chip to the metal islands as lead-out pads.
10. The method of claim 5, wherein a metal protective layer is formed on the bottom of the metal island after the substrate structure is removed.
CN202310306198.5A 2023-03-21 2023-03-21 Processing structure and processing method of microminiature package Active CN116207057B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310306198.5A CN116207057B (en) 2023-03-21 2023-03-21 Processing structure and processing method of microminiature package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310306198.5A CN116207057B (en) 2023-03-21 2023-03-21 Processing structure and processing method of microminiature package

Publications (2)

Publication Number Publication Date
CN116207057A true CN116207057A (en) 2023-06-02
CN116207057B CN116207057B (en) 2024-02-02

Family

ID=86517319

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310306198.5A Active CN116207057B (en) 2023-03-21 2023-03-21 Processing structure and processing method of microminiature package

Country Status (1)

Country Link
CN (1) CN116207057B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090166824A1 (en) * 2007-12-26 2009-07-02 Byung Tai Do Leadless package system having external contacts
CN106158742A (en) * 2016-08-30 2016-11-23 长电科技（滁州）有限公司 A kind of planar salient point type is without Metal Cutting packaging technology and encapsulating structure thereof
CN110021565A (en) * 2017-12-14 2019-07-16 英飞凌科技股份有限公司 The encapsulated type non-leaded package of at least partly exposed inner sidewall with chip carrier
CN113571434A (en) * 2021-06-07 2021-10-29 华宇华源电子科技（深圳）有限公司 Novel panel-level packaging method and structure
CN113643990A (en) * 2021-06-29 2021-11-12 华宇华源电子科技（深圳）有限公司 Board level packaging method and structure for improving device strength
CN215342591U (en) * 2021-06-07 2021-12-28 华宇华源电子科技（深圳）有限公司 Packaging structure based on prevent static

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090166824A1 (en) * 2007-12-26 2009-07-02 Byung Tai Do Leadless package system having external contacts
CN106158742A (en) * 2016-08-30 2016-11-23 长电科技（滁州）有限公司 A kind of planar salient point type is without Metal Cutting packaging technology and encapsulating structure thereof
CN110021565A (en) * 2017-12-14 2019-07-16 英飞凌科技股份有限公司 The encapsulated type non-leaded package of at least partly exposed inner sidewall with chip carrier
CN113571434A (en) * 2021-06-07 2021-10-29 华宇华源电子科技（深圳）有限公司 Novel panel-level packaging method and structure
CN215342591U (en) * 2021-06-07 2021-12-28 华宇华源电子科技（深圳）有限公司 Packaging structure based on prevent static
CN113643990A (en) * 2021-06-29 2021-11-12 华宇华源电子科技（深圳）有限公司 Board level packaging method and structure for improving device strength

Also Published As

Publication number Publication date
CN116207057B (en) 2024-02-02

Similar Documents

Publication Publication Date Title
KR101168263B1 (en) Semiconductor package and fabrication method thereof
US6740964B2 (en) Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device
US6541848B2 (en) Semiconductor device including stud bumps as external connection terminals
EP1005086B1 (en) Metal foil having bumps, circuit substrate having the metal foil, and semiconductor device having the circuit substrate
EP0072673B1 (en) Area tape for the electrical interconnection between electronic components and external circuitry
US20040136123A1 (en) Circuit devices and method for manufacturing the same
TW200921884A (en) Method for making copper-core layer multi-layer encapsulation substrate
US7264997B2 (en) Semiconductor device including inclined cut surface and manufacturing method thereof
EP1951012B1 (en) Method of manufacturing a wiring board including electroplating
CN213071119U (en) Substrate with through window and device packaging structure
EP0171232B1 (en) Area-bonding tape
JP3437477B2 (en) Wiring board and semiconductor device
JP2005286057A (en) Circuit device and its manufacturing method
CN116207057B (en) Processing structure and processing method of microminiature package
US11869844B2 (en) Semiconductor device
US20040247840A1 (en) Electronic elements, method for manufacturing electronic elements, circuit substrates, method for manufacturing circuit substrates, electronic devices and method for manufacturing electronic devices
US6444494B1 (en) Process of packaging a semiconductor device with reinforced film substrate
TWI351749B (en) Packaging substrate and method for menufacturing t
US7160796B2 (en) Method for manufacturing wiring board and semiconductor device
KR20010033602A (en) Semiconductor device and method of production thereof and semiconductor mounting structure and method
US20010022391A1 (en) Substrate for semiconductor device and semiconductor device fabrication using the same
US9570372B1 (en) Thermally enhanced semiconductor assembly with heat spreader and integrated dual build-up circuitries and method of making the same
JP2000216185A (en) Semiconductor wafer fitted with columnar electrode and its manufacture, and semiconductor device and its manufacture
KR101231163B1 (en) Manufacturing method of circuit module
JP7382170B2 (en) semiconductor equipment

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant