CN106409689A - High-density circuit chip packaging process - Google Patents
High-density circuit chip packaging process Download PDFInfo
- Publication number
- CN106409689A CN106409689A CN201610871160.2A CN201610871160A CN106409689A CN 106409689 A CN106409689 A CN 106409689A CN 201610871160 A CN201610871160 A CN 201610871160A CN 106409689 A CN106409689 A CN 106409689A
- Authority
- CN
- China
- Prior art keywords
- circuit
- outer pin
- electrodeposited coating
- copper base
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012858 packaging process Methods 0.000 title abstract 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052802 copper Inorganic materials 0.000 claims abstract description 50
- 239000010949 copper Substances 0.000 claims abstract description 50
- 239000013078 crystal Substances 0.000 claims abstract description 22
- 238000007747 plating Methods 0.000 claims abstract description 21
- 238000003466 welding Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004806 packaging method and process Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims description 38
- 238000000576 coating method Methods 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 12
- 239000010410 layer Substances 0.000 claims description 11
- 239000003292 glue Substances 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 5
- 238000004026 adhesive bonding Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000001746 injection moulding Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004568 cement Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000004513 sizing Methods 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/858—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A high-density circuit chip packaging process relates to the technical field of semiconductor packaging processes, and comprises the following steps: electroplating: electroplating on the front surface of the copper substrate according to the circuit pattern of the chip to form an electroplated layer, wherein the electroplated layer is used as the circuit, and the electroplated layer of the outer pin is electroplated on the back surface of the copper substrate according to the pattern of the outer pin; crystal bonding and electrifying: bonding the crystal grains and welding wires between the crystal grains and welding positions of the circuit to realize electric connection; plastic packaging: forming a plastic protection layer on the front surface of the copper substrate by injection molding; manufacturing an outer leg: the copper substrate is etched from the back surface thereof, and the portions of the copper substrate not covered with the outer leg plating layer are etched away, and the portions of the copper substrate not covered with the outer leg plating layer and the outer leg plating layer serve as outer legs.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation.
Background technology
In the existing chip package process with lead frame as substrate, it is the circuit etching chip using copper base, such as
The circuit of fruit chip is simple, density is low, and this kind of technique has no problem.However, for the high chip of complex circuit, density, profit
With copper base come the place's of etching chip circuit the drawbacks of just highlight.If circuit or pin son are too intensive, ensureing size
In the case of increasing not too much, circuit is accomplished by being made very carefully, and the technique etching is limited by copper material thickness bottom and etching factor,
The circuit etching gap of very little cannot be accomplished, which limits the density of the circuit of chip it is impossible to be designed to circuit too intensive,
Can not neatly design chips circuit.
Content of the invention
In view of this, the present invention proposes a kind of high-density line chip package process, and it can make the circuit of chip be designed to
More crypto set, is capable of the circuit of more neatly design chips.
For achieving the above object, the present invention provides technical scheme below.
High-density line chip package process, comprises the following steps：
Plating：Electroplate in copper base front according to the pattern of the circuit of chip and form electrodeposited coating, this electrodeposited coating is as described
Circuit, electroplates in copper-based back according to the pattern of outer pin and forms outer pin electrodeposited coating；
Viscous brilliant energising：Bonding crystal grain and between crystal grain and the welding position of described circuit bonding wire to realize electrically connecting；
Plastic packaging：It is molded in copper base front and form plastic protection layer；
Make outer pin：From copper base back etched copper base, the part not covered by outer pin electrodeposited coating of copper base is lost
Go, the part not being etched being covered by outer pin electrodeposited coating of copper base and outer pin electrodeposited coating are as outer pin.
In the high-density line chip package process of the present invention, by the way of plating, to make the circuit of chip, rather than
Traditional mode etching on copper base, is therefore no longer limited by copper material thickness bottom and etching factor in etch process, due to electricity
The feature of depositing process, can make thinner circuit, therefore the circuit of chip can be made to be designed to more crypto set it is also possible to more neatly
The circuit of design chips, realizes the high-density line of chip.The circuit of chip includes wire, bonding wire welding position and outer pin connection position.
It is preferred that in plating step, according to the pattern in die bonder region and the circuit of chip pattern in copper base just
Face plating formed electrodeposited coating, this plating layer segment as described circuit, partly as wafer base；
In viscous crystalline substance energizing step, by die bonder on wafer base.
It is preferred that before plastic packaging step, further comprising the steps of：
Microetch：Slight etching copper base front, the copper part etching off below described electrodeposited coating edge forms lock glue
Groove.
After forming lock glue groove, when being molded in follow-up plastic packaging step, sizing material can flow in lock glue groove, and solidification forms plastic cement
After protective layer, described electrodeposited coating will be clasped, after injection, plastic cement can preferably be tied with leadframe substrate (i.e. the electrodeposited coating in front)
Close, it is to avoid plastic protection layer occurs and departs from lead frame, plastic protection layer and electrodeposited coating are so securely joined with it is ensured that encapsulating shape
The reliability of the chip becoming.
It is preferred that microetching step is after the electroplating step, before gluing crystalline substance energizing step.Against corrosion using electrodeposited coating itself
Property it is not necessary to pad pasting, exposed and developed protecting electrodeposited coating.Microetching step before bonding crystal grain and bonding wire, with more reality
May and being worth of operation, will not cause to damage to crystal grain and the line being welded.
It is preferred that after making outer step and be rapid, further comprising the steps of：
Make back-protective layer：It is molded in chip back and forms back-protective layer, outer sole end is exposed from back-protective layer.
Brief description
Fig. 1 is the step schematic diagram of the high-density line chip package process of the present invention；
Fig. 2 is the enlarged diagram at A in Fig. 2；
Fig. 3 is the enlarged diagram at B in Fig. 2；
Fig. 4 is the schematic diagram of the part circuit of the chip made using the high-density line chip package process of the present invention.
Reference includes：
Copper base 1, the circuit 2 of chip, wire 21, bonding wire welding position 22, outer pin connection position 23, wafer base 3, lock glue groove 4,
Crystal grain 5, wire 6, plastic protection layer 7, back-protective layer 8, outer pin electrodeposited coating 9, outer pin 10.
Specific embodiment
Below in conjunction with specific embodiment, the present invention is elaborated.
As shown in figure 1, the high-density line chip package process of the present embodiment comprises the steps：
Plating：Form the electrodeposited coating as circuit 2 in copper base 1 front according to the pattern plating of the circuit 2 of chip.Circuit
2 referring to Fig. 4, and circuit 2 includes wire 21 (different from the wire 6 of welding), bonding wire welding position 22 and outer pin connection position 23, bonding wire welding position
22 are used for welding lead 6, and outer pin connection position 23 is used for connecting outer pin 10, it should be noted that being succinctly to illustrate technique mistake in Fig. 1
Journey, to circuit 2 and its not necessarily complete with the expression of the relation of outer pin 10, circuit 2 referring specifically to Fig. 4, outer pin connection position 23
Lower section is fabricated to outer pin 10.Form outer pin electrodeposited coating 9 at copper base 1 back side according to the pattern plating of outer pin 10.In the present embodiment,
In this step, also together can electroplate in copper base 1 front and form wafer base 3, specifically, according to crystal grain 5 bonding region (i.e.
Wafer base 3) pattern and chip circuit 2 pattern copper base 1 front electroplate formed electrodeposited coating, this plating layer segment make
For described circuit 2, partly as wafer base 3.
A in the corresponding Fig. 1 of plating step, concrete operations can be to stick light-sensitive surface on copper base 1 two sides, then expose,
Development, the pattern of the pattern of the circuit 2 on egative film and crystal grain 5 bonding region is transferred on the light-sensitive surface in copper base 1 front, will
The pattern of the outer pin 10 on egative film is transferred on the light-sensitive surface at copper base 1 back side, then carries out plating and forms electrodeposited coating.
The circuit 2 of chip is made by the way of plating, and the mode of unconventional etching on copper base 1, therefore
No longer it is limited by copper material thickness bottom and etching factor in etch process, due to electroplating technology, thinner circuit 2 can be made,
Therefore the design more crypto set and flexibly of the circuit 2 of chip can be made.Referring to Fig. 4, circuit 2, Neng Gourang is made using electroplating technology
The location and shape of wire 21 are more flexible, can easily shuttle in narrow and small gap between outer pin link bit 23, therefore, it is possible to more
Plus the circuit 2 of neatly design chips, realize the high-density line of chip.
It should be noted that formation wafer base 3 also can not be electroplated, to make the position of bonding crystal grain 5 using other modes
Put, for example, paste crystal grain 5 and paste gummed paper using insulation crystal grain, thus can be with designed lines 2 below crystal grain 5, thus realizing
More high density；Or plating forms variously-shaped wafer base 3 at copper base 1 back side, forms wafer base 3 after back of the body erosion.
Made using other modes bonding crystal grain 5 position when, also make accommodation in subsequent process steps, concrete regarding adopts
Depending on which kind of mode is to make the position of bonding crystal grain 5, here is not developed in details in explanation.
Microetch：Slight etching copper base 1 front, by the copper part below described electrodeposited coating (electrodeposited coating in front) edge
Etching off, forms lock glue groove 4.In conjunction with b and Fig. 2 in Fig. 1, by one layer of copper base 1 front etching off, so that as circuit 2 and crystalline substance
Gap in the lower section at the edge of the electrodeposited coating of round bottom seat 3, and this gap is locks glue groove 4.
Viscous brilliant energising：Crystal grain 5 is bonded on wafer base 3, and welding lead between the welding position of crystal grain 5 and circuit 2
6, to realize the electrical connection between crystal grain 5 and circuit 2.As shown in c in Fig. 1.
Plastic packaging：It is molded in copper base 1 front and form plastic protection layer 7.As shown in d in Fig. 1.Sizing material during injection can flow into
Filling lock glue groove 4, forms, after solidification, the structure clasping electrodeposited coating, can clearly see, after injection, plastic cement can be more from Fig. 3
Good is combined with leadframe substrate (i.e. electrodeposited coating), it is to avoid plastic protection layer 7 and departs from lead frame it is ensured that what encapsulation was formed
The reliability of chip.
Make outer pin：From copper base 1 back etched copper base 1, by the portion not covered by outer pin electrodeposited coating 9 of copper base 1
Divide etching off, the part not being etched being covered by outer pin electrodeposited coating 9 of copper base 1 and outer pin electrodeposited coating 9 as outer pin 10.As
In Fig. 1 shown in e.Using the corrosion stability of electrodeposited coating, electroplate at the back side of copper base 1 simultaneously and form outer pin electrodeposited coating 9, after etching
Fall the part not covered by outer pin electrodeposited coating 9 of copper base 1, thus make and form outer pin 10, this is to be different from traditional viscous tin
Another kind of outer pin production method of ball, need not glue tin ball, during manufacturing chip, reduce processing step.
Make back-protective layer：It is molded in chip back and forms back-protective layer 8, outer pin 10 bottom is from back-protective layer 8
In expose.As shown in f in Fig. 1.Due to make outer pin 10 when, copper base 1 by part etching off, as circuit 2 and wafer base 3
Electrodeposited coating be possible to expose (actual conditions might not be as shown in fig. 1), make back-protective layer after, can protect
Circuit 2 and crystal grain 5.
The above disclosed preferred embodiment being only the invention, can not limit present invention wound with this certainly
The interest field made, the equivalent variations therefore made according to the invention claim, still belong to the invention and covered
Scope.
Claims (5)
1. high-density line chip package process, is characterized in that, comprises the following steps：
Plating：According to chip circuit pattern copper base front electroplate formed electrodeposited coating, this electrodeposited coating as described circuit,
Electroplate in copper-based back according to the pattern of outer pin and form outer pin electrodeposited coating；
Viscous brilliant energising：Bonding crystal grain and between crystal grain and the welding position of described circuit bonding wire to realize electrically connecting；
Plastic packaging：It is molded in copper base front and form plastic protection layer；
Make outer pin：From copper base back etched copper base, by the part etching off not covered by outer pin electrodeposited coating of copper base, copper
The part not being etched being covered by outer pin electrodeposited coating of substrate and outer pin electrodeposited coating are as outer pin.
2. high-density line chip package process according to claim 1, is characterized in that,
In plating step, according to the pattern of the pattern in die bonder region and the circuit of chip, in copper base front, plating forms electricity
Coating, this plating layer segment as described circuit, partly as wafer base；
In viscous crystalline substance energizing step, by die bonder on wafer base.
3. high-density line chip package process according to claim 1 and 2, is characterized in that, before plastic packaging step, also
Comprise the following steps：
Microetch：Slight etching copper base front, the copper part etching off below described electrodeposited coating edge forms lock glue groove.
4. high-density line chip package process according to claim 3, is characterized in that, microetching step plating step it
Afterwards, before gluing crystalline substance energizing step.
5. high-density line chip package process according to claim 1, is characterized in that, after making outer step and be rapid,
Further comprising the steps of：
Make back-protective layer：It is molded in chip back and forms back-protective layer, outer sole end is exposed from back-protective layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610871160.2A CN106409689B (en) | 2016-09-30 | 2016-09-30 | High-density circuit chip packaging process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610871160.2A CN106409689B (en) | 2016-09-30 | 2016-09-30 | High-density circuit chip packaging process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106409689A true CN106409689A (en) | 2017-02-15 |
| CN106409689B CN106409689B (en) | 2019-11-01 |
Family
ID=59228042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610871160.2A Active CN106409689B (en) | 2016-09-30 | 2016-09-30 | High-density circuit chip packaging process |
Country Status (1)
| Country | Link |
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| CN (1) | CN106409689B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899308A (en) * | 2018-06-26 | 2018-11-27 | 苏州日月新半导体有限公司 | Semiconductor packaging process and semiconductor package |
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| US7319265B1 (en) * | 2000-10-13 | 2008-01-15 | Bridge Semiconductor Corporation | Semiconductor chip assembly with precision-formed metal pillar |
| US7064012B1 (en) * | 2004-06-11 | 2006-06-20 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a pillar and a routing line using multiple etch steps |
| US20100129964A1 (en) * | 2008-11-26 | 2010-05-27 | Infineon Technologies Ag | Method of manufacturing a semiconductor package with a bump using a carrier |
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| CN108899308A (en) * | 2018-06-26 | 2018-11-27 | 苏州日月新半导体有限公司 | Semiconductor packaging process and semiconductor package |
| CN108899308B (en) * | 2018-06-26 | 2020-07-17 | 苏州日月新半导体有限公司 | Semiconductor packaging process and semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106409689B (en) | 2019-11-01 |
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Effective date of registration: 20220510 Address after: 523000 No. 7, Zhenyuan West Road, Chang'an Town, Dongguan City, Guangdong Province Patentee after: Liance Youte semiconductor (Dongguan) Co.,Ltd. Address before: 523000 Zhen'an science and Technology Industrial Park, Chang'an Town, Dongguan City, Guangdong Province Patentee before: Lewin semiconductor (Dongguan) Co.,Ltd. |