CN105895605A - Thin chip mounted substrate fan-out type packaging structure and manufacturing method therefor - Google Patents

Thin chip mounted substrate fan-out type packaging structure and manufacturing method therefor Download PDF

Info

Publication number
CN105895605A
CN105895605A CN201610408773.2A CN201610408773A CN105895605A CN 105895605 A CN105895605 A CN 105895605A CN 201610408773 A CN201610408773 A CN 201610408773A CN 105895605 A CN105895605 A CN 105895605A
Authority
CN
China
Prior art keywords
substrate
chip
fan
dielectric layer
thin chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610408773.2A
Other languages
Chinese (zh)
Inventor
于大全
项敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Kunshan Electronics Co Ltd
Original Assignee
Huatian Technology Kunshan Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Kunshan Electronics Co Ltd filed Critical Huatian Technology Kunshan Electronics Co Ltd
Priority to CN201610408773.2A priority Critical patent/CN105895605A/en
Publication of CN105895605A publication Critical patent/CN105895605A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/30104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a thin chip mounted substrate fan-out type packaging structure and a manufacturing method therefor. The thin chip mounted substrate fan-out type packaging structure comprises a substrate and at least one chip, wherein the substrate is provided with a first surface and a second surface which are arranged in opposite; the corresponding chip is fixed on the first surface; at least one welding pad is arranged on one side, far from the first surface, of the corresponding chip; a dielectric layer for covering the corresponding chip is paved on the first surface; a window I for exposing the welding pad is formed in a position, corresponding to the welding pad, of the dielectric layer; and at least one metal circuit on the dielectric layer extends through the window I from the welding pad to the substrate. According to the packaging structure provided with the invention, the packaging reliability can be improved, and simple process and low cost are achieved; the substrate has lower warping, so that a smaller wiring linewidth can be obtained, and therefore, the packaging structure is applicable to high-density packaging; in addition, wafer plastic packaging, slotting or hole forming, and a de-bonding process are omitted, so that the cost difficulty is lowered; and therefore, the cost is obviously lowered and the rate of finished products is improved. The invention also discloses the manufacturing method for the thin chip mounted substrate fan-out type packaging structure.

Description

A kind of thin chip attachment substrate fan-out package structure and manufacture method thereof
Technical field
The present invention relates to the encapsulating structure of a kind of FAN-OUT in technical field of semiconductor encapsulation, especially relate to And a kind of thin chip attachment substrate fan-out package structure and manufacture method thereof.
Background technology
In current semicon industry, Electronic Packaging has become as an importance of industry development.Tens The development of the encapsulation technology in year, makes high density, undersized encapsulation requirement become the main flow direction of encapsulation.
Along with electronic product is to pin density thinner, higher, higher, the development of lower cost aspect, govern The major reason that encapsulation technology develops to high density direction is that matrix technique is originally in fine pitch aspect Working ability, it is necessary to by carrier, such as the organic substrate carrier in plastic base array package and pottery carrier band Ceramic monolith in BGA, the amplification to array pitch completes encapsulation process.
Wafer level fan-out structure, it is by the way of reconstruct disk and wafer level connect up again, it is achieved chip fan-out The plastic packaging of structure, finally cuts into single packaging body.But it still suffers from following deficiency: 1, be coated with outside chip Plastic packaging material, plastic packaging material is epoxylite material, its low strength, and the support strength making fan-out structure is inadequate, Thin encapsulation is difficult to apply；2, fan-out structure in packaging technology due to reconstruct wafer thermal coefficient of expansion relatively Silicon chip is much larger, and technical process warpage is relatively big, equipment can working ability relatively low, yield loss is bigger；3, existing Having technique is to meet low thermal coefficient of expansion, and encapsulating resin costly, is unfavorable for the cost degradation of product.
Chinese patent CN 104037133 A discloses a kind of fan-out packaging structure, and this structure is on silicon support plate Fluting, chip upside down is in bottom land, and chip bonding pad electrically guides to silicon support plate surface by circuit；Plastic packaging is used in groove Material is filled, and makes on capsulation material surface and reroutes metal, is electrically derived by circuit.This structure processing procedure is multiple Miscellaneous, relatively costly.
Chinese patent 201520597950.7 use silicon substrate replace the moulding compound substrate as fan-out, fully Utilize the advantage of silicon substrate, it is possible to make forming fine wiring, utilize ripe silicon etching process, can accurately carve The structure such as pit, groove.In technique, it is also possible to cancel disk plastic packaging, tear bonding technology open, reduce technology difficulty, Thus significantly reduce cost, improve yield rate.
Above-mentioned packaging body can solve technique in conventional art to a certain extent, but simultaneously because chip buried Silicon substrate, technique is relative or more complicated, and cost is of a relatively high, and for the relatively thin chip of ratio, enters Row embedment encapsulation can produce certain impact to product reliability, solves to this end, need a kind of chip-packaging structure badly The encapsulation problem of thin chip.
Summary of the invention
For solve above-mentioned technical problem, the present invention provide a kind of thin chip attachment substrate fan-out package structure and Its manufacture method, its solution is due to chip buried base plate, and technique is relatively complicated, and reliability is the highest, and The technical problem that cost is of a relatively high.
The solution of the present invention is: a kind of thin chip attachment substrate fan-out package structure, it include substrate, At least one chip；Substrate has the first surface and second surface being oppositely arranged；Chip is fixed on the first table On face, chip is away from being provided with at least one weld pad on the side of first surface；Covering it is covered with on first surface The dielectric layer of chip, and dielectric layer is provided with the window one of exposed weld pad at corresponding weld pad；On dielectric layer at least A metallic traces is had to be extended to substrate from weld pad by window one.
As the further improvement of such scheme, the thickness of chip is not more than 80 μm.
As the further improvement of such scheme, the material of described substrate be silicon, glass, metal framework extremely Few one.
As the further improvement of such scheme, metallic circuit is formed with pad；Covering it is covered with on dielectric layer The protective layer of metallic circuit, and it is provided with the window two of exposed described pad.
Further, described thin chip attachment substrate fan-out package structure includes at least one conductive structure, Conductive structure on the protection layer and is electrically connected with corresponding pad by window two.
Yet further, during conductive structure is soldered ball, conductive salient point, conductive glue, conductive silver paste at least A kind of.
Further, dielectric layer is identical with the material of protective layer.
Yet further, dielectric layer all has photolithographic characteristics with the material of protective layer.
The present invention also provides for the manufacture method of above-mentioned any thin chip attachment substrate fan-out package structure, including Following steps:
A. a substrate, described substrate is provided to have first surface and the second surface relative with described first surface；
Place at least one on the most described first surface and treat that cartridge chip, described chip contain weld pad one faces up；
It is covered with the dielectric layer covering described chip on the most described first surface, and described dielectric layer is at corresponding weld pad Place is provided with the window one of exposed weld pad；
It is formed with metallic circuit on the most described dielectric layer and described weld pad；
E. being formed with protective layer on described metallic circuit, described protective layer has and exposes for forming conduction The window two of structure；
F. at described window two, form conductive structure.
As the further improvement of such scheme, by the of described substrate before or after described conductive structure is formed Two surfaces carry out thinning, are thinned to described substrate thickness not less than 200 μm.
The invention has the beneficial effects as follows: the present invention provide thin chip attachment substrate fan-out package structure and Manufacture method, uses substrate to replace the moulding compound substrate as fan-out, it is possible to make forming fine wiring；Chip pastes It is contained in substrate surface, protective layer (such as polymer or membrane material) can be passed through and be connected with substrate fixing, prevent Chip offset after thinning, by the first surface being electrically fanned out to substrate of cloth bundle of lines chip again, and by base Plate second surface carries out thinning, advantage of this is that: first, it is possible to increase package reliability, technique letter Single, low cost；Again, due to substrate, there is less warpage, it is possible to obtain less wiring live width, suitable In high-density packages；Finally, the present invention cancels disk plastic packaging, fluting or hole, tears bonding technology open, reduces work Skill difficulty, thus significantly reduce cost, improve yield rate.
Accompanying drawing explanation
Fig. 1 is the generalized section of the first surface pasting chip of substrate of the present invention；
Fig. 2 is that the present invention is coated with dielectric layer on substrate, and is exposed the knot of chip pad by photoetching/etching Structure schematic diagram；
Fig. 3 is that the present invention reroutes on dielectric layer, forms the structural representation that metal reroutes；
Fig. 4 is the structural representation that the present invention forms the first protective layer on metal reroutes；
Fig. 5 is the structural representation that the present invention forms conductive structure on metal reroutes.
Primary symbols illustrates:
1 substrate 101 first surface
102 second surface 2 chips
201 pads 3 cohere glue
4 dielectric layer 5 metal lines
6 protective layer 7 conductive structures
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly Chu, be fully described by, it is clear that described embodiment be only a part of embodiment of the present invention rather than Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creation The every other embodiment obtained under property work premise, broadly falls into the scope of protection of the invention.
Seeing also Fig. 1 to Fig. 5, wherein, Fig. 1 is the first surface pasting chip of substrate of the present invention Generalized section；Fig. 2 is that the present invention is coated with dielectric layer on substrate, and exposes chip by photoetching/etching The structural representation of weld pad；Fig. 3 is that the present invention reroutes on dielectric layer, forms what metal rerouted Structural representation；Fig. 4 is the structural representation that the present invention forms the first protective layer on metal reroutes；Figure 5 is the structural representation that the present invention forms conductive structure on metal reroutes.
The thin chip attachment substrate fan-out package structure of the present invention includes a substrate 1, at least one chip 2 (in the present embodiment as a example by 1), as shown in Figure 5.The material of substrate 1 can be silicon or other support plate, Preferably, the material of substrate 1 is Silicon Wafer or hard support plate.Substrate 1 have first surface 101 and and its Relative second surface 102, described first surface 101 is placed the chip 2 that at least one weld pad faces outwardly. Therefore, chip 2 is fixed on first surface 101, and chip 2 is provided with on the side away from first surface 101 At least one weld pad 201.
It is covered with the dielectric layer 4 covering chip 2 on first surface 101, and dielectric layer 4 is at corresponding weld pad 201 Place is provided with the window 1 of exposed weld pad 201.On dielectric layer 4, at least a metallic traces 5 passes through window Mouth 1 extends to substrate 1 from weld pad 201.Therefore, the first surface 101 of substrate 1, chip 2 Side and end face form one layer of dielectric layer 4, dielectric layer 4 is formed at least one of which metal and reroutes (i.e. gold Belong to circuit 5), described metal reroutes and is connected with the weld pad 201 of chip 2.The weight cloth wiring of described metal Material can be copper or aluminum.Described metal reroutes and is formed with pad, and described metal reroutes and lays exposure The protective layer 6 of described pad, therefore on dielectric layer 4, it is covered with the protective layer 6 covering metallic circuit 5, and it is provided with naked Reveal the window 2 601 of described pad.At least one conductive structure 7, conductive structure 7 it is formed with on described pad It is electrically connected with corresponding pad on protective layer 6 and by window 2 601.Conductive structure 7 can be soldered ball In (such as solder ball), conductive salient point (such as copper post solder bump), conductive glue, conductive silver paste at least A kind of.
The thickness of functional chip 2 is not more than 80 μm.It is provided with one layer between bottom surface and the substrate 1 of chip 2 to glue Attached layer, adhesion layer can be to cohere glue 3, and chip 2 can be fixed on first surface 101 by cohering glue 3. Cohere glue 3 and be preferably non-conductive polymer glue or thin film, adhering chip 2 and first surface 101 so that core Sheet 2 position does not offsets, in order to obtain preferable alignment precision, it is thus achieved that thinner connects up lines again. Polymer latex can be prepared by coating method, and thin film can be prepared by press mold mode.
Dielectric layer 4 can be identical with the material of protective layer 5, as being all same polymer, to improve encapsulation The reliability of body.The material of dielectric layer 4 can be polymer latex, with fixed chip 2, ensures medium simultaneously Energy.Conductive structure can arrange for 7 times formed pad metal level, metal level can be Ni/Au, CrW/Cu, One in Ti/W/Cu/Ni/Au, Ti/Cu, it is illustrated that be not drawn into.
The manufacture method of described thin chip attachment substrate fan-out package structure, implements as follows:
A. providing a substrate 1, the present embodiment is silicon substrate disk, and described silicon substrate disk has first surface 101 and second surface 102 corresponding thereto；
B. the first surface 101 at described silicon substrate places at least one chip to be packaged 2, makes described core The pad face (there is the side of weld pad 201) of sheet 2 upward, as shown in Figure 1；
C., on the pad face of described chip 2 and on the first surface 101 of described silicon substrate, one is formed Layer dielectric layer 4；
D. the dielectric layer 4 above the pad of described chip 2 is opened, as in figure 2 it is shown, and at dielectric layer 4 Make the metal line (i.e. metallic circuit 5) of the weld pad 201 connecting chip 2 above, as shown in Figure 3；
E. on described metal line, make layer protective layer 6, this metal line reserves conduction knot Protective layer 6, as shown in Figure 4, the conduction needed for preparing on the metal line exposed are opened in the position of structure 7 Metal level under structure 7, then carries out the salient point preparation of conductive structure 7 or plants soldered ball, finally cutting into slices, shape Become thin chip attachment silicon substrate fan-out package structure, as shown in Figure 5.
It is also preferred that the left coating process uses polymer latex in step C, protective layer 6 and dielectric layer 4 in step E For same polymer latex, to improve the reliability of packaging body.
Preferably, before and after salient point preparation or planting soldered ball, the second surface 102 of silicon substrate disk is thinned to Desired thickness.
Preferably, before step B, by chip Wafer Thinning to be packaged to setting thickness, then at chip The non-pad face brush of disk coheres glue, forms single chips after scribing, will be with cohering glue by pick tool Chip be positioned over the first surface 101 of described silicon substrate.
Preferably, described dielectric layer 4 be can photoetching material, protective layer 6 is can photoetching material.To use Lithographic process forms opening, exposes the pad of chip, makes metal line connect pad.
The present invention provides a kind of thin chip attachment substrate fan-out package structure and manufacture method thereof, uses substrate Replace the moulding compound substrate as fan-out, it is possible to make forming fine wiring.Chip attachment, at substrate surface, is passed through Cohere glue and cohere fixing with substrate, and prevent chip offset, by connecting up again at chip circumference formation dielectric layer Part I/O soldered ball chip is fanned out to the surface of substrate, it is possible to increase package reliability, and technique is simple, Low cost.Owing to substrate has less warpage, it is possible to obtain less wiring live width, be suitable to high density envelope Dress.In technique, the present invention can cancel disk plastic packaging, tears bonding technology open, reduces technology difficulty, thus aobvious Write and reduce cost, improve yield rate.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.

Claims (10)

1. a thin chip attachment substrate fan-out package structure, it includes substrate (1), at least one core Sheet (2)；Substrate (1) has the first surface (101) and second surface (102) being oppositely arranged；Its It is characterised by: chip (2) is fixed on first surface (101), and chip (2) is away from first surface (101) Side on be provided with at least one weld pad (201)；Covering chip (2) it is covered with on first surface (101) Dielectric layer (4), and dielectric layer (4) is provided with exposed weld pad (201) at corresponding weld pad (201) place Window one (202)；On dielectric layer (4), at least a metallic traces (5) passes through window one (202) Extend to substrate (1) from weld pad (201).
Thin chip attachment substrate fan-out package structure the most as claimed in claim 1, it is characterised in that: core The thickness of sheet (2) is not more than 80 μm.
Thin chip attachment substrate fan-out package structure the most as claimed in claim 1, it is characterised in that: institute State the material of substrate be silicon, glass, metal framework at least one.
Thin chip attachment substrate fan-out package structure the most as claimed in claim 1, it is characterised in that: gold Belong to and be formed with pad on circuit (5)；The protective layer (6) covering metallic circuit (5) it is covered with on dielectric layer (4), And it is provided with the window two (601) of exposed described pad.
Thin chip attachment substrate fan-out package structure the most as claimed in claim 4, it is characterised in that: institute State thin chip attachment substrate fan-out package structure and include at least one conductive structure (7), conductive structure (7) Above and it is electrically connected with by window two (601) and corresponding pad at protective layer (6).
Thin chip attachment substrate fan-out package structure the most as claimed in claim 5, it is characterised in that: lead Electricity structure (7) is at least one in soldered ball, conductive salient point, conductive glue, conductive silver paste.
Thin chip attachment substrate fan-out package structure the most as claimed in claim 4, it is characterised in that: it is situated between Matter layer (4) is identical with the material of protective layer (6).
Thin chip attachment substrate fan-out package structure the most as claimed in claim 7, it is characterised in that: it is situated between Matter layer (4) all has photolithographic characteristics with the material of protective layer (6).
9. a thin chip attachment substrate fan-out package as claimed in any of claims 1 to 8 in one of claims knot The manufacture method of structure, it is characterised in that: comprise the steps:
A. a substrate, described substrate is provided to have first surface and the second surface relative with described first surface；
Place at least one on the most described first surface and treat that cartridge chip, described chip contain weld pad one faces up；
It is covered with the dielectric layer covering described chip on the most described first surface, and described dielectric layer is at corresponding weld pad Place is provided with the window one of exposed weld pad；
It is formed with metallic circuit on the most described dielectric layer and described weld pad；
E. being formed with protective layer on described metallic circuit, described protective layer has and exposes for forming conduction The window two of structure；
F. at described window two, form conductive structure.
The manufacture method of thin chip attachment substrate fan-out package structure the most as claimed in claim 9, its It is characterised by: before or after described conductive structure is formed, the second surface of described substrate is carried out thinning, thinning To described substrate thickness not less than 200 μm.
CN201610408773.2A 2016-06-12 2016-06-12 Thin chip mounted substrate fan-out type packaging structure and manufacturing method therefor Pending CN105895605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610408773.2A CN105895605A (en) 2016-06-12 2016-06-12 Thin chip mounted substrate fan-out type packaging structure and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610408773.2A CN105895605A (en) 2016-06-12 2016-06-12 Thin chip mounted substrate fan-out type packaging structure and manufacturing method therefor

Publications (1)

Publication Number Publication Date
CN105895605A true CN105895605A (en) 2016-08-24

Family

ID=56729260

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610408773.2A Pending CN105895605A (en) 2016-06-12 2016-06-12 Thin chip mounted substrate fan-out type packaging structure and manufacturing method therefor

Country Status (1)

Country Link
CN (1) CN105895605A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106505073A (en) * 2016-09-23 2017-03-15 江西盛泰光学有限公司 A kind of wafer scale glass top chip encapsulating structure
CN109003973A (en) * 2018-09-19 2018-12-14 华天科技（西安）有限公司 A kind of double cushion block photosensor package structures and its packaging method
CN112820706A (en) * 2020-12-30 2021-05-18 南通通富微电子有限公司 Fan-out type packaging structure and packaging method
CN112820653A (en) * 2020-12-30 2021-05-18 南通通富微电子有限公司 Fan-out type packaging method
CN114141726A (en) * 2021-12-01 2022-03-04 甬矽电子(宁波)股份有限公司 Fan-out type packaging method and fan-out type packaging structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1521818A (en) * 2003-01-30 2004-08-18 矽品精密工业股份有限公司 Semiconductor chip package and process of operation
CN101567322A (en) * 2008-04-21 2009-10-28 南茂科技股份有限公司 Encapsulating structure and encapsulating method of chip
CN104681456A (en) * 2015-01-27 2015-06-03 华进半导体封装先导技术研发中心有限公司 Fan-out-type wafer level package method
CN105244341A (en) * 2015-09-01 2016-01-13 华进半导体封装先导技术研发中心有限公司 Semiconductor device FOWLP packaging structure and manufacturing method thereof
CN105448752A (en) * 2015-12-01 2016-03-30 华天科技（昆山）电子有限公司 Fan-out package method of embedded silicon substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1521818A (en) * 2003-01-30 2004-08-18 矽品精密工业股份有限公司 Semiconductor chip package and process of operation
CN101567322A (en) * 2008-04-21 2009-10-28 南茂科技股份有限公司 Encapsulating structure and encapsulating method of chip
CN104681456A (en) * 2015-01-27 2015-06-03 华进半导体封装先导技术研发中心有限公司 Fan-out-type wafer level package method
CN105244341A (en) * 2015-09-01 2016-01-13 华进半导体封装先导技术研发中心有限公司 Semiconductor device FOWLP packaging structure and manufacturing method thereof
CN105448752A (en) * 2015-12-01 2016-03-30 华天科技（昆山）电子有限公司 Fan-out package method of embedded silicon substrate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106505073A (en) * 2016-09-23 2017-03-15 江西盛泰光学有限公司 A kind of wafer scale glass top chip encapsulating structure
CN109003973A (en) * 2018-09-19 2018-12-14 华天科技（西安）有限公司 A kind of double cushion block photosensor package structures and its packaging method
CN109003973B (en) * 2018-09-19 2023-11-28 华天科技（西安）有限公司 Double-cushion block photoelectric sensor packaging structure and packaging method thereof
CN112820706A (en) * 2020-12-30 2021-05-18 南通通富微电子有限公司 Fan-out type packaging structure and packaging method
CN112820653A (en) * 2020-12-30 2021-05-18 南通通富微电子有限公司 Fan-out type packaging method
CN114141726A (en) * 2021-12-01 2022-03-04 甬矽电子(宁波)股份有限公司 Fan-out type packaging method and fan-out type packaging structure

Similar Documents

Publication Publication Date Title
US10559525B2 (en) Embedded silicon substrate fan-out type 3D packaging structure
US20210050226A1 (en) Method of manufacturing semiconductor devices and corresponding semiconductor device
CN107123605A (en) Semiconductor package part and its technique of doing over again
CN105895605A (en) Thin chip mounted substrate fan-out type packaging structure and manufacturing method therefor
US20190259629A1 (en) Method of manufacturing semiconductor devices and corresponding semiconductor device
CN105023900A (en) Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof
TW200915525A (en) Packaged integrated circuit devices with through-body conductive vias, and methods of making same
CN104051383B (en) The semiconductor devices of encapsulation, the method and PoP device for encapsulating semiconductor devices
JP3622435B2 (en) Semiconductor device and manufacturing method thereof
CN106129023A (en) The fan-out packaging structure of two-sided attachment and method for packing
CN105448752A (en) Fan-out package method of embedded silicon substrate
TWI233188B (en) Quad flat no-lead package structure and manufacturing method thereof
CN105845643A (en) Packaging structure for chip embedded into silicon substrate and manufacturing method of packaging structure
JP2003347352A (en) Method for bonding ic chip by non-conductive adhesive to substrate and assembly formed by the method
CN105845585A (en) Chip packaging method and chip packaging structure
CN205984951U (en) Fan -out packaging structure of two -sided subsides dress
CN205488088U (en) Bury silicon substrate fan -out type 3D packaging structure
CN102751204A (en) Fanout type wafer level chip packaging method
JP2000040676A (en) Manufacture of semiconductor device
US20120061834A1 (en) Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof
JP4825529B2 (en) Semiconductor device
US7727861B2 (en) Method and device for contacting semiconductor chips
KR20000061035A (en) Semiconductor chip, method for manufacturing the semiconductor chip, stacked chip package using the semiconductor chip and method for manufacturing the stacked chip package
CN204885147U (en) Bury silicon substrate fan -out type packaging structure
CN107919333A (en) Three-dimensional POP packaging structure and packaging method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20160824

RJ01 Rejection of invention patent application after publication