CN106158760A - 指纹感测器及其制造方法 - Google Patents
指纹感测器及其制造方法 Download PDFInfo
- Publication number
- CN106158760A CN106158760A CN201610313065.0A CN201610313065A CN106158760A CN 106158760 A CN106158760 A CN 106158760A CN 201610313065 A CN201610313065 A CN 201610313065A CN 106158760 A CN106158760 A CN 106158760A
- Authority
- CN
- China
- Prior art keywords
- substrate
- nude film
- fingerprint sensing
- semiconductor die
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title abstract description 165
- 238000004519 manufacturing process Methods 0.000 title abstract description 30
- 239000004065 semiconductor Substances 0.000 claims description 208
- 239000000758 substrate Substances 0.000 claims description 188
- 239000000463 material Substances 0.000 claims description 109
- 230000001681 protective effect Effects 0.000 claims description 94
- 239000012790 adhesive layer Substances 0.000 claims description 47
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 11
- 208000031481 Pathologic Constriction Diseases 0.000 claims description 9
- 210000001215 vagina Anatomy 0.000 claims description 9
- 239000002344 surface layer Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 109
- 239000010408 film Substances 0.000 description 62
- 238000005538 encapsulation Methods 0.000 description 43
- 230000008569 process Effects 0.000 description 26
- 230000002093 peripheral effect Effects 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- 229910052802 copper Inorganic materials 0.000 description 17
- 239000010949 copper Substances 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 17
- 210000000887 face Anatomy 0.000 description 16
- 238000000429 assembly Methods 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 229920000642 polymer Polymers 0.000 description 12
- 239000003822 epoxy resin Substances 0.000 description 11
- 229920000647 polyepoxide Polymers 0.000 description 11
- 238000010168 coupling process Methods 0.000 description 10
- 230000008878 coupling Effects 0.000 description 9
- 238000005859 coupling reaction Methods 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 8
- 230000008859 change Effects 0.000 description 8
- 239000013078 crystal Substances 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- 239000003292 glue Substances 0.000 description 8
- 238000007747 plating Methods 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 238000009434 installation Methods 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 238000011049 filling Methods 0.000 description 6
- -1 juggles Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000000945 filler Substances 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 239000011469 building brick Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 239000012071 phase Substances 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000003344 environmental pollutant Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 231100000719 pollutant Toxicity 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002679 ablation Methods 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000001427 coherent effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007749 high velocity oxygen fuel spraying Methods 0.000 description 2
- 238000007731 hot pressing Methods 0.000 description 2
- 230000003116 impacting effect Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- 229920002635 polyurethane Polymers 0.000 description 2
- 239000004814 polyurethane Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000005336 safety glass Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 238000007751 thermal spraying Methods 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 241001074085 Scophthalmus aquosus Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020830 Sn-Bi Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910020994 Sn-Zn Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910018731 Sn—Au Inorganic materials 0.000 description 1
- 229910018728 Sn—Bi Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 229910009069 Sn—Zn Inorganic materials 0.000 description 1
- 229910009071 Sn—Zn—Bi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 210000004204 blood vessel Anatomy 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001548 drop coating Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000005370 electroosmosis Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002576 ketones Chemical class 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000007645 offset printing Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229950000845 politef Drugs 0.000 description 1
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 210000001525 retina Anatomy 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000002352 surface water Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14678—Contact-type imagers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1329—Protecting the fingerprint sensor against damage caused by the finger
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
- H01L2224/03464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05671—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05684—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
- H01L2224/1132—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13013—Shape in top view being rectangular or square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/13294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/27312—Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/2732—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/276—Manufacturing methods by patterning a pre-deposited material
- H01L2224/2762—Manufacturing methods by patterning a pre-deposited material using masks
- H01L2224/27622—Photolithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/278—Post-treatment of the layer connector
- H01L2224/2783—Reworking, e.g. shaping
- H01L2224/2784—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29006—Layer connector larger than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29007—Layer connector smaller than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/2939—Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/81424—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81439—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81455—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/8146—Iron [Fe] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/81464—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/81466—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/81471—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/81484—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9211—Parallel connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Human Computer Interaction (AREA)
- Multimedia (AREA)
- Theoretical Computer Science (AREA)
- Electromagnetism (AREA)
- Image Input (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
- Measurement Of The Respiration, Hearing Ability, Form, And Blood Characteristics Of Living Organisms (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一种指纹感测器装置和一种制作指纹感测器装置的方法。作为非限制性实例,本发明的各种方面提供各种指纹感测器装置及其制造方法,所述指纹感测器装置包括在裸片的底面上的感测区域,其不具有从顶面感测指纹的顶面电极,和/或所述指纹感测器装置包括直接电连接到板的导电元件的感测器裸片,其中通过所述板感测指纹。
Description
相关申请/以引用的方式并入的申请的交叉引用
本申请引用、主张2015年5月12日在韩国知识产权局递交的且标题为“指纹感测器封装及其制造方法(PACKAGE OF FINGERPRINT SENSOR AND FABRICATING METHODTHEREOF)”的第10-2015-0065900号韩国专利申请的优先权并主张所述韩国专利申请的权益,所述韩国专利申请的内容在此以全文引入的方式并入本文中。
技术领域
本申请涉及一种指纹感测器封装及其制造方法。
背景技术
当前用于形成感测器装置(例如,指纹感测器装置)的半导体封装和方法并不适当,例如,会导致感测准确性和/或装置可靠性不足、装置比需要的更厚、装置难以整合到其它产品和/或整合到其它产品中的成本高、等等。通过比较常规和传统方法与如在本申请的其余部分中参考图式阐述的本发明,所属领域的技术人员将显而易见此类方法的另外的限制和缺点。
发明内容
本发明的各种方面提供一种指纹感测器装置和一种制作指纹感测器装置的方法。作为非限制性实例,本发明的各种方面提供各种指纹感测器装置及其制造方法,所述指纹感测器装置包括在裸片的底面上的感测区域,其不具有从顶面感测指纹的顶面电极,和/或所述指纹感测器装置包括直接电连接到板的导电元件的感测器裸片,其中通过所述板感测指纹。
附图说明
图1示出根据本发明的各种方面的制作感测器装置的实例方法的流程图。
图2A-2E示出说明根据本发明的各种方面的实例感测器装置的横截面图以及制作感测器装置的实例方法。
图3示出根据本发明的各种方面的制作感测器装置的实例方法的流程图。
图4A-4B示出说明根据本发明的各种方面的实例感测器装置的横截面图以及制作感测器装置的实例方法。
图5示出根据本发明的各种方面的制作感测器装置的实例方法的流程图。
图6A-6E示出说明根据本发明的各种方面的实例感测器装置的横截面图以及制作感测器装置的实例方法。
图7示出说明根据本发明的各种方面的实例感测器装置的横截面图以及制作感测器装置的实例方法。
图8示出说明根据本发明的各种方面的实例感测器装置的横截面图以及制作感测器装置的实例方法。
图9示出说明根据本发明的各种方面的实例感测器装置的横截面图以及制作感测器装置的实例方法。
具体实施方式
以下论述通过提供实例来呈现本发明的各种方面。此类实例是非限制性的,并且由此本发明的各种方面的范围应不必受所提供的实例的任何特定特征限制。在以下论述中,短语“例如”和“示例性”是非限制性的且通常与“借助于实例而非限制”“例如且不加限制”等等同义。
如本文中所使用,“和/或”意指通过“和/或”联结的列表中的项目中的任何一个或多个。作为一实例,“x和/或y”意指三元素集合{(x),(y),(x,y)}中的任何元素。换句话说,“x和/或y”意指“x和y中的一个或两个”。作为另一实例,“x、y和/或z”意指七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任何元素。换句话说,“x、y和/或z”意指“x、y和z中的一个或多个”。
本文中所使用的术语仅出于描述特定实例的目的,且并不意图限制本发明。如本文中所使用,除非上下文另外明确指示,否则单数形式也意图包含复数形式。将进一步理解,术语“包括”、“包含”、“具有”等等当在本说明书中使用时,表示所陈述特征、整体、步骤、操作、元件和/或组件的存在,但是不排除一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组的存在或添加。
将理解,虽然术语“第一”、“第二”等可在本文中用于描述各种元件,但这些元件不应受这些术语限制。这些术语仅用于将一个元件与另一元件区分开来。因此,例如,在不脱离本发明的教示内容的情况下,下文论述的第一元件、第一组件或第一部分可被称为第二元件、第二组件或第二部分。类似地,各种空间术语,例如“上部”、“下部”、“侧部”等等,可以用于以相对方式将一个元件与另一元件区分开来。然而,应理解,组件可以不同方式定向,例如,在不脱离本发明的教示内容的情况下,半导体装置可以侧向转动使得其“顶”表面水平地朝向且其“侧”表面垂直地朝向。
在图式中,为了清楚起见可以放大层、区和/或组件的厚度或大小。因此,本发明的范围应不受此类厚度或大小限制。另外,在图式中,类似参考标号可以在整个论述中指代类似元件。
此外,应理解,当元件A被提及为“连接到”或“耦合到”元件B时,元件A可以直接连接到元件B或间接连接到元件B(例如,插入元件C(和/或其它元件)可以定位在元件A与元件B之间)。
应理解,尽管本文中呈现的实例主要涉及指纹感测器及其制造方法,但是本发明的范围不限于此。例如,本发明的各种方面容易适用于其它形式的感测器(例如,血管感测器、温度感测器、湿度感测器、图像感测器、通用生物识别感测器、眼或视网膜感测器、声音感测器、材料检测器等)。
另外,应理解,本文中呈现的实例不限于任何特定类型的指纹感测(例如,光学感测类型、半导体感测类型等)。在涉及半导体感测类型的指纹感测器的实例情境中,本文中呈现的各种实例不限于任何特定类型的此类感测(例如,利用温度和/或压力感测器,利用电容感测器等)。此外,应理解,本文中呈现的实例可以适用于其中同时感测整个指纹的所谓单次感测装置或技术、和/或其中连续地(或依序地)感测(例如,当滑移手指时等)局部经扫描的指纹的所谓连续感测装置或技术。
本发明的各种方面提供一种指纹感测器装置(或封装),在其中第一导电凸块和指纹感测单元(或区域)处于半导体裸片的一个表面上且手指(或其指纹)接近半导体裸片的另一表面上的防护层(例如,防护板、防护涂层等)的配置中,所述指纹感测器装置(或封装)可以基于电容的改变而感测指纹。
本发明的各种方面还提供一种指纹感测器装置(或封装)架构,所述指纹感测器装置(或封装)架构可以例如通过将具有指纹感测单元(或区域)的半导体裸片以倒装晶片配置安装在衬底上(例如,安装到封装衬底、安装到通过其可以感测指纹的板或层等)而简化指纹感测器装置的制造(或建造)过程。
本发明的各种方面另外提供一种指纹感测器装置(或封装)及其制造方法,所述指纹感测器装置(或封装)包含:衬底(例如,长方形的、板形的等),所述衬底具有第一表面和与第一表面相对的第二表面;半导体裸片,所述半导体裸片具有平面的第一裸片表面和与第一裸片表面相对的第二裸片表面,并且包含电连接到衬底的多个第一导电凸块和在第二裸片表面上的指纹感测单元(或区域);在第一裸片表面上的防护板;以及将防护板附着(或保持、或耦合)到衬底的边框。
本发明的各种方面进一步提供一种指纹感测器装置(或封装)及其制造方法,所述指纹感测器装置(或封装)包含:衬底(例如,长方形的、板形的等),所述衬底具有第一表面和与第一表面相对的第二表面;半导体裸片,所述半导体裸片具有平面的第一裸片表面和与第一裸片表面相对的第二裸片表面,并且包含电连接到衬底的多个第一导电凸块和在第二裸片表面上的指纹感测单元(或区域);围绕半导体裸片的侧部的包封材料;以及包覆在半导体裸片的第一表面上的防护层。
本发明的各种方面又进一步提供一种指纹感测器装置(或封装)及其制造方法,所述指纹感测器装置(或封装)包含:衬底,所述衬底具有平面的第一表面和与第一表面相对的第二表面;半导体裸片,所述半导体裸片具有平面的第一裸片表面和与第一裸片表面相对的第二裸片表面,并且包含电连接到衬底的第二表面的多个第一导电凸块和在第二裸片表面上的指纹感测单元(或区域);围绕衬底的第一表面以及半导体裸片的侧部和第一裸片表面的包封材料;以及包覆在衬底的第二表面上(或跨衬底的第二表面包覆)的防护层。
本发明的各种方面提供一种指纹感测器装置(或封装),所述指纹感测器装置(或封装)包含:半导体裸片,所述半导体裸片具有平面的第一裸片表面和与第一裸片表面相对的第二裸片表面并且在第一裸片表面上包含多个第一导电凸块和指纹感测单元(或区域);防护板,所述防护板电连接到第一裸片表面上的多个第一导电凸块并且在防护板上包含多个第二导电凸块;衬底(例如,长方形的、板形的等),所述衬底使第二裸片表面安装在其第一衬底表面上并且使第一衬底表面电连接到多个第二导电凸块;以及将防护板附着到衬底的边框。
本发明的各种方面还提供一种指纹感测器装置(或封装)或其制造方法,所述指纹感测器装置(或封装)包含:衬底,所述衬底具有衬底顶面、衬底底面以及在衬底顶面与衬底底面之间的衬底侧面;半导体裸片,所述半导体裸片具有裸片顶面、裸片底面以及在裸片顶面与裸片底面之间的裸片侧面,其中裸片底面包括感测区域,感测区域包括指纹感测电路;多个第一互连结构,所述多个第一互连结构将裸片底面电连接到衬底顶面;以及在裸片顶面上的防护板,通过所述防护板感测指纹,所述防护板具有板顶面、板底面以及在板顶面与板底面之间的板侧面。
实例指纹感测器装置(或封装)还可以例如包含耦合到衬底顶面并耦合到板的边框。感测区域可以例如在裸片底面的中心区域中,并且多个第一互连结构可以定位在感测区域之外。实例指纹感测器装置可以例如包含粘附到裸片顶面并粘附到板底面的粘合层。粘合层可以例如完全覆盖裸片顶面。实例指纹感测器装置可以例如在裸片顶面上不包含电导体(例如,感测迹线或元件或电极等)。实例指纹感测器装置可以例如包含多个第二互连结构,所述多个第二互连结构耦合到板底面并耦合到半导体裸片的覆盖面积之外的衬底顶面,并且其中防护板包含多个导电迹线,多个导电迹线中的每一个电连接到第二互连结构中的相应一个。防护板可以例如是或包含玻璃。实例指纹感测器装置可以例如包含在裸片顶面与防护板之间的插入件。多个第二互连结构可以例如耦合到插入件的底面并耦合到半导体裸片的覆盖面积之外的衬底顶面,并且插入件可以包括多个导电迹线,多个导电迹线中的每一个电连接到第二互连结构中的相应一个。
本发明的各种方面可以另外提供一种指纹感测器装置(或封装)或其制造方法,所述指纹感测器装置(或封装)包含:衬底,所述衬底具有衬底顶面、衬底底面以及在衬底顶面与衬底底面之间的衬底侧面;半导体裸片,所述半导体裸片具有裸片顶面、裸片底面以及在裸片顶面与裸片底面之间的裸片侧面,其中裸片底面包括感测区域,感测区域包括指纹感测电路;多个第一互连结构,所述多个第一互连结构将裸片底面电连接到衬底顶面;围绕裸片侧面的包封材料;以及在裸片顶面上的防护层,通过所述防护层感测指纹,所述防护层具有防护层顶面、防护层底面以及在防护层顶面与防护层底面之间的防护层侧面。
包封材料可以例如具有与裸片顶面共面的顶面。防护层可以例如包括涂层。防护层可以例如完全覆盖裸片顶面。防护层可以例如覆盖包封材料的顶面的至少一部分。
本发明的各种方面可以进一步提供一种指纹感测器装置(或封装)或其制造方法,所述指纹感测器装置(或封装)包含:衬底,所述衬底具有衬底顶面、衬底底面以及在衬底顶面与衬底底面之间的衬底侧面;板,通过所述板感测指纹,所述板具有板顶面、板底面以及在板顶面与板底面之间的板侧面;半导体裸片,所述半导体裸片具有裸片顶面、裸片底面以及在裸片顶面与裸片底面之间的裸片侧面,其中裸片顶面包含感测区域,感测区域包括指纹感测电路;以及多个第一导电互连结构,所述多个第一导电互连结构将裸片顶面电连接到板底面。
板可以例如包括多个导电迹线,多个导电迹线中的每一个耦合到第一导电互连结构中的相应一个。在实例实施方案中,多个导电迹线可以嵌入板内。实例指纹感测器装置可以例如包含多个第二导电互连结构,所述多个第二导电互连结构中的每一个耦合到板的导电迹线中的相应一个并耦合到衬底顶面。实例指纹感测器装置还可以例如包含将裸片底面粘附到衬底顶面的粘合层。
本发明的以上和其它方面将在各种实例实施方案的以下描述中进行描述并从各种实例实施方案的以下描述中显而易见。现将参考附图呈现本发明的各种方面。
应注意,尽管一般在形成单个指纹感测器装置的情况下呈现本文中提供的实例,但这仅是出于说明的清晰性目的。在实例实施方案中,可以面板或晶片形式形成多个此类装置,其中在过程中的适当时刻执行分离,在分离之后可以在单个装置级别执行额外过程。
图1示出根据本发明的各种方面的制作感测器装置(例如,指纹感测器装置)的实例方法1000的流程图。实例方法1000可以例如与本文中所论述的任何其它方法(例如,图3的实例方法3000、图5的实例方法5000等)共享任何或全部特征。图2A-2E示出说明根据本发明的各种方面的实例感测器装置的横截面图以及制作感测器装置的实例方法。2A-2E中示出的结构可以与图4A-4B、图6A-6E、图7-9等中示出的类似结构共享任何或全部特征。图2A-2E可以例如示出在图1的实例方法1000的各种阶段(或块)的实例感测器装置(例如,指纹感测器装置)。现将一起论述图1和2A-2E。应注意,在不脱离本发明的范围的情况下,可以改变实例方法1000的实例块的顺序,可以省略各种块,和/或可以添加各种块。
一般来说,实例方法1000可以包括提供半导体裸片(块1010)、安装半导体裸片(块1020)、形成粘合层(块1030)、附着防护板(块1040)以及附着边框(块1050)。
实例方法1000可以在块1005处开始执行。实例方法1000可以响应于任何各种原因或条件而开始执行,在此提供所述各种原因或条件的非限制性实例。例如,实例方法1000可以响应于从实例方法1000或另一方法(例如,图3的实例方法3000、图5的实例方法5000、或任何块或其部分等)的另一块接收过程流程而开始执行。又例如,实例方法1000可以响应于方法1000所使用的材料的到达、响应于过程或设备或方法1000所使用的其它资源的可用性等而开始执行。另外,例如,实例方法1000可以响应于用户和/或自动化命令的开始(例如,来自过程控制器、安全系统等)而开始执行。一般来说,实例方法1000可以响应于任何各种原因或条件而开始执行。因此,本发明的范围不受任何特定开始原因或条件的特征限制。
实例方法1000可以在块1010处包括提供半导体裸片。块1010可以包括以任何各种方式提供(例如,接收和/或制备等)半导体裸片,在此提供所述各种方式的非限制性实例。
块1010可以例如包括接收完全制备或部分制备状态的半导体裸片。例如,块1010可以包括接收来自不同地理位置处的建造机构或相关联分销机构的充分制备或部分制备的裸片、来自相同的一般地理位置处的上游制造过程的充分制备或部分制备的裸片等。例如,可以在现场或在与本文中所论述的任何其它处理活动有关的场外执行本文中所论述的任何或全部的半导体裸片制备活动。
半导体裸片可以例如包括第一面(例如,平面的顶面或顶表面等)、第二面(例如,平面的底面或底表面等)以及在第一面与第二面之间的一个或多个外围面(例如,平面的侧面或侧表面等)。半导体裸片可以例如具有50μm到150μm范围内的厚度(例如,第一面与第二面之间的距离)。半导体裸片可以例如具有小于150μm或小于100μm的厚度。如果半导体裸片太厚,此厚度可能会约束感测指纹(例如,通过半导体裸片感测指纹)。因此,在本文中所论述的各种实施方案中,半导体裸片可以制备得足够薄以通过裸片的厚度有效感测指纹。在实例实施方案中,半导体裸片的整个第一面和整个第二面可以是平面的(例如,在其外围边缘处没有阶跃或凹口等)。
半导体裸片的第二面可以例如包括指纹感测单元。指纹感测单元可以例如包括指纹感测电路(例如,迹线、电极、光学元件、电容性感测元件等)和/或指纹处理电路(例如,用以处理或分析从指纹感测电路接收的指纹相关信号的逻辑电路等)。指纹感测单元可以例如通过感测和分析电容(例如,电容的改变或电容模式)、光学图像、温度、压力等来检测指纹。指纹感测单元用以感测指纹特征的部分(例如,在半导体裸片的第二面上)可通常在本文中称为指纹感测区域。在实例实施方案中,指纹感测区域可以位于半导体裸片的中心(或居中)区中。指纹感测区域可以例如是长方形、正方形等。例如从顶视图看,半导体裸片可以类似地例如是正方形、长方形等。
半导体裸片的第二面可以例如包括一个或多个导电互连结构,导电互连结构在本文中还可以称为互连结构。此类导电互连结构可以例如包括导电凸块或导电球(例如,焊料凸块或焊料球等)、金属桩或金属柱(例如,铜桩或铜柱等)等。在实例实施方案中,导电互连结构可以定位在半导体裸片的第二面上在感测单元的感测区域的周界之外(和/或在所述周界周围)。例如,此类互连结构可以围绕任何数目的面上(例如,两个面、四个面、三个面、一个面上等)的感测单元(或感测区域)。另外,导电互连结构可以比半导体裸片上的感测单元的任何部分(例如,电子装置元件、电极、迹线、图案、垫片、焊盘、探针等)更高(例如,来自衬底的第二面)。
块1010可以包括以任何各种方式制备半导体裸片。例如,为了获得半导体裸片的所要薄度(或厚度),块1010可以包括将半导体裸片薄化为所要厚度。例如,块1010可以包括磨削半导体裸片的第一面(例如,半导体裸片的背面或非活动面以实现所要厚度。又例如,块1010可以包括通过利用化学/机械平坦化(CMP)和/或任何其它类型的薄化处理来执行薄化。块1010可以例如包括将半导体裸片薄化为单个裸片或薄化为裸片的晶片(例如在晶片薄化处理中)。以此方式,半导体裸片可以是在薄化之后单一化的(或从晶片切分的)。应注意,在实例实施方案中,薄化还可以出现在块1020处执行裸片安装之后。
块1010可以包括以任何各种方式形成导电互连结构。在其中导电互连结构包括导电凸块或导电球(例如,焊料凸块或焊料球、晶片凸块或晶片球等)的实例情境中,此类球或凸块可以包括锡、银、铅、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Pb-Bi、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi、Sn-Ag-Cu、Sn-Ag-Bi、Sn-Zn、Sn-Zn-Bi、其组合、其等效物等,但是本发明的范围不限于此。块1010可以包括通过球落、颠球、金属电镀、胶合和回焊等形成或附着此类互连结构。例如,块1010可以包括例如在导电垫或凸块下金属结构层(UBM)上落导电球、回焊和冷却。
另外,在其中导电互连结构包括金属桩或金属柱的实例情境中,块1010可以例如包括在互连垫(例如,如在块1010的前一部分形成的)或其它导电层部分上形成此类结构。如本文中所论述,此类互连垫可以例如包括任何各种导电材料(例如,铜、铝、银、金、镍、其合金等)。互连垫可以例如通过裸片或衬底的介电层(例如,顶部介电层)中的孔口暴露。介电层可以例如覆盖互连垫的侧表面和/或互连垫的顶表面的外周界。
块1010可以例如包括跨介电层和/或跨互连垫通过介电层中的孔口暴露的部分形成UBM晶种层。如本文中所论述,UBM晶种层可以例如包括任何各种导电材料(例如,铜、金、银、金属等)。可以任何各种方式(例如,溅镀、无电极电镀、化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、等离子体气相沉积等)形成UBM晶种层。
块1010可以例如包括跨UBM晶种层形成掩模(或模板)以限定在其中形成UBM和/或导电桩(或其它互连结构)的区(或体积)。例如,掩模可以包括光阻(PR)材料或其它材料,其可经图案化以覆盖除在上面形成UBM和/或导电桩的区之外的区。块1010接着可例如包括在通过掩模暴露的UBM晶种层上形成UBM层。如本文中所论述,UBM可以包括任何各种材料(例如,钛、铬、铝、钛/钨、钛/镍、铜、其合金等)。块1010可以包括以任何各种方式(例如,溅镀、无电极电镀、化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、等离子体气相沉积等)在UBM晶种层上形成UBM。
块1010接着可例如包括在UBM上形成导电桩。导电桩(或柱)可以包括任何各种特征。例如,导电桩可以是圆柱形、椭圆柱形、长方形柱形等。导电桩可以包括平坦的上端、凹面的上端或凸面的上端。导电桩可以例如包括本文中关于导体层所论述的任何材料。在实例实施方案中,导电桩可以包括铜(例如,纯铜、具有一些杂质的铜等)、铜合金等。在实例实施方案中,块1010(或实例方法1000的另一块)还可以包括在导电桩上形成焊料盖(或圆顶)。
在形成导电桩之后,块1010可以包括剥离或移除掩模(例如,化学剥离、灰化等)。另外,块1010可以包括(例如,通过化学蚀刻等)移除UBM晶种层的至少一部分(例如,此至少一部分未被导电桩所覆盖)。应注意,在晶种层的蚀刻期间,可以例如蚀刻至少UBM晶种层的侧边缘部分。此类蚀刻可以例如导致导电桩和/或UBM下方的底切。
应注意,尽管本文中呈现的实例通常涉及单个半导体裸片,但是还可以提供任何数目的半导体裸片和/或其它电子组件。
示出块1010的各种方面的实例实施方案200A在图2A处示出。实例实施方案200A(或组合件、子组合件、封装等)包括半导体裸片110,所述半导体裸片具有第一面110a(例如,平面的顶面或顶表面等)、第二面110b(例如,平面的底面或底表面等)以及在第一面110a与第二面110b之间的一个或多个外围面110c(例如,平面的侧面或侧表面等)。半导体裸片110可以例如具有50μm到150μm范围内的厚度(例如,第一面与第二面之间的距离)。半导体裸片110a可以例如具有小于150μm或小于100μm的厚度。在实例实施方案200A中,半导体裸片110的整个第一面110a和整个第二面110b可以是平面的(例如,在其外围边缘处没有阶跃或凹口等)。
实例半导体裸片110的第二面110b包括指纹感测单元112。实例指纹感测单元112包括指纹感测电路(例如,迹线、电极、光学元件、电容性感测元件等)和/或指纹处理电路(例如,用以处理或分析从指纹感测电路接收的指纹相关信号的逻辑电路等)。指纹感测单元112可以例如通过感测电容(例如,电容的改变或电容模式)、光学图像、温度、压力等来检测指纹。指纹感测单元112用以感测指纹特征的部分(例如,在半导体裸片的第二面上)可通常在本文中称为指纹感测区域。在实例实施方案中,指纹感测区域可以位于半导体裸片110的中心(或居中)区中。指纹感测区域可以例如是长方形、正方形等。例如从顶视图看,半导体裸片110可以类似地例如是正方形、长方形等。
实例半导体裸片110的第二面110b包括多个导电互连结构111,此处导电互连结构111还可以称为互连结构111。此类导电互连结构111可以例如包括导电凸块或导电球(例如,焊料凸块或焊料球等)、金属桩或金属柱(例如,铜桩或铜柱等)等。在实例实施方案200A中,导电互连结构111定位在半导体裸片110的第二面110b上在感测单元112(或其感测区域)的周界之外(和/或在所述周界周围)。虽然示出实例互连结构111围绕两个面上的指纹感测单元112(或感测区域),但是可以围绕任何数目的面(例如,四个面、两个面、三个面、一个面等)。实例互连结构111比半导体裸片110上的感测单元112的任何部分(例如,电子装置元件、电极、迹线、图案、垫片、焊盘、探针等)更高(例如,来自衬底110的第二面110b)。
一般来说,块1010可以包括制备半导体裸片。因此,本发明的范围不应受半导体裸片的任何特定类型的特征或制备半导体裸片的任何特定方式的特征限制。
实例方法1000可以在块1020处包括安装半导体裸片。块1020可以包括以任何各种方式安装半导体裸片(和/或其它电子组件),在此提供所述各种方式的非限制性实例。
块1020可以例如包括将半导体裸片安装到包括任何各种特征的衬底。例如,衬底可以包括电路板材料(例如,FR-4玻璃环氧树脂、G-10布纹玻璃和环氧树脂、FR-n(其中n=1至6)、CEM-m(其中m=1至4)、层合材料、层合热固性树脂、包铜层合材料、树脂浸渍B状态布(预浸体)、聚四氟乙烯、其组合、其等效物等)。衬底还可以例如是无芯的。衬底可以包括一层或多层的任何各种介电材料,例如,无机介电材料(例如,Si3N4、SiO2、SiON、SiN、氧化物、氮化物等)和/或有机介电材料(例如,聚合物、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、模塑材料、酚醛树脂、环氧树脂等),但本发明的范围不限于此。衬底可以例如包括硅或任何各种半导体材料。衬底还可以例如包括玻璃(例如,玻璃、蓝宝石玻璃、钢化玻璃等)或金属板(或晶片)。衬底可以包括任何各种配置。例如,衬底可以呈晶片或面板形式。衬底还可以例如呈切分或单一化形式。
衬底可以例如是或仅包括不具有导电路由路径的疏松材料。替代地,例如,衬底可以包括一个或多个导电层、通孔、和或信号分配结构。例如,衬底可以包括从衬底的顶表面到或朝向衬底的底表面延伸至衬底中的导电通孔。又例如,替代延伸直通衬底的导电通孔(或除延伸直通衬底的导电通孔之外),衬底可以包括呈间接路径(例如,呈包括垂直导电路径段或部分和橫向导电路径段或部分的组合的导电路径)在衬底的顶表面与底表面之间延伸的导电路径。
块1020可以例如包括以任何各种方式将半导体裸片(例如,如在块1010处提供的半导体裸片)安装(或附着)到衬底。例如,块1020可以包括利用在块1010处提供(或形成)的导电互连结构将半导体裸片安装(或附着)到衬底。应注意,在其中在块1010处并未提供(或形成)导电互连的实例实施方案中,块1020可以包括在半导体裸片上和/或在衬底上形成此类结构。块1020可以例如包括利用任何各种类型的互连结构(例如,导电球或导电凸块、焊料球或焊料凸块、金属柱或金属桩、铜柱或铜桩、焊料加盖柱或焊料加盖桩、焊胶、导电粘合剂等)将半导体裸片安装到衬底。块1020可以包括利用任何各种接合技术(例如,热压(TC)接合、热压非导电胶(TCNCP)接合、块回焊、粘合附着等)将电子组件安装到衬底。在实例实施方案中,块1020可以包括利用导电凸块将半导体裸片的裸片接合垫(或迹线、焊盘、图案等)电连接到衬底的对应衬底接合垫(或迹线、焊盘、图案等)。此类裸片接合垫可以例如通过半导体裸片上的介电层(或钝化层)中的对应开口(或孔口)暴露。类似地,此类衬底接合垫可以例如通过衬底上的介电层(或钝化层)中的对应开口(或孔口)暴露。
块1020还可以例如包括在安装的半导体裸片与衬底之间形成底部填充胶。底部填充胶可以包括任何各种类型的材料,例如,环氧树脂、热塑性材料、热可固化材料、聚酰亚胺、聚氨酯、聚合材料、填充环氧树脂、填充热塑性材料、填充热可固化材料、填充聚酰亚胺、填充聚氨酯、填充聚合材料、助熔底部填充胶、及其等效物,但是并不限于此。可以任何各种方式(例如,毛细底部填充、液体或胶或预制片材的预涂覆底部填充、模塑底部填充等)形成底部填充胶。此类底部填充胶可以包括任何各种特征(例如,毛细底部填充胶、预涂覆底部填充胶、模塑底部填充胶等)。应注意,在各种实例实施方案中,不在块1030处形成(例如,从不形成、在后续过程步骤形成等)此类底部填充胶。
示出块1020的各种方面的实例实施方案200B在图2B处示出。实例实施方案200B(或组合件、子组合件、封装等)包括如关于块1010和图2A所论述的半导体裸片110。半导体裸片110的底面110b通过导电互连结构111电性且机械地附着到衬底120的顶面120a。具体来说,衬底120的顶面120a具有衬底裸片垫和导电迹线121(或图案、焊盘、垫片等),导电互连结构111连接到所述衬底裸片垫和导电迹线121(或图案、焊盘、垫片等)。实例轨迹121又连接到从衬底120的顶面120a到衬底的底面120b延伸穿过衬底的导电通孔122。此类导电通孔122可以例如用来将指纹感测器装置连接到另一电路。虽然实例实施方案200B示出为在半导体裸片110与衬底120之间没有底部填充胶,但是底部填充胶可以填充此空间。
应注意,尽管本文中提供的实例通常涉及安装单个半导体裸片,但是还可以安装任何数目的裸片和/或其它电子组件。
一般来说,块1020可以包括安装半导体裸片。因此,本发明的范围不应受半导体裸片的任何特定类型的特征或安装半导体裸片的任何特定方式的特征限制。
实例方法1000可以在块1030处包括形成粘合层。块1030可以包括以任何各种方式形成粘合层,在此提供所述各种方式的非限制性实例。
粘合层可以例如具有第一面(例如,平面的顶面等)、第二面(例如,平面的底面等)以及在第一面与第二面之间的外围面(例如,侧面表面等)。粘合层的第二面(例如,下侧面)可以例如直接接触和/或覆盖在块1020处安装的半导体裸片的第一面(例如,上侧面)。粘合层可以例如包括均匀的厚度和/或可以覆盖半导体裸片的整个第一面(例如,顶面)。
在实例实施方案中,粘合层可以是或包括非导电粘合剂(例如,包括一个或多个介电材料),所述非导电粘合剂电隔离半导体裸片的整个第一面,例如,在半导体裸片的第一面与粘附到粘合层的与半导体裸片相反的一面的组件(例如,防护板或防护层等)之间提供非导电路径。粘合层可以例如设定大小为恰好匹配半导体裸片的第一面的区域。另外,粘合层的区域可以小于导电裸片的第一面,例如保留半导体裸片的第一面的一部分不被粘合层覆盖。又例如,粘合层的区域可以大于半导体裸片的第一面。
粘合层可以包括任何各种特征。例如,粘合层可以包括液体或胶、预制粘合片材或薄膜等。
块1030可以包括以任何各种方式形成粘合层。例如,块1030可以包括通过光刻、丝网印刷、滴涂和铺开或压滚、打印、涂刷、浸渍、层合预制片材或薄膜等形成粘合层。
示出块1030的各种方面的实例实施方案200C在图2C处示出。实例实施方案200C(或组合件、子组合件、封装等)包括在半导体裸片110的顶面110a上(例如,直接在顶面110a上等)的粘合层130。实例粘合层130具有均匀的厚度并设定大小为恰好匹配(例如,通常在工程和/或制造准确性内匹配)半导体裸片110的顶面110a的区域。实例粘合层130可以例如包括非导电粘合剂的固体层,例如,在半导体裸片110的顶面110a与粘附到粘合层130的与半导体裸片110相反的一面的组件(例如,防护板或防护层等)之间提供非导电路径。在替代实施方案中,粘合层130可以包括孔口(或开口),通过所述孔口(或开口)可以与另一组件进行导电接触。
一般来说,块1030可以包括形成粘合层。因此,本发明的范围不应受粘合层的任何特定类型的特征或形成粘合层的任何特定方式的特征限制。
实例方法1000可以在块1040处包括附着防护板。块1040可以包括以任何各种方式附着防护板,在此提供所述各种方式的非限制性实例。
防护板(或层)可以包括任何各种特征。防护板可以例如防止半导体裸片受外部力和/或污染物(例如,归因于手指按压、滑动等)影响。防护板可以例如覆盖半导体裸片的至少第一面。在实例实施方案中,防护板可以具有比半导体裸片更大的区域(例如,悬垂于导电裸片之上)。虽然实例防护板可以包括预制材料板(例如,在块1040处的附着之前形成),但是本发明的范围不限于此。例如,可以当在粘合层130上形成防护板的材料时(或在此之后)形成防护板。
防护板可以包括各种材料中的任何一个或多个。例如,防护板可以包括玻璃、蓝宝石、蓝宝石玻璃、钢化玻璃、塑料、聚碳酸酯(PC)、聚酰胺(PI)等中的一个或多个,但是本发明的各方面并不限于此。防护板可以例如包括平面的第一面(例如,顶表面等)、平面的第二面(例如,底表面等)以及在第一面与第二面之间的平面的外围面(例如,侧面等)。防护板的第二面(例如,底面)可以例如粘附到粘合层的第一面(例如,顶面)。
示出块1040的各种方面的实例实施方案200D在图2D处示出。实例实施方案200D(或组合件、子组合件、封装等)包括防护板140,底面140b(或表面)(例如,其一部分)粘附到粘合层130的顶面(或表面)。防护板140的顶面140a(或表面)暴露,例如,用于与被感测的手指接触或至少与被感测的手指极为接近。示出实例防护板140具有的区域大体上大于半导体裸片110和粘合层130的区域,例如悬垂于半导体裸片110和粘合层130的外围边缘之上。
一般来说,块1040可以包括附着防护板。因此,本发明的范围不应受防护板的任何特定类型的特征或附着防护板的任何特定方式的特征限制。
实例方法1000可以在块1050处包括附着边框。块1050可以包括以任何各种方式附着边框,在此提供所述各种方式的非限制性实例。
边框可以例如经配置且经附着以将防护板耦合到衬底和/或保护防护板的外围边缘。例如,边框可以覆盖(例如,在顶面和/或侧面和/或底面处)在块1040处附着到半导体裸片的防护板。在实例实施方案中,边框可以仅接触(或直接覆盖)防护板的第一面(例如,顶面)的外围。边框还可以例如附着到(例如,粘附到等)衬底120的第一面120a。边框可以例如在四个、两个或任何数目个面上围绕防护板、粘合层和半导体裸片。边框可以例如提供对指纹感测器装置的所有组件的覆盖,例如除衬底的周界区外(在各种实例实施方案中,还可以覆盖衬底的周界区)。
示出块1050的各种方面的实例实施方案200E在图2E处示出。实例实施方案200E(或组合件、子组合件、封装等)包括边框150,所述边框包含主体部分151、贴附部分152(例如,在边框150的上端处)以及基底部分153(例如,在边框150的下端处)。实例边框150围绕半导体裸片110、粘合层130和防护板140的侧面。实例边框150保留防护板140的第一面140a(例如,顶面)(或其中心区域)暴露,例如,用于与手指接触或与手指极为接近。基底部分153的底表面附着(例如,粘附等)到衬底120的顶面120a。主体部分151将基底部分153和贴附部分152耦合到彼此。贴附部分150包括朝向半导体裸片110的中心向内延伸的部分。贴附部分152的此部分跨防护板140的顶面140a的外围延伸。贴附部分152的此底面的底面接触防护板140并将防护板140固定到衬底120。
在实例实施方案200E中,在半导体裸片的上侧面110a之上不存在电导体(例如,指纹感测迹线或元件或电极或图案等)。然而,情况并不总是如此,如将在本文中呈现的其它实例实施方案中示出。
一般来说,块1050可以包括附着边框。因此,本发明的范围不应受边框的任何特定类型的特征或附着边框的任何特定方式的特征限制。
实例方法1000可以在块1095处包括必要时继续制造(或处理)。块1095可以包括以任何各种方式继续制造(或处理),在此提供所述各种方式的非限制性实例。
例如,块1095可以包括执行额外的衬底处理功能、将额外电子组件安装到衬底、将装置互连结构附着到衬底、包封、覆盖、一般封装、测试、标记、运送、将指纹感测装置100整合到另一产品中等。又例如,块1095可以包括将实例方法1000的执行流程引导到实例方法1000的任何前一步骤。另外例如,块1095可以包括将实例方法1000的执行流程引导到本文中所揭示的任何其它方法(例如,图3的实例方法3000、图5的实例方法5000、或任何块或任何块的部分,等)。又例如,块1095可以包括将实例方法1000的执行流程引导到本文中未揭示的任何方法或其部分。
一般来说,块1095可以包括继续制造(或处理)。因此,本发明的范围不应受继续制造(或处理)的任何特定方式或类型的特征限制。
如图2E中示出的实例实施方案200E中所示(所述实例实施方案在本文中还可以称为指纹感测器装置100(或封装)),根据图1的实例方法1000制造的实例指纹感测器装置可以在手指(或其指纹)触摸或极为接近于防护板140的顶面140a时基于电容的改变而感测指纹,其在半导体裸片110的顶面110a上,所述半导体裸片在其底面110b上包含多个第一导电凸块111和指纹感测单元112。指纹感测器装置(或封装)100可进一步包含电连接到衬底120的导电图案(例如,在其底面120b和/或顶面120a上)的柔性电路板或其它互连结构(未示出)。柔性电路板可以例如电连接到指纹感测器封装100的一个或多个输入和/或输出垫以及电连接到外部衬底或外部电子装置。由于实例半导体裸片110以倒装晶片配置安装在衬底120上,因此指纹感测器封装100提供相对于其它配置简化的制造过程。
如本文中所陈述,本发明的范围不限于所论述的具体实例方法步骤(或相关联结构)。例如,可以从图1的实例方法1000移除各种块(或其部分)或将各种块(或其部分)添加到图1的实例方法1000,可以重新排列各种块(或其部分),可以修改各种块(或其部分)等。例如,在实例实施方案中,包封材料可用于围绕半导体裸片,防护层可以包覆在半导体裸片的第一面上和/或包覆在包封材料上,可以省略边框,等。在图3和4A-4B中示出此类实例实施方案。
图3示出根据本发明的各种方面的制作感测器装置(例如,指纹感测器装置)的实例方法3000的流程图。实例方法3000可以例如与本文中所论述的任何其它方法(例如,图1的实例方法1000、图5的实例方法5000等)共享任何或全部特征。图4A-4B示出说明根据本发明的各种方面的实例感测器装置的横截面图以及制作感测器装置的实例方法。4A-4B中示出的结构可以与图2A-2E、图6A-6E、图7-9等中示出的类似结构共享任何或全部特征。图4A-4B可以例如示出在图3的实例方法3000的各种阶段(或块)的实例感测器装置(例如,指纹感测器装置)。现将一起论述图3和4A-4B。应注意,在不脱离本发明的范围的情况下,可以改变实例方法3000的实例块(或其部分)的顺序,可以省略或添加各种块(或其部分),和/或可以改变各种块(或其部分)。
一般来说,实例方法3000可以包括提供半导体裸片(块3010)、安装半导体裸片(块3020)、包封(块3025)以及形成防护层(块3040)。
实例方法3000可以在块3005处开始执行。实例方法3000可以出于任何各种原因而开始执行,在此提供所述各种原因的非限制性实例。例如,实例方法3000可以出于本文中关于图1的实例方法1000所论述的任何或全部原因而开始执行。例如,块3005可以与图1的实例方法1000的块1005共享任何或全部特征。
实例方法3000可以在块3010处包括提供半导体裸片。块3010可以包括以任何各种方式提供半导体裸片,在此提供所述各种方式的非限制性实例。块3010可以例如与图1的实例方法1000的块1010共享任何或全部特征。
实例方法3000可以在块3020处包括安装半导体裸片。块3020可以包括以任何各种方式安装半导体裸片,在此提供所述各种方式的非限制性实例。块3020可以例如与图1的实例方法1000的块1020共享任何或全部特征。
实例方法3000可以在块3025处包括包封。块3025可以包括以任何各种方式包封(例如,半导体裸片、衬底等),在此提供所述各种方式的非限制性实例。
块3025可以例如包括形成包封材料,所述包封材料覆盖衬底的至少第一面或表面(例如,顶面或顶表面),在块3020处在所述第一面或表面安装半导体裸片。包封材料可以例如具有第二面或表面(例如,底面或底表面),所述第二面或表面覆盖衬底的整个第一面(例如,尚未被半导体裸片和/或互连结构覆盖的部分),但是也可以仅覆盖衬底的一部分(例如,保留衬底的第一面的外围部分或环形部分暴露)。
包封材料还可以例如覆盖和围绕半导体裸片的至少外围面或外围表面(例如,侧面)。在实例实施方案中,包封材料具有与半导体裸片的第一面或表面(例如,顶面或顶表面)共面的第一面或表面(例如,顶面或顶表面)。然而,在替代实施方案中,包封材料可以覆盖第一面或半导体裸片,或可以高于半导体裸片的第一面且包括暴露半导体裸片的第一面(或其一部分)的孔口。
包封材料可以包括任何各种包封或模塑材料(例如,树脂、聚合物、聚合物复合材料、具有填充剂的聚合物、环氧树脂、具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯、硅酮树脂、其组合、其等效物等)。包封材料可以例如包括聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、酚醛树脂、本文中所论述的任何介电材料等中的任何一个或多个。
块3025可以包括以任何各种方式(压缩模塑、传递模塑、液体包封剂模塑、真空层合、胶印刷、薄膜辅助模塑等)形成包封材料。在实例实施方案中,块3025可以包括利用密封模套或薄膜辅助模塑技术来保持半导体裸片的第一面不含包封材料。在另一实例实施方案中,块3025可以最初形成包封材料以覆盖半导体裸片的第一面,且接着薄化包封材料直到半导体裸片的第一面从包封材料暴露。在再一实例实施方案中,块3025可以最初形成包封材料以覆盖半导体裸片的第一面,且接着薄化包封材料和半导体裸片两者以将包封材料和半导体裸片两者薄化为所要厚度。
如关于实例方法1000的块1020所论述,可以在半导体裸片与衬底之间形成底部填充胶。如同块1020一样,块3020也可以已经形成底部填充胶。在此情况下,包封材料还可以覆盖此类底部填充胶的外围表面(例如,侧表面)。在另一实例实施方案中,块3025可以包括用包封材料底部填充半导体裸片(例如,作为模塑底部填充胶等)。
示出块3025的各种方面的实例实施方案400A在图4A处示出。实例实施方案400A(和实例实施方案400B)的组件可以例如与本文中示出和论述的其它实例实施方案的类似编号的组件共享任何或全部特征,并且因此将不重复此类组件的详细论述。
实例实施方案400A(或组合件、子组合件、封装等)包括覆盖衬底120的第一面120a(例如,顶面等)的至少一部分的包封材料230。实例包封材料230又覆盖在衬底120的第一面120a上或在所述第一面处的导电迹线121(或图案、焊盘、垫片等)。实例包封材料230还覆盖并围绕半导体裸片110的侧面110c。实例包封材料230还填充半导体裸片110的底面110b与衬底120的顶面120a之间的体积(例如,作为底部填充胶)并围绕导电互连结构111。实例包封材料230具有与半导体裸片110a的第一面110a共面的第一面或表面230a(例如,顶面或顶表面)。
一般来说,块3025可以包括包封。因此,本发明的范围不应受包封材料的任何特定类型的特征或包封的任何特定方式的特征限制。
实例方法3000可以在块3040处包括形成防护层。块3040可以包括以任何各种方式形成防护层(例如,在半导体裸片上、在包封材料上等),在此提供所述各种方式的非限制性实例。块3040可以例如与图1的实例方法1000的块1040共享任何或全部特征。应注意,防护层也可以称为保护层。
防护层(或板)可以包括任何各种特征。防护层可以例如防止半导体裸片受外部力和/或污染物(例如,归因于手指按压、滑动等)影响。防护层可以例如具有背对半导体裸片的第一面(例如,顶面或顶表面)、朝向半导体裸片的第二面(例如,底面或底表面)以及在第一面与第二面之间的外围面(例如,侧面或侧表面)。防护层可以例如包括均匀的厚度层。防护层可以例如定位在块3020处安装的半导体裸片的第一面(例如,顶面)上或跨所述第一面定位。防护层可以例如覆盖半导体裸片的整个第一面。防护层还可以例如定位在块3030处形成的包封材料的第一面(例如,顶面)上或跨所述第一面。防护层可以例如覆盖包封材料的整个第一面或可以仅覆盖包封材料的第一面的在半导体裸片的第一面的外围周围的一部分。例如,包封材料的顶面的外周界可以保持不被防护层覆盖。
防护层可以包括任何各种材料。例如,防护层可以是或包括氧化铝(Al2O3)、其任何变体等。又例如,防护层可以是或包括聚合物。一般来说,防护层可以是或包括本文中揭示的各种介电材料中的任何一个或多个。防护层还可以例如与本文中关于图1所论述的防护板共享任何或全部特征。
块3040可以包括以任何各种方式形成防护层。例如,块3040可以包括形成掩模图案以覆盖除意图由防护层覆盖的区之外的区。块3040接着可例如包括将防护层材料涂覆到组合件的未被掩模层覆盖的部分(例如,半导体裸片的第一面的一部分或全部、包封材料的一部分或全部等)。在另一实例实施方案中,块3040可以利用选择性印刷或不使用掩模层的涂覆来涂覆防护层。在再一实例实施方案中,块3040可以包括形成防护层为跨至少半导体裸片的整个第一面、包封材料的整个顶面和/或侧面、和/或衬底的暴露顶面的覆盖层。在再一实例实施方案中,块3040可以包括涂覆和粘附防护层材料的预制板或薄膜。
例如,在其中防护层为或包括聚合物的实例实施方案中,块3040可以包括包覆聚合物(例如,利用本文中呈现的任何层形成工艺)且接着固化聚合物(例如,通过施加热量、紫外辐射等)。又例如,在其中防护层包括氧化铝(或类似物)层的实例实施方案中,块3040可以包括通过粒子冲击(或机械冲击)、热喷涂、等离子体喷涂、超音速火焰(HVOF)喷涂等形成氧化铝层。
示出块3040的各种方面的实例实施方案400B在图4B处示出。实例实施方案400B(或组合件、子组合件、封装等)包括防护层240。实例防护层240具有背对半导体裸片110的第一面(例如,顶面或顶表面)、朝向半导体裸片110的第二面(例如,底面或底表面)以及在第一面与第二面之间的外围面(例如,侧面或侧表面)。实例防护层240覆盖半导体裸片的整个顶面110a,并覆盖包封材料230的在半导体裸片110周界周围的顶面230a。包封材料230的顶面230a的外周界不被实例防护层240覆盖,但是在另一实例实施方案中可以例如被覆盖。
在实例实施方案400B中,在半导体裸片的上侧面110a之上不存在电导体(例如,指纹感测迹线或元件或电极或图案等)。然而,情况并不总是如此,如将在本文中呈现的其它实例实施方案中示出。
一般来说,块3040可以包括形成防护层。因此,本发明的范围不应受防护层的任何特定类型的特征或形成防护层的任何特定方式的特征限制。
实例方法3000可以在块3095处包括必要时继续制造(或处理)。块3095可以包括以任何各种方式继续制造(或处理),在此提供所述各种方式的非限制性实例。块3095可以例如与图1的实例方法1000的块1095共享任何或全部特征。
如图4B中示出的实例实施方案400B中所示(所述实例实施方案在本文中还可以称为指纹感测器装置200(或封装)),根据图3的实例方法3000制造的实例指纹感测器装置可以在手指(或其指纹)触摸或极为接近于防护层240的顶面140a时基于电容的改变而感测指纹,其在半导体裸片110的第一面110a上,所述半导体裸片在其底面110b上包含多个第一导电凸块111和指纹感测单元112。指纹感测器装置(或封装)200可进一步包含电连接到衬底120的导电图案(例如,在其底面120b和/或顶面120a上)的柔性电路板或其它互连结构(未示出)。柔性电路板可以例如电连接到指纹感测器封装200的一个或多个输入和/或输出垫以及电连接到外部衬底或外部电子装置。由于实例半导体裸片110以倒装晶片配置安装在衬底120上,因此指纹感测器封装200提供相对于其它配置简化的制造过程。
虽然本文中呈现的各种实例实施方案通过半导体裸片感测指纹,但是可以替代地(或又)通过半导体裸片所附着到的衬底执行指纹感测。现将呈现此配置的实例实施方案以及用于制作此配置的方法。
图5示出根据本发明的各种方面的制作感测器装置(例如,指纹感测器装置)的实例方法5000的流程图。实例方法5000可以例如与本文中所论述的任何其它方法(例如,图1的实例方法1000、图3的实例方法3000等)共享任何或全部特征。图6A-6E示出说明根据本发明的各种方面的实例感测器装置的横截面图以及制作感测器装置的实例方法。6A-6E中示出的结构可以与图2A-2E、图4A-4B、图7-9等中示出的类似结构共享任何或全部特征。图6A-6E可以例如示出在图5的实例方法5000的各种阶段(或块)的实例感测器装置(例如,指纹感测器装置)。现将一起论述图5和6A-6E。应注意,在不脱离本发明的范围的情况下,可以改变实例方法5000的实例块(或其部分)的顺序,可以省略或添加各种块(或其部分),和/或可以改变各种块(或其部分)。
一般来说,实例方法5000可以包括提供半导体裸片(块5010)、安装半导体裸片(块5020)、包封(块5025)、形成通孔(块5027)、形成导电层(块5028)、形成互连结构(块5035)以及形成防护层(块5040)。
实例方法5000可以在块5005处开始执行。实例方法5000可以出于任何各种原因而开始执行,在此提供所述各种原因的非限制性实例。例如,实例方法5000可以出于本文中关于图1的实例方法1000所论述的任何或全部原因而开始执行。例如,块5005可以与图1的实例方法1000的块1005共享任何或全部特征。
实例方法5000可以在块5010处包括提供半导体裸片。块5010可以包括以任何各种方式提供半导体裸片,在此提供所述各种方式的非限制性实例。块5010可以例如与图1的实例方法1000的块1010共享任何或全部特征。
实例方法5000可以在块5020处包括安装半导体裸片。块5020可以包括以任何各种方式安装半导体裸片,在此提供所述各种方式的非限制性实例。块5020可以例如与图1的实例方法1000的块1020共享任何或全部特征。
实例方法5000可以在块5025处包括包封。块5025可以包括以任何各种方式包封(例如,半导体裸片、衬底等),在此提供所述各种方式的非限制性实例。块5025可以例如与图3的实例方法3000的块3025共享任何或全部特征。
如块3025的论述中所提及,可以保留半导体裸片的第一面(例如,顶面或顶表面等)暴露的方式或以覆盖半导体裸片的第一面的方式形成包封材料。在本文中所论述的块5025的实例实施方案中,包封材料形成为覆盖半导体裸片的第一面(例如,覆盖半导体裸片的整个第一面)。
示出块5025的各种方面的实例实施方案600A在图6A处示出。实例实施方案600A的组件可以例如与本文中示出和论述的其它实例实施方案的类似编号的组件共享任何或全部特征,并且因此将不重复此类组件的详细论述。应注意,相对于本文中(例如,关于图2A-2E、图4A-4B、图7-8等)呈现的各种其它图式,一般倒转地示出图6A-6E。然而,保持类似组件的编号。
应注意,如同本文中的所有类似编号的元件一样,实例实施方案600A的衬底120可以与本文中所论述的图1的衬底(例如,图2B的实例实施方案200B的衬底120)共享任何或全部特征。例如,在实例实施方案中,衬底120可以是或包括玻璃和/或的任何各种材料,和/或可以具有被配置成允许通过其(例如,在感测区域112处)测量指纹相关电容(或电容变化)的厚度和/或电渗透性。
实例实施方案600A(或组合件、子组合件、封装等)包括覆盖衬底120的第一面120a的包封材料330。应注意,包封材料330可以与本文中所揭示的其它包封材料(例如,图4A-4B的实例包封材料230等)共享任何或全部特征。
实例包封材料330又覆盖在衬底120的第一面120a上或在所述第一面处的导电迹线121(或图案、焊盘、垫片等)。实例包封材料330另外覆盖并围绕半导体裸片110的外围面110c。实例包封材料330进一步填充半导体裸片110(例如,其第二面110b)与衬底120(例如,其第一面120a)之间的体积,例如作为底部填充胶,并且围绕导电互连结构111。然而,应注意,在实例实施方案中,半导体裸片110与衬底120之间的体积可以保持为空(例如,如果形成则与互连结构111隔开)。在另一实例实施方案中,可以通过与包封材料330不同的底部填充材料填充半导体裸片110与衬底120之间的体积。
一般来说,块5025可以包括包封。因此,本发明的范围不应受包封材料的任何特定类型的特征或包封的任何特定方式的特征限制。
实例方法5000可以在块5027处包括形成通孔。块5027可以包括以任何各种方式形成一个或多个通孔(例如,穿过在块5025处形成的包封材料等),在此提供所述各种方式的非限制性实例。通孔也可以称为贯穿孔。
通孔可以例如延伸穿过(例如,完全穿过等)包封材料。例如,通孔可以从包封材料的第一面或表面延伸到包封材料的第二面或表面。例如,通孔可以从包封材料的第一面延伸到衬底的第一面上的图案(或迹线、或焊盘、或垫片、或通孔终止处等),其经由通孔通过包封材料暴露。
块5027可以例如包括通过消融通孔(例如,激光消融、等离子体消融、机械消融或钻孔等)形成通孔。块5027还可以例如包括利用化学蚀刻或溶解形成通孔。另外例如,块5027可以与块5025组合以在执行包封时形成通孔(例如,利用掩蔽、模套特征等以在形成包封材料时形成通孔)。
示出块5027的各种方面的实例实施方案600B在图6B处示出。实例实施方案600B(或组合件、子组合件、封装等)包括穿过包封材料330的通孔331(或贯穿孔)。实例通孔331从包封材料330的第一面330a延伸到包封材料330的第二面330b并暴露衬底120的导电迹线121(或导电通孔122)。示出实例通孔331以包封材料330的倾斜内侧面为界。例如,实例通孔331在包封材料330的第一表面330a处比在包封材料的第二表面330b处更宽。此类形状可以有利地改善导电层或填充剂的后续形成。实例通孔331还可以具有直面(例如,正交于包封材料330的第一表面330a和第二表面330b)。
一般来说,块5027可以包括形成一个或多个通孔。因此,本发明的范围不应受通孔(或贯穿孔)的任何特定类型的特征或形成通孔的任何方式的特征限制。
实例方法5000可以在块5028处包括形成导电层。块5028可以包括以任何各种方式形成导电层,在此提供所述各种方式的非限制性实例。
导电层可以例如包括图案,所述图案包含任何各种特征。例如,导电层可以包括迹线、垫片、焊盘、通孔衬垫或填充剂等。导电层也可以称为再分布层。
导电层可以例如包括用于填充在块5027处形成的通孔或为所述通孔加衬的导电通孔部分。导电通孔部分可以例如在经由通孔穿过包封材料暴露的衬底的图案上形成和/或电连接到所述图案。在实例实施方案中,导电层的导电通孔部分可以为界定(或限定)通孔的包封材料的壁加衬。接着可保留通过导电层衬垫界定(或限定)的空腔。此类空腔可以保留不填充、用介电材料填充、用导电材料(例如,与导电层材料不同的材料,例如焊接材料、导电环氧树脂等)填充等。在另一实例实施方案中,导电层可以完全地填充通孔。
导电层还可以例如包括在其上可以形成互连结构(例如,在块5035处)的导电焊盘部分(或垫片、迹线、图案等)。此外,导电层可以例如包括在导电通孔部分与导电焊盘部分之间延伸的导电迹线部分。
导电层可以包括任何各种材料(例如,铜、铝、镍、铁、银、金、钛、铬、钨、钯、其组合、其合金、其等效物等),但是本发明的范围不限于此。
块5028可以例如包括利用各种工艺(例如,电解电镀、无电极电镀、化学气相沉积(CVD)、溅镀或物理气相沉积(PVD)、原子层沉积(ALD)、等离子体气相沉积、印刷、丝网印刷、光刻等)中的任何一个或多个形成(或沉积)导电层,但是本发明的范围不限于此。
示出块5028的各种方面的实例实施方案600C在图6C处示出。实例实施方案600C(或组合件、子组合件、封装等)包括导电层350,所述导电层包括导电通孔部分350a,所述导电通孔部分在通过穿过包封材料330的通孔331暴露的衬底120的导电迹线121(或导电通孔122)上,且又为界定(或限定)通孔331的包封材料330的壁加衬,从而留下可以填充或可以不填充的空腔。实例导电层350又包括在包封材料330的第一面330a上的导电焊盘部分350b,在所述导电焊盘部分上可以形成互连结构(例如,在块5035处)。实例导电通孔部分350a和导电焊盘部分350b通过导电层350的导电迹线部分电连接。
虽然实例实施方案600C仅示出了单个导电层,但是本发明的范围不限于此。例如,可以形成任何数目的导电层和/或介电层以建造多层信号分配结构。
一般来说,块5028可以包括形成导电层。因此,本发明的范围不应受导电层(或图案)的任何特定类型的特征或形成导电层(或图案)的任何方式的特征限制。
实例方法5000可以在块5035处包括形成导电互连结构。块5035可以包括以任何各种方式形成一个或多个导电互连结构,在此提供所述各种方式的非限制性实例。
如本文中所论述,在块5028处形成的导电层可以包括在其上可以形成导电互连结构的导电焊盘部分。在导电焊盘部分上形成(或附着到导电焊盘部分)的导电互连结构可以是或包括任何各种不同类型的导电互连结构(例如,导电球或导电凸块、焊料球或焊料凸块、金属柱或金属桩、铜柱或铜桩、焊料加盖柱或焊料加盖桩、焊胶、导电粘合剂等)。在实例实施方案中,导电互连结构可以耦合到导电层的导电焊盘部分,所述导电焊盘部分又耦合到衬底的导电图案,所述导电图案又耦合到另一导电互连结构,所述另一导电互连结构又耦合到半导体裸片的接合垫。导电互连结构可以例如在指纹感测器装置与另一电路(例如,母板、柔性电路或其它线缆、多芯片模块的衬底等)之间提供连接。
块5035可以例如包括以任何各种方式形成导电互连结构,在论述图1的实例方法1000的块1010时提供了所述各种方式的非限制性实例,但是本发明的范围不限于此。此类导电互连结构可以例如是用于将半导体裸片连接到衬底的相同类型的导电互连结构,或可以是不同类型的导电互连结构。
示出块5035的各种方面的实例实施方案600D在图6D处示出。实例实施方案600D(或组合件、子组合件、封装等)包括在导电层350的导电焊盘部分350b上形成的导电互连结构360(例如,导电凸块)。导电层的导电焊盘部分350b又耦合到衬底120的导电图案121,所述导电图案又耦合到导电互连结构111,所述导电互连结构又耦合到半导体裸片110。
一般来说,块5035可以包括形成导电互连结构。因此,本发明的范围不应受导电互连结构的任何特定类型的特征或形成导电互连结构的任何方式的特征限制。
实例方法5000可以在块5040处包括形成防护层。块5040可以包括以任何各种方式形成防护层,在此提供所述各种方式的非限制性实例。块5040可以例如与图3的实例方法3000的块3040和/或与图1的实例方法1000的块1040共享任何或全部特征。
防护层(或板)可以包括任何各种特征。防护层可以例如防止衬底(或半导体裸片)受外部力和/或污染物(例如,归因于手指按压、滑动等)影响。防护层可以例如具有朝向衬底的第一面或表面、背对衬底的第二面或表面以及在第一面与第二面之间的外围面或表面。防护层可以例如包括均匀的厚度层。防护层可以例如定位在衬底的第二面上或跨所述第二面定位。防护层可以例如覆盖衬底的整个第二面。
防护层可以包括任何各种材料。例如,防护层可以是或包括氧化铝(Al2O3)、其任何变体等。又例如,防护层可以是或包括聚合物。一般来说,防护层可以是或包括本文中揭示的各种介电材料中的任何一个或多个。防护层还可以例如与本文中关于图1所论述的防护板和/或与本文中关于图3所论述的防护层共享任何或全部特征。
块5040可以包括以任何各种方式形成防护层。例如,块5040可以包括形成掩模图案以覆盖除意图由防护层覆盖的区之外的区。块5040接着可例如包括将防护层材料涂覆到组合件的未被掩模层覆盖的部分(例如,衬底的第二面的一部分或全部等)。在另一实例实施方案中,块5040可以包括利用选择性印刷或不使用掩模层的涂覆来涂覆防护层。在再一实例实施方案中,块5040可以包括形成防护层为跨至少衬底的整个第二面的覆盖层。在再一实例实施方案中,块5040可以包括涂覆和粘附防护层材料的预制板或薄膜。
例如,在其中防护层为或包括聚合物的实例实施方案中,块5040可以包括包覆聚合物(例如,利用本文中呈现的任何层形成工艺)且接着固化聚合物(例如,通过施加热量、紫外辐射等)。又例如,在其中防护层包括氧化铝(或类似物)层的实例实施方案中,块5040可以包括通过粒子冲击(或机械冲击)、热喷涂、等离子体喷涂、超音速火焰(HVOF)喷涂等形成氧化铝层。
示出块5040的各种方面的实例实施方案600E在图6E处示出。实例实施方案600E(或组合件、子组合件、封装等)包括防护层340。实例防护层340具有朝向衬底120的第一面或表面、背对衬底120的第二面或表面以及在第一面与第二面之间的外围面或表面。实例防护层340覆盖衬底120的整个第二面120b。实例防护层340的外围面与衬底120和包封材料330的外围面共面。
应注意,如同本文中所论述的全部块一样,可以在晶片或面板级执行块5040。例如,块5040可以包括在同一程序中在多个指纹感测器装置上形成防护层,其中后续可以单一化(或切离)此类装置。
一般来说,块5040可以包括形成防护层。因此,本发明的范围不应受防护层的任何特定类型的特征或形成防护层的任何特定方式的特征限制。
实例方法5000可以在块5095处包括必要时继续制造(或处理)。块5095可以包括以任何各种方式继续制造(或处理),在此提供所述各种方式的非限制性实例。块5095可以例如与图1的实例方法1000的块1095共享任何或全部特征。如本文中所论述,在不脱离本发明的范围的情况下,可以改变任何各种实例方法块和/或相关联结构。例如,参考图1中示出且本文中论述的实例方法1000,块1040包括附着防护板。关于图1和2A-2E所论述的实例防护板不具有电路。然而,防护板可以包括电路。此类电路可以例如包括一个或多个导电层,一个或多个导电层包括迹线、垫片、焊盘等。此类导电层可以例如在防护板的外表面上和/或可以在防护板内部(例如,在分层或层合结构中)。此类电路还可以例如包括有源和/或无源电路组件。在实例实施方案中,此类电路还可以包括用以处理通过半导体裸片感测的指纹相关信息的处理电路。
在实例实施方案中,防护板的导电层和/或电组件可以利用在防护板的导电层(例如,垫片、焊盘、迹线、图案等)与衬底的导电层(例如,垫片、焊盘、迹线、图案等)之间延伸的一个或多个导电互连结构电耦合到衬底。导电互连结构(或其形成)可以例如与本文中所论述的任何导电互连结构(或其形成)共享任何或全部特征。导电互连结构(或多个导电互连结构)可以例如包括导电凸块或导电球(例如,焊料凸块或焊料球等)、金属柱或金属桩(例如,铜柱或铜桩)、导电凸块或导电球的堆叠、铜芯焊料球等。导电互连结构可以例如定位在半导体裸片的周界之外。例如,多个导电互连结构可以在任何数目的面(例如,四个面、两个面、三个面、一个面等)上围绕半导体裸片。
示出修改后的块1040的各种方面的实例实施方案700在图7处示出,图7示出说明根据本发明的各种方面的实例实施方案700的截面视图。实例实施方案700也可以称为指纹感测器装置400。
实例实施方案700(或组合件、子组合件、封装等)可以与图2E中示出且本文中论述的实例实施方案200E共享任何或全部特征。一般来说,此论述将集中于此类实例实施方案之间的区别。
在实例实施方案700中,防护板440具有第一面440a(例如,顶面或顶表面)、第二面440b(例如,底面或底表面)以及在第一面440a与第二面440b之间的外围面(例如,侧面或侧表面)。实例防护板440包括导电层442(例如,一个或多个迹线、垫片、焊盘、图案、电子装置、电子电路、逻辑电路、处理电路、指纹感测电极、接地迹线等)。导电层442可以位于防护板440的第一面440a和/或第二面440b处和/或在其之间。防护板440的导电层442利用导电互连结构441耦合到衬底120的导电迹线121和/或导电通孔122。通过回焊、电镀、不使用回焊的直接金属与金属耦合、导电环氧树脂、本文中所论述的任何接合技术等,导电互连结构441可以例如连接到防护板440的导电层442和/或连接到衬底120的导电迹线121和/或导电通孔122。在实例实施方案中,多个导电互连结构441定位在半导体裸片110的外周界周围(例如,在半导体裸片110的覆盖面积之外),围绕半导体裸片110的任何数目的面(例如,四个面、两个面、三个面、一个面等)。
应注意,如图7中所示,导电层442的位置在半导体裸片110的感测区域112的覆盖面积之外。然而,情况并不总是如此。例如,当导电层442辅助指纹感测活动时(例如,当导电层442包括指纹感测电极时,等),导电层442的各种部分可以跨感测区域112定位。
防护板440的导电层442可以例如通过互连结构441、导电迹线121和互连结构111电连接到半导体裸片110。导电层442还可以例如通过互连结构441、导电迹线121和导电通孔122连接到另一电路。
在实例实施方案700中,例如,如同实例实施方案200E和本文中所论述的其它实例实施方案一样,指纹感测单元112可以例如通过半导体裸片112、粘合层130和防护板440感测指纹。又应注意,作为导电层442的部分或以其它方式,防护板440可以包含通过互连结构441、导电迹线121和互连结构111电耦合到指纹感测单元112的指纹感测电极。
应注意,尽管示出防护板440通过粘合层130耦合到半导体裸片110,并通过互连结构441和/或边框150耦合到衬底,但是可以省略此类耦合中的一个或多个。
作为其中在不脱离本发明的范围的情况下可以改变一个或多个方法块和/或相关联结构和/或可以添加或省略各种方法块的另一实例实施方案,可以在半导体裸片与防护板(或防护层)之间放置插入件。例如,与图7中示出且本文中论述的实例实施方案700相比,插入件可以包括本文中关于实例防护板所论述的电路(例如,所述电路替代防护板、除防护板外还包括电路等)。插入件接着可以如关于图7的实例防护板所论述的相同方式附着到半导体裸片和/或衬底。防护板(例如,类似关于图1、3、5、7所论述的防护板(或防护层)等)接着可跨插入件附着(或形成)。
插入件可以包括任何各种特征。例如,插入件可以包括本文中关于衬底120所论述的任何或全部特征。
图8示出实例实施方案800,图8示出说明根据本发明的各种方面的实例实施方案800的横截面图。实例实施方案800也可以称为指纹感测器装置500。
实例实施方案800(或组合件、子组合件、封装等)可以与图2E中示出且本文中论述的实例实施方案200E、与图4B中示出且本文中论述的实例实施方案400B、与图7中示出且本文中论述的实例实施方案700等共享任何或全部特征。一般来说,此论述将集中于此类实例实施方案之间的区别。
在实例实施方案800中,插入件560具有第一面560a(例如,顶面或顶表面)、第二面560b(例如,底面或底表面)以及在第一面560a与第二面560b之间的外围面(例如,侧面或侧表面)。实例插入件560包括导电层562(例如,一个或多个迹线、垫片、焊盘、图案、电子装置、电子电路、逻辑电路、处理电路、指纹感测电极、接地迹线等)。导电层562可以位于插入件560的第一面560a和/或第二面560b处和/或在其之间。插入件560的导电层562利用导电互连结构561耦合到衬底120的导电迹线121和/或通孔122。通过回焊、电镀、不使用回焊的直接金属与金属耦合、导电环氧树脂、本文中所论述的任何接合技术等,导电互连结构561可以例如连接到插入件560的第一导电层562和/或连接到衬底120的导电迹线121和/或通孔122。
应注意,如图8中所示,导电层562的位置在半导体裸片110的感测区域112的覆盖面积之外。然而,情况并不总是如此。例如,当导电层562辅助指纹感测活动时(例如,当导电层562包括指纹感测电极时,等),导电层562的各种部分可以跨感测区域112定位。
插入件560的导电层562可以例如通过互连结构561、导电迹线121和互连结构111电连接到半导体裸片110。导电层562还可以例如通过互连结构561、导电迹线121和导电通孔122连接到另一电路。
例如,如关于实例方法1000的块1040所论述,防护板140接着可附着到插入件560的第一面560a(例如,顶面或顶表面)。可以例如利用粘合层(未示出)、利用边框151提供的机械耦合、或任何各种耦合技术来执行此类附着。
在实例实施方案800中,指纹感测单元112可以例如通过半导体裸片110、粘合层130、插入件560和防护板140感测指纹。又应注意,作为导电层562的部分或以其它方式,插入件560可以包含通过互连结构561、导电迹线121和互连结构111电耦合到指纹感测单元112的指纹感测电极。
作为其中在不脱离本发明的范围的情况下可以改变一个或多个方法块和/或相关联结构和/或可以添加或省略各种方法块的另一实例实施方案,可以在本文中所揭示的任何或全部实例实施方案中倒转半导体裸片的定向。例如,与图7中示出且本文中论述的实例实施方案700相比,可以倒转半导体裸片。因此,替代利用导电互连结构附着到衬底以及利用粘合层附着到防护板,半导体裸片可以利用粘合层附着到衬底以及利用导电互连结构附着到防护板(或附着到图8中示出的实例实施方案800的插入件)。
图9示出实例实施方案900,图9示出说明根据本发明的各种方面的实例实施方案900的横截面图。实例实施方案900也可以称为指纹感测器装置600。
实例实施方案900(或组合件、子组合件、封装等)可以与图2E中示出且本文中论述的实例实施方案200E、与图7中示出且本文中论述的实例实施方案700等共享任何或全部特征。一般来说,此论述将集中于此类实例实施方案之间的区别。
相对于实例实施方案200E、400B和700,在实例实施方案900中,半导体裸片610安装到衬底120的第一面120a,其中背面610b向下且正面610a(例如,包含感测单元612(或感测区域)的面)向上。半导体裸片610可以与本文中所论述的任何实例半导体裸片(例如,半导体裸片110等)共享任何或全部特征。
粘合层630可以与本文中所论述任何粘合层(例如,粘合层130等)共享任何或全部特征。如图9中所示,粘合层630的顶面粘附到半导体裸片610的底面610b,并且粘合层630的底面粘附到衬底120的顶面120a。在实例实施方案900中,在衬底120的第一面120a与半导体裸片610的第二面610b之间不存在直接电连接。然而,应注意,替代实施方案可以利用导电粘合层630用于向半导体裸片610的接地信号传递,以改善热传递等。在另一替代实施方案中,可以省略粘合层630。
如同图7的实例实施方案700一样,实例实施方案900包含防护板440,所述防护板包括导电层442(例如,一个或多个迹线、垫片、图案或焊盘;电子装置、电子电路、逻辑电路、处理电路、指纹感测电极、接地迹线等)。导电层442可以位于插入件防护板440的第一面440a和/或第二面440b处和/或在其之间。防护板440的导电层442利用导电互连结构441耦合到衬底120的导电迹线121和/或导电通孔122。通过回焊、电镀、不使用回焊的直接金属与金属耦合、导电环氧树脂、本文中所论述的任何接合技术等,导电互连结构441可以例如连接到防护板440的导电层442和/或衬底120的导电迹线121和/或导电通孔122。
在实例实施方案900中,半导体裸片630(例如,其接合垫)利用一个或多个导电互连结构611耦合到防护板440的导电层442。导电互连结构611可以例如与本文中所论述导电互连结构111共享任何或全部特征。
半导体裸片610(例如,其接合垫)可以通过互连结构611、防护板440的导电层442和互连结构441电连接到衬底120。半导体裸片610还可以例如通过互连结构611、防护板440的导电层442、互连结构441、导电迹线121和导电通孔122连接到另一电路。
应注意,尽管示出防护板440通过互连结构611耦合到半导体裸片110,并通过互连结构441和/或边框150耦合到衬底,但是可以省略此类耦合中的一个或多个。例如,在其中防护板440是另一装置(例如,其中集成指纹感测器装置600的消费型电子装置)的板的实例实施方案中,防护板440可能是较大板(例如,窗口、涂层、显示屏幕等)的一部分。在此实施方案中,可以省略或重新配置边框150(例如,重新配置为不延伸高于防护板440的底面440b),因为防护板440的顶表面440a和/或侧表面可能无法接近指纹感测器装置600。
在实例实施方案900中,指纹感测单元612可以例如通过防护板440、通过指纹感测单元612之间的空隙(例如,如果存在此类空隙,且是否用粘合材料或底部填充胶填充此类空隙)等感测指纹。又应注意,作为导电层442的部分或以其它方式,防护板440可以包含通过互连结构611电耦合到指纹感测单元112的指纹感测电极。
本文中的论述包含示出电子装置(例如,指纹感测器装置)的各种部分及其制造方法的许多示意图。为了清楚地示意,这些图并未示出每个实例组合件的所有方面。本文中提供的任何实例组合件和/或方法可以与本文中提供的任何或全部其它组合件和/或方法共享任何或全部特征。
综上所述,本发明的各种方面提供一种指纹感测器装置和一种制作指纹感测器装置的方法。作为非限制性实例,本发明的各种方面提供各种指纹感测器装置及其制造方法,所述指纹感测器装置包括在裸片的底面上的感测区域,其不具有从顶面感测指纹的顶面电极,和/或所述指纹感测器装置包括直接电连接到板(通过所述板感测指纹)的导电元件的感测器裸片。虽然已经参考某些方面和实例描述了以上内容,但是所属领域的技术人员应理解,在不脱离本发明的范围的情况下,可以进行各种修改并可以替代等效物。另外,在不脱离本发明的范围的情况下,可以进行许多修改以使特定情况或材料适应本发明的教示内容。因此,希望本发明不限于所揭示的特定实例,而是本发明将包含落入所附权利要求书的范围内的所有实例。
Claims (20)
1.一种指纹感测器装置,其包括:
衬底,所述衬底具有衬底顶面、衬底底面以及在所述衬底顶面与所述衬底底面之间的衬底侧面;
半导体裸片,所述半导体裸片具有裸片顶面、裸片底面以及在所述裸片顶面与所述裸片底面之间的裸片侧面,其中所述裸片底面包括感测区域,所述感测区域包括指纹感测单元;
多个第一互连结构,所述多个第一互连结构将所述裸片底面电连接到所述衬底顶面;以及
在所述裸片顶面上的防护板,通过所述防护板感测指纹,所述防护板具有板顶面、板底面以及在所述板顶面与所述板底面之间的板侧面。
2.根据权利要求1所述的指纹感测器装置,其中所述指纹感测单元包括指纹感测电路。
3.根据权利要求1所述的指纹感测器装置,其中所述感测区域在所述裸片底面的中心区域中,并且所述多个第一互连结构定位在所述感测区域之外。
4.根据权利要求1所述的指纹感测器装置,其包括粘附到所述裸片顶面并粘附到所述板底面的粘合层。
5.根据权利要求4所述的指纹感测器装置,其中所述粘合层完全覆盖所述裸片顶面。
6.根据权利要求1所述的指纹感测器装置,其中所述指纹感测器装置的指纹感测电极均不在所述裸片顶面上。
7.根据权利要求1所述的指纹感测器装置,其包括多个第二互连结构,所述多个第二互连结构耦合到所述板底面并耦合到所述半导体裸片的覆盖面积之外的所述衬底顶面,并且其中所述防护板包括多个导电迹线,所述多个导电迹线中的每一个电连接到所述第二互连结构中的相应一个。
8.根据权利要求1所述的指纹感测器装置,其中所述防护板包括玻璃。
9.根据权利要求1所述的指纹感测器装置,其包括在所述裸片顶面与所述防护板之间的插入件。
10.根据权利要求9所述的指纹感测器装置,其包括多个第二互连结构,所述多个第二互连结构耦合到所述插入件的底面并耦合到所述半导体裸片的覆盖面积之外的所述衬底顶面,并且其中所述插入件包括多个导电迹线,所述多个导电迹线中的每一个电连接到所述第二互连结构中的相应一个。
11.一种指纹感测器装置,其包括:
衬底,所述衬底具有衬底顶面、衬底底面以及在所述衬底顶面与所述衬底底面之间的衬底侧面;
半导体裸片,所述半导体裸片具有裸片顶面、裸片底面以及在所述裸片顶面与所述裸片底面之间的裸片侧面,其中所述裸片底面包括感测区域,所述感测区域包括指纹感测电路;
多个第一互连结构,所述多个第一互连结构将所述裸片底面电连接到所述衬底顶面;
围绕所述裸片侧面的包封材料;以及
在所述裸片顶面上的防护层,通过所述防护层感测指纹,所述防护层具有防护层顶面、防护层底面以及在所述防护层顶面与所述防护层底面之间的防护层侧面。
12.根据权利要求11所述的指纹感测器装置,其中所述包封材料包括与所述裸片顶面共面的顶面。
13.根据权利要求11所述的指纹感测器装置,其中所述防护层包括涂层。
14.根据权利要求11所述的指纹感测器装置,其中所述防护层完全覆盖所述裸片顶面。
15.根据权利要求11所述的指纹感测器装置,其中所述防护层覆盖所述包封材料的顶面的至少一部分。
16.一种指纹感测器装置,其包括:
衬底,所述衬底具有衬底顶面、衬底底面以及在所述衬底顶面与所述衬底底面之间的衬底侧面;
板,通过所述板感测指纹,所述板具有板顶面、板底面以及在所述板顶面与所述板底面之间的板侧面;
半导体裸片,所述半导体裸片具有裸片顶面、裸片底面以及在所述裸片顶面与所述裸片底面之间的裸片侧面,其中所述裸片顶面包括感测区域,所述感测区域包括指纹感测单元;以及
多个第一导电互连结构,所述多个第一导电互连结构将所述裸片顶面电连接到所述板底面。
17.根据权利要求16所述的指纹感测器装置,其中所述板包括多个导电迹线,所述多个导电迹线中的每一个耦合到所述第一导电互连结构中的相应一个。
18.根据权利要求17所述的指纹感测器装置,其中所述板的所述多个导电迹线嵌入所述板内。
19.根据权利要求17所述的指纹感测器装置,其包括多个第二导电互连结构,所述多个第二导电互连结构中的每一个耦合到所述板的所述导电迹线中的相应一个并耦合到所述衬底顶面。
20.根据权利要求16所述的指纹感测器装置,其中所述板包括玻璃。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202210825314.XA CN115117106A (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器及其制造方法 |
CN201911035681.4A CN110739275B (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器及其制造方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2015-0065900 | 2015-05-12 | ||
KR1020150065900A KR101942141B1 (ko) | 2015-05-12 | 2015-05-12 | 지문센서 패키지 |
US15/131,967 | 2016-04-18 | ||
US15/131,967 US10297515B2 (en) | 2015-05-12 | 2016-04-18 | Fingerprint sensor and manufacturing method thereof |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911035681.4A Division CN110739275B (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器及其制造方法 |
CN202210825314.XA Division CN115117106A (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器及其制造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106158760A true CN106158760A (zh) | 2016-11-23 |
Family
ID=57277544
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201620428887.9U Active CN205984935U (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器装置 |
CN201911035681.4A Active CN110739275B (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器及其制造方法 |
CN202210825314.XA Pending CN115117106A (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器及其制造方法 |
CN201610313065.0A Pending CN106158760A (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器及其制造方法 |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201620428887.9U Active CN205984935U (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器装置 |
CN201911035681.4A Active CN110739275B (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器及其制造方法 |
CN202210825314.XA Pending CN115117106A (zh) | 2015-05-12 | 2016-05-12 | 指纹感测器及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (5) | US10297515B2 (zh) |
KR (1) | KR101942141B1 (zh) |
CN (4) | CN205984935U (zh) |
TW (4) | TW202220117A (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108229340A (zh) * | 2016-12-15 | 2018-06-29 | 指纹卡有限公司 | 指纹感测模块及其制造方法、智能卡及其制造方法 |
CN108630623A (zh) * | 2017-03-21 | 2018-10-09 | 矽品精密工业股份有限公司 | 封装结构及其制法 |
US11023702B2 (en) | 2016-12-15 | 2021-06-01 | Fingerprint Cards Ab | Fingerprint sensing module and method for manufacturing the fingerprint sensing module |
CN112906442A (zh) * | 2019-12-04 | 2021-06-04 | 茂丞科技股份有限公司 | 晶圆级超声波装置及其制造方法 |
US20210307225A1 (en) * | 2018-08-22 | 2021-09-30 | Pragmatic Printing Ltd. | Profiled thermode |
US11610429B2 (en) | 2016-12-15 | 2023-03-21 | Fingerprint Cards Anacatum Ip Ab | Fingerprint sensing module and method for manufacturing the fingerprint sensing module |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160143071A (ko) * | 2015-06-04 | 2016-12-14 | 앰코 테크놀로지 코리아 주식회사 | 지문센서 패키지 |
US10002281B2 (en) * | 2015-07-09 | 2018-06-19 | Gingy Technology Inc. | Fingerprint identification module |
US10489631B2 (en) | 2015-07-09 | 2019-11-26 | Gingy Technology Inc. | Biometric identification module |
KR102592972B1 (ko) * | 2016-02-12 | 2023-10-24 | 삼성전자주식회사 | 센싱 모듈 기판 및 이를 포함하는 센싱 모듈 |
KR101973431B1 (ko) * | 2016-09-29 | 2019-04-29 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
US20180165495A1 (en) * | 2016-12-09 | 2018-06-14 | Fingerprint Cards Ab | Electronic device |
CN108241830A (zh) * | 2016-12-23 | 2018-07-03 | 创智能科技股份有限公司 | 生物特征辨识装置 |
CN107184209A (zh) * | 2017-05-19 | 2017-09-22 | 华为机器有限公司 | 检测皮肤水分的方法和终端设备 |
KR101901714B1 (ko) | 2017-10-27 | 2018-09-27 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
WO2019103676A1 (en) * | 2017-11-24 | 2019-05-31 | Fingerprint Cards Ab | Ultra-thin fingerprint sensor component and manufacturing method |
TWI646020B (zh) * | 2018-01-26 | 2019-01-01 | 致伸科技股份有限公司 | 指紋辨識模組包裝方法 |
KR102716356B1 (ko) * | 2019-01-25 | 2024-10-10 | 삼성전자주식회사 | 생체신호 측정용 텍스쳐 인터페이스 및 이를 포함한 생체신호 측정장치 |
CN109871793A (zh) * | 2019-01-31 | 2019-06-11 | 北京集创北方科技股份有限公司 | 指纹检测方法、指纹传感器、指纹检测装置和移动终端 |
FR3111215B1 (fr) * | 2020-06-04 | 2022-08-12 | Linxens Holding | Module de capteur biométrique pour carte à puce et procédé de fabrication d’un tel module |
KR20220008426A (ko) | 2020-07-13 | 2022-01-21 | 삼성전자주식회사 | 지문 인증을 수행하는 전자 장치 및 그것의 동작 방법 |
CN113178139B (zh) * | 2021-04-27 | 2023-08-04 | 上海天马微电子有限公司 | 一种显示面板、制备方法及装置 |
TWI777742B (zh) * | 2021-05-18 | 2022-09-11 | 友達光電股份有限公司 | 指紋辨識裝置 |
KR20230056474A (ko) | 2021-10-20 | 2023-04-27 | 삼성전자주식회사 | 지문 센서 패키지 및 센서 패키지 |
CN114745850A (zh) * | 2022-04-13 | 2022-07-12 | 业成科技(成都)有限公司 | 指纹识别装置和指纹识别装置的制造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030215117A1 (en) * | 2002-05-14 | 2003-11-20 | Canon Kabushiki Kaisha | Fingerprint entering apparatus and method for manufacturing fingerprint entering apparatus |
TW201246410A (en) * | 2011-03-16 | 2012-11-16 | Validity Sensors Inc | Packaging for fingerprint sensors and methods of manufacture |
US20130221452A1 (en) * | 2011-09-15 | 2013-08-29 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus |
KR20150018358A (ko) * | 2013-08-08 | 2015-02-23 | 삼성전자주식회사 | 지문인식장치와 그 제조방법 및 전자기기 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4160851B2 (ja) | 2003-03-31 | 2008-10-08 | 富士通株式会社 | 指紋認識用半導体装置 |
JP4970845B2 (ja) * | 2006-05-16 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | 固体撮像装置 |
KR20110051191A (ko) * | 2008-08-29 | 2011-05-17 | 버티칼 서킷, 인크. | 이미지 센서 |
NO20093601A1 (no) | 2009-12-29 | 2011-06-30 | Idex Asa | Overflatesensor |
US20110175218A1 (en) * | 2010-01-18 | 2011-07-21 | Shiann-Ming Liou | Package assembly having a semiconductor substrate |
WO2011130493A1 (en) * | 2010-04-15 | 2011-10-20 | Authentec, Inc. | Finger sensor including capacitive lens and associated methods |
KR101503183B1 (ko) * | 2010-06-18 | 2015-03-16 | 오쎈테크, 인코포레이티드 | 감지 영역 위에 캡슐화 층을 포함하는 핑거 센서 및 관련 방법 |
US8717775B1 (en) * | 2010-08-02 | 2014-05-06 | Amkor Technology, Inc. | Fingerprint sensor package and method |
US9158958B2 (en) * | 2010-10-28 | 2015-10-13 | Synaptics Incorporated | Signal strength enhancement in a biometric sensor array |
US9147670B2 (en) | 2012-02-24 | 2015-09-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Functional spacer for SIP and methods for forming the same |
KR101356143B1 (ko) * | 2012-05-15 | 2014-01-27 | 크루셜텍 (주) | 지문센서 패키지 및 그 제조방법 |
US8616451B1 (en) * | 2012-06-21 | 2013-12-31 | Authentec, Inc. | Finger sensing device including finger sensing integrated circuit die within a recess in a mounting substrate and related methods |
TWI490455B (zh) * | 2012-10-12 | 2015-07-01 | Morevalued Technology Co Let | 具有高感測靈敏度之電容式感測陣列裝置及使用其之電子設備 |
US9385091B2 (en) * | 2013-03-08 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reinforcement structure and method for controlling warpage of chip mounted on substrate |
WO2015077733A1 (en) * | 2013-11-22 | 2015-05-28 | Shenzhen Huiding Technology Co., Ltd. | Secure human fingerprint sensor |
KR101431566B1 (ko) * | 2014-04-08 | 2014-08-21 | (주)드림텍 | 베젤 내부에 부품 실장이 가능한 지문인식 모듈 제조방법 및 그 지문인식 모듈 |
CN104182738A (zh) * | 2014-08-26 | 2014-12-03 | 南昌欧菲生物识别技术有限公司 | 指纹识别模组及其制造方法 |
CN204044840U (zh) * | 2014-08-26 | 2014-12-24 | 南昌欧菲生物识别技术有限公司 | 指纹识别模组 |
CN204011397U (zh) * | 2014-08-26 | 2014-12-10 | 南昌欧菲生物识别技术有限公司 | 电容式的指纹传感器封装结构 |
CN104201115A (zh) * | 2014-09-12 | 2014-12-10 | 苏州晶方半导体科技股份有限公司 | 晶圆级指纹识别芯片封装结构及封装方法 |
JP6314070B2 (ja) * | 2014-10-07 | 2018-04-18 | 新光電気工業株式会社 | 指紋認識用半導体装置、指紋認識用半導体装置の製造方法及び半導体装置 |
TWI570857B (zh) * | 2014-12-10 | 2017-02-11 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
CN105845635B (zh) * | 2015-01-16 | 2018-12-07 | 恒劲科技股份有限公司 | 电子封装结构 |
TWI594341B (zh) * | 2015-01-19 | 2017-08-01 | 神盾股份有限公司 | 指紋辨識裝置封裝及其製造方法 |
TWI531980B (zh) * | 2015-01-19 | 2016-05-01 | 致伸科技股份有限公司 | 感測裝置之製造方法 |
-
2015
- 2015-05-12 KR KR1020150065900A patent/KR101942141B1/ko active IP Right Grant
-
2016
- 2016-04-18 US US15/131,967 patent/US10297515B2/en active Active
- 2016-05-12 CN CN201620428887.9U patent/CN205984935U/zh active Active
- 2016-05-12 CN CN201911035681.4A patent/CN110739275B/zh active Active
- 2016-05-12 CN CN202210825314.XA patent/CN115117106A/zh active Pending
- 2016-05-12 TW TW111103751A patent/TW202220117A/zh unknown
- 2016-05-12 CN CN201610313065.0A patent/CN106158760A/zh active Pending
- 2016-05-12 TW TW108137857A patent/TWI755640B/zh active
- 2016-05-12 TW TW113109395A patent/TW202427691A/zh unknown
- 2016-05-12 TW TW105114694A patent/TWI711125B/zh active
-
2017
- 2017-05-10 US US15/591,416 patent/US10446455B2/en active Active
-
2019
- 2019-10-15 US US16/601,928 patent/US11393734B2/en active Active
-
2022
- 2022-07-18 US US17/867,287 patent/US11990435B2/en active Active
-
2024
- 2024-05-17 US US18/667,720 patent/US20240304577A1/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030215117A1 (en) * | 2002-05-14 | 2003-11-20 | Canon Kabushiki Kaisha | Fingerprint entering apparatus and method for manufacturing fingerprint entering apparatus |
TW201246410A (en) * | 2011-03-16 | 2012-11-16 | Validity Sensors Inc | Packaging for fingerprint sensors and methods of manufacture |
US20130221452A1 (en) * | 2011-09-15 | 2013-08-29 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus |
KR20150018358A (ko) * | 2013-08-08 | 2015-02-23 | 삼성전자주식회사 | 지문인식장치와 그 제조방법 및 전자기기 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108229340A (zh) * | 2016-12-15 | 2018-06-29 | 指纹卡有限公司 | 指纹感测模块及其制造方法、智能卡及其制造方法 |
US11023702B2 (en) | 2016-12-15 | 2021-06-01 | Fingerprint Cards Ab | Fingerprint sensing module and method for manufacturing the fingerprint sensing module |
US11610429B2 (en) | 2016-12-15 | 2023-03-21 | Fingerprint Cards Anacatum Ip Ab | Fingerprint sensing module and method for manufacturing the fingerprint sensing module |
CN108630623A (zh) * | 2017-03-21 | 2018-10-09 | 矽品精密工业股份有限公司 | 封装结构及其制法 |
US20210307225A1 (en) * | 2018-08-22 | 2021-09-30 | Pragmatic Printing Ltd. | Profiled thermode |
US11910533B2 (en) * | 2018-08-22 | 2024-02-20 | Pragmatic Printing Ltd. | Profiled thermode |
CN112906442A (zh) * | 2019-12-04 | 2021-06-04 | 茂丞科技股份有限公司 | 晶圆级超声波装置及其制造方法 |
CN112906442B (zh) * | 2019-12-04 | 2024-04-30 | 茂丞(郑州)超声科技有限公司 | 晶圆级超声波装置及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20160133187A (ko) | 2016-11-22 |
US20240304577A1 (en) | 2024-09-12 |
TW202005005A (zh) | 2020-01-16 |
CN115117106A (zh) | 2022-09-27 |
TWI711125B (zh) | 2020-11-21 |
US20170243798A1 (en) | 2017-08-24 |
TW202427691A (zh) | 2024-07-01 |
US11393734B2 (en) | 2022-07-19 |
KR101942141B1 (ko) | 2019-01-24 |
US20200219780A1 (en) | 2020-07-09 |
TWI755640B (zh) | 2022-02-21 |
US11990435B2 (en) | 2024-05-21 |
US20230009679A1 (en) | 2023-01-12 |
US10297515B2 (en) | 2019-05-21 |
TW201644013A (zh) | 2016-12-16 |
TW202220117A (zh) | 2022-05-16 |
CN110739275B (zh) | 2024-07-12 |
US20160335470A1 (en) | 2016-11-17 |
CN110739275A (zh) | 2020-01-31 |
US10446455B2 (en) | 2019-10-15 |
CN205984935U (zh) | 2017-02-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106158760A (zh) | 指纹感测器及其制造方法 | |
CN205944070U (zh) | 指纹感测器 | |
CN106449554B (zh) | 带有封闭空腔的芯片嵌入式封装结构及其制作方法 | |
EP1317773B1 (en) | Build-up layer structure on an encapsulated die package having a moisture barrier structure | |
CN105206592B (zh) | 扇出型封装的结构和制作方法 | |
CN108630658A (zh) | 半导体装置及其制造方法 | |
CN107680911A (zh) | 一种指纹识别模组结构及制作方法、终端设备 | |
US8836108B2 (en) | Circuit board structure and package structure | |
CN102347301A (zh) | 芯片封装件积层的系统和方法 | |
CN209276148U (zh) | 一种基于扇出型封装结构的混合封装系统 | |
KR20210072722A (ko) | 전자 장치 및 전자 장치 제조 방법 | |
JP2010171216A (ja) | Memsデバイスパッケージ装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161123 |