CN106062922B - 复合基板 - Google Patents

复合基板 Download PDF

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CN106062922B
CN106062922B CN201580009375.7A CN201580009375A CN106062922B CN 106062922 B CN106062922 B CN 106062922B CN 201580009375 A CN201580009375 A CN 201580009375A CN 106062922 B CN106062922 B CN 106062922B
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silicon
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thin film
base board
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CN106062922A (zh
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川合信
小西繁
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Shin Etsu Chemical Co Ltd
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Abstract

本发明涉及复合基板，是在热导率为5W/m·K以上并且体积电阻率为1×108Ω·cm以上的无机绝缘性烧结体基板11的至少表面具有单晶半导体薄膜13的复合基板，其中，在上述无机绝缘性烧结体基板11和单晶半导体薄膜13之间具有由多晶硅或非晶硅构成的硅被覆层12。根据本发明，即使是在对于可见光为不透明、导热性良好、而且高频区域中的损失小、并且价格低的陶瓷烧结体上设置了单晶硅薄膜的复合基板，也可以抑制来自烧结体的金属杂质污染，使特性提高。

Description

复合基板
技术领域
本发明涉及在导热性高的氮化硅、氮化铝这样的烧结体基板的表面形成了硅薄膜的主要高频用的半导体器件制造用的复合基板。
背景技术
近年来，对于硅系半导体器件，随着设计规则的微细化，其性能日益提高。因此，从各个晶体管、将晶体管之间连接的金属配线的放热成为了问题。为了应对该问题，也出现了在器件的制作后使硅基板的背面变薄到百微米～数百微米左右、在芯片上安装巨大的风扇、促进放热的方案、使水冷管围绕的方案。
但是，实际上即使使硅变薄，制作器件的区域也是从表面到数微米左右的厚度，其以外的区域作为热积存处发挥作用，因此从放热的观点出发，效率变差。另外，近年来，高性能处理器等中使用的SOI晶片等在器件活性层的正下方具有夹持由SiO2构成的绝缘层的结构，但SiO2的热导率低达1.38W/m·k，从放热的观点出发，极成问题。进而，硅基板由于介电特性的关系，在高频区域中的损失大，其使用存在限度。
另外，由于导热性良好并且高频区域中的损失小，因此使用了蓝宝石基板的蓝宝石上硅(SOS)受到了关注，但存在以下的问题。即，蓝宝石基板由于在可见光区域中为透明，因此存在在器件制造工艺中对于在基板的有无确认、晶片的位置确定中使用的光传感器无反应的问题。另外，存在蓝宝石基板的成本高的问题。进而，也存在与硅的热膨胀率差也大，复合基板的热处理、成膜时容易发生翘曲、难以大口径化的问题。
另外，作为对于可见光为不透明、导热性良好、并且价格低的基板，可以列举出氮化硅、氮化铝等的陶瓷烧结体。但是，由于这些是用烧结助剂使氮化硅、氮化铝的粉末坚固的产物，因此粉末中所含的Fe、Al等金属杂质、或者氧化铝等烧结助剂自身成为器件制造工艺中的污染原因，存在其使用困难的问题。
应予说明，作为与本发明关联的现有技术，可列举出国际公开第2013/094665号(专利文献1)。
现有技术文献
专利文献
专利文献1：国际公开第2013/094665号
发明内容
发明要解决的课题
本发明鉴于上述实际情况而完成，其目的在于提供复合基板，其为在对于可见光为不透明、导热性良好、进而高频区域中的损失小、并且价格低的陶瓷烧结体上设置了单晶硅薄膜的复合基板，可以抑制来自烧结体的金属杂质污染，使特性提高。
用于解决课题的手段
本发明人发现了：通过在热导率为5W/m·K以上并且体积电阻率为1×108Ω·cm以上的无机绝缘性烧结体基板的至少表面具有单晶半导体薄膜的复合基板中使用在上述无机绝缘性烧结体基板与单晶半导体薄膜之间介入有由多晶硅或非晶硅构成的硅被覆层的复合基板，从而有效地实现上述目的。
即，本发明提供下述的复合基板。
[1]复合基板，是在热导率为5W/m·K以上并且体积电阻率为1×108Ω·cm以上的无机绝缘性烧结体基板的至少表面具有单晶半导体薄膜的复合基板，其特征在于，在上述无机绝缘性烧结体基板与单晶半导体薄膜之间具有由多晶硅或非晶硅构成的硅被覆层。
[2][1]所述的复合基板，其特征在于，上述硅被覆层覆盖了上述无机绝缘性烧结体基板的整体。
[3][1]或[2]所述的复合基板，其特征在于，上述硅被覆层为采用溅射法、电子束蒸镀法、化学气相生长法或外延生长法形成的高纯度硅层。
[4][1]～[3]的任一项所述的复合基板，其特征在于，上述无机绝缘性烧结体基板以氮化硅、氮化铝或SIALON作为主成分。
[5][1]～[4]的任一项所述的复合基板，其特征在于，上述单晶半导体薄膜为单晶硅。
[6][1]～[5]的任一项所述的复合基板，其特征在于，在上述无机绝缘性烧结体基板与硅被覆层之间还具有采用化学气相生长法形成的氮化硅被覆层。
[7][1]～[6]的任一项所述的复合基板，其特征在于，在上述硅被覆层与单晶半导体薄膜之间具有至少一层由选自氧化硅、氮化硅、氮化铝和SIALON中的材料构成的中间绝缘层。
发明的效果
根据本发明，使用对可见光为不透明、导热性良好、而且高频区域中的损失小、价格低的无机绝缘性烧结体，能够提供金属杂质污染得到了抑制的价格低的复合基板。
附图说明
图1为表示本发明涉及的复合基板的构成例的剖面图。
具体实施方式
以下对本发明涉及的复合基板的一实施方式中的构成进行说明。
本发明涉及的复合基板是在热导率为5W/m·K以上并且体积电阻率为1×108Ω·cm以上的无机绝缘性烧结体基板的至少表面具有单晶半导体薄膜的复合基板，其特征在于，在上述无机绝缘性烧结体基板与单晶半导体薄膜之间具有由多晶硅或非晶硅构成的硅被覆层。
其中，作为基板使用的无机绝缘性烧结体，其热导率优选比SiO2的热导率1.5W/m·k高，更优选为5W/m·k以上，进一步优选为10W/m·k以上。对其上限并无特别限制，通常为2,500W/m·K以下，特别地为2,000W/m·K以下。
另外，为了抑制介电特性引起的电力损失，希望基板的体积电阻率尽可能高，优选至少为1×108Ω·cm以上，更优选为1×1010Ω·cm以上。对其上限并无特别限制，通常为1×1018Ω·cm以下，特别地为1×1016Ω·cm以下。
作为满足这些条件的无机绝缘性烧结体，可以列举出以氮化硅、氮化铝、赛隆(SIALON：Si3N4·Al2O3)等作为主成分的烧结体。其中，从器件制造工艺中使用的药液耐性高，而且基板成本低出发，最优选氮化硅。应予说明，所谓“主成分”，意味着以氮化硅、氮化铝、SIALON作为主原料，这以外还包含烧结助剂等副原料，包含优选地全体的50质量％以上、更优选地80质量％以上、特别优选地90质量％以上的氮化硅、氮化铝或SIALON。
再有，上述基板的厚度优选设为100～2,000μm，特别优选设为200～1,000μm。
有时在上述烧结体中大量含有Fe、Al等金属元素、特别是Al，由于它们在器件制造工艺中溶出或扩散等，有可能产生不良影响。
这种情况下，采用ICP-MS法(电感耦合等离子体质谱分析法)评价基板中的杂质浓度时，Fe为1×1017原子/cm3以下、Al为1×1017原子/cm3以下的情形下，能够在基板表面直接形成单晶半导体膜，但在Fe超过上述浓度且1×1020原子/cm3以下，Al超过上述浓度且1×1020原子/cm3以下的情形下，为了防止这些杂质的溶出，优选用由多晶硅或非晶硅构成的硅被覆层覆盖基板整体。当然，在Fe为1×1017原子/cm3以下，Al为1×1017原子/cm3以下的情形下，也推荐形成上述硅被覆层。通过经由上述硅被覆层设置形成元件的单晶半导体膜、具体地单晶硅膜，能够得到所期望的复合基板。再有，上述硅被覆层优选不仅在基板的表面，而且在背面和侧面也设置而将基板整体覆盖。
上述硅被覆层的目的是防止基板中的金属杂质的溶出或扩散，该硅被覆层必须为高纯度。为了实现这点，作为设置硅被覆层的手段，优选采用溅射法、电子束蒸镀法、化学气相生长法或外延生长法。通过采用这样的手段，能够使硅被覆层的膜中的Al和Fe的各自的浓度为烧结体中的浓度以下、典型地1×1017原子/cm3以下、优选地1×1016原子/cm3以下、更优选地1×1015原子/cm3以下，能够抑制来自基板的金属杂质污染。构成硅被覆层的多晶硅、非晶硅是一般经常使用的膜，因此可以低价且容易地形成。
另外，利用硅被覆层，在单晶半导体薄膜与基板之间容易获得良好的密合性，或者设置后述的中间绝缘层的情况下在隔着该中间绝缘层的单晶半导体薄膜与基板之间容易获得良好的密合性。
再有，硅被覆层的厚度优选设为0.01～50μm，特别优选设为0.1～20μm。如果厚度不到0.01μm，抑制来自基板的金属杂质污染有可能变得困难，如果超过50μm，有时在成本方面变得不利。
作为隔着上述硅被覆层形成的单晶半导体薄膜，如果制成单晶硅膜，则可以在通常的使用块体的硅基板的CMOS工序中形成器件而优选。另外，作为单晶半导体薄膜的厚度，通常优选设为0.01～100μm，特别优选设为0.05～1μm。这种情况下，作为单晶半导体薄膜的形成方法，可列举下述的方法等：将智能切割法那样的将氢、稀有气体离子进行了离子注入的单晶半导体基板贴合后，从进行了离子注入的层剥离并转印的方法(将该方法称为贴合法)；将Si、SOI等的半导体层接合后，采用机械的和/或化学的手段进行薄化。
另外，如果用采用化学气相生长法形成的氮化硅被覆上述无机绝缘性烧结体基板，在其上设置硅被覆层，则能够进一步地抑制金属杂质污染。
该氮化硅的被覆层的厚度优选设为0.01～50μm，特别优选设为0.1～20μm。
如果在上述硅被覆层与单晶半导体薄膜之间进一步设置至少一层由选自氧化硅、氮化硅、氮化铝和SIALON中的材料制成的中间绝缘层，则将硅被覆层与单晶半导体薄膜之间绝缘，制作的器件特性变得良好，因此更为优选。应予说明，作为设置中间绝缘层的手段，优选采用溅射、电子束蒸镀或化学气相生长法。另外，该中间绝缘层的厚度优选设为0.01～50μm，特别优选设为0.1～20μm。
作为这种情形的复合基板的制造步骤，可在上述硅被覆层上形成了该中间绝缘层后，采用上述贴合法形成单晶半导体薄膜。此时，将基板整个面被覆的硅被覆层整个面用中间绝缘层进一步被覆为宜。或者，作为复合基板的另外的制造步骤，可以在贴合法中的单晶半导体基板的表面形成该中间绝缘层，进行了离子注入后，进行贴合以使中间绝缘层与硅被覆层相接，从进行了离子注入的层剥离，进行转印。此时，中间绝缘层只在硅被覆层与单晶半导体薄膜之间作为夹层存在。
本发明的复合基板主要用于放热大的功率器件、使用高频的RF器件等。
实施例
以下列举实施例和比较例，对本发明更具体地说明，但本发明并不限定于下述的实施例。
[实施例1]
将本实施例中制作的复合基板的构成示于图1。
首先，作为无机绝缘性烧结体基板11，制作了外径200mm、厚725μm的Si3N4烧结体。采用4端针法测定了该基板的体积电阻率，结果为1×1014Ω·cm。另外，采用激光闪光法测定了基板的热导率，结果为15W/m·k。
在该基板11的整个面采用CVD法形成了厚2μm的多晶硅膜作为硅被覆层12。该硅被覆层12的膜中所含的金属杂质浓度通过连同形成了硅被覆层12的基板11一起在HF水溶液中浸渍，将硅被覆层12的自然氧化膜溶解于HF水溶液，采用ICM-MS法进行分析而进行。其结果，硅被覆层中的金属杂质的Fe最多，为1.2×1015原子/cm3。其次多的金属杂质为Al，其浓度为1.0×1014原子/cm3。其他金属杂质为检测极限(7×1013原子/cm3)以下，是在器件制造工艺中没有问题的浓度。
接下来，在该基板的一面的硅被覆层12上采用贴合法作成了厚0.3μm的单晶硅薄膜作为单晶半导体薄膜13。
如以上那样，使用热导率高、价格低的烧结体基板，能够制作金属污染的担心小的复合基板。
[实施例2]
将本实施例中制作的复合基板的构成示于图1。
首先，作为无机绝缘性烧结体基板11，制作了外径150mm、厚625μm的Si3N4烧结体。采用4端针法测定了该基板的体积电阻率，结果为1×1014Ω·cm。另外，采用激光闪光法测定了基板的热导率，结果为50W/m·k。
在该基板11的整个面采用溅射法形成了厚1μm的非晶硅膜作为硅被覆层12。该硅被覆层12的膜中所含的金属杂质浓度通过连同形成了硅被覆层12的基板11一起在HF水溶液中浸渍，将硅被覆层12的自然氧化膜溶解于HF水溶液，采用ICM-MS法进行分析而进行。其结果，硅被覆层中的金属杂质的Fe最多，为1.5×1015原子/cm3。其次多的金属杂质为Al，其浓度为1.5×1014原子/cm3。其他金属杂质为检测极限(7×1013原子/cm3)以下，是在器件制造工艺中没有问题的浓度。
接下来，在该基板的一面的硅被覆层12上采用贴合法作成了厚0.3μm的单晶硅薄膜作为单晶半导体薄膜13。
如以上那样，使用热导率高、价格低的烧结体基板，能够制作金属污染的担心小的复合基板。
[实施例3]
本实施例中制作的复合基板，是对于图1中所示的复合基板进一步在硅被覆层12与单晶半导体薄膜13之间形成了中间绝缘层的产物。
首先，作为无机绝缘性烧结体基板11，制作了外径200mm、厚725μm的Si3N4烧结体。采用4端针法测定了该基板的体积电阻率，结果为1×1014Ω·cm。另外，采用激光闪光法测定了基板的热导率，结果为15W/m·k。
在该基板11的整个面采用溅射法形成了厚1μm的非晶硅膜作为硅被覆层12。该硅被覆层12的膜中所含的金属杂质浓度通过连同形成了硅被覆层12的基板11一起在HF水溶液中浸渍，将硅被覆层12的自然氧化膜溶解于HF水溶液，采用ICM-MS法进行分析而进行。其结果，硅被覆层中的金属杂质的Fe最多，为1.5×1015原子/cm3。其次多的金属杂质为Al，其浓度为1.5×1014原子/cm3。其他金属杂质为检测极限(7×1013原子/cm3)以下，是在器件制造工艺中没有问题的浓度。
接下来，在该基板整个面的硅被覆层12上采用化学气相生长法(CVD法)形成了厚2μm的氧化硅膜作为中间绝缘层。该氧化硅膜中所含的金属杂质浓度通过将该膜溶解于HF水溶液，采用ICM-MS法进行分析而进行。其结果，膜中的金属杂质为检测极限(7×1013原子/cm3)以下，是在器件制造工艺中没有问题的浓度。
最后，在该基板的一面的中间绝缘层上采用贴合法制作厚0.3μm的单晶硅薄膜作为单晶半导体薄膜13。
如以上那样，使用热导率高、价格低的烧结体基板，能够制作金属污染的担心小的复合基板。
[比较例1]
制作了体积电阻率和热导率与实施例1相同的Si3N4烧结体基板。将该基板浸渍于HF水溶液中溶解，采用ICP-MS法评价了金属杂质浓度，结果Fe为1×1019原子/cm3，Al为5×1018原子/cm3，与实施例1的硅被覆层中的金属杂质浓度相比显著地高。虽然体积电阻率、热导率没有问题，但在器件制造工艺中使用时为制造线的污染成为问题的浓度水平，如果是这样的形态就不能使用。
应予说明，目前为止用附图中所示的实施方式对本发明进行了说明，但本发明并不限定于附图中所示的实施方式，其他的实施方式、追加、改变、删除等可以在本领域技术人员能够想到的范围内进行改变，只要所有的方案都产生本发明的作用效果，则都包含在本发明的范围内。
附图标记的说明
11 无机绝缘性烧结体基板
12 硅被覆层
13 单晶半导体薄膜

Claims (7)

1.复合基板，是在热导率为5W/m·K以上并且体积电阻率为1×108Ω·cm以上的无机绝缘性烧结体基板的至少表面具有单晶半导体薄膜的复合基板，其特征在于，具有位于上述无机绝缘性烧结体基板与单晶半导体薄膜之间且由多晶硅或非晶硅构成的硅被覆层，上述硅被覆层覆盖了该无机绝缘性烧结体基板的整体，
具有至少一层位于上述硅被覆层与单晶半导体薄膜之间且由选自氧化硅、氮化硅、氮化铝和SIALON中的材料构成的中间绝缘层，上述中间绝缘层进一步被覆覆盖了上述无机绝缘性烧结体基板整体的硅被覆层整个面。
2.根据权利要求1所述的复合基板，其特征在于，上述硅被覆层中的Al和Fe各自的浓度为1×1017原子/cm3以下。
3.根据权利要求1或2所述的复合基板，其特征在于，上述硅被覆层为采用溅射法、电子束蒸镀法、化学气相生长法或外延生长法形成的高纯度硅层。
4.根据权利要求1或2所述的复合基板，其特征在于，上述无机绝缘性烧结体基板以氮化硅、氮化铝或SIALON作为主成分。
5.根据权利要求1或2所述的复合基板，其特征在于，上述单晶半导体薄膜为单晶硅。
6.根据权利要求1或2所述的复合基板，其特征在于，在上述无机绝缘性烧结体基板与硅被覆层之间还具有采用化学气相生长法形成的氮化硅被覆层。
7.根据权利要求1或2所述的复合基板，其特征在于，上述硅被覆层的厚度是0.1～20μm，上述中间绝缘层的厚度是0.1～20μm。
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EP3109893B1 (en) 2022-09-28
EP3109893A1 (en) 2016-12-28
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