WO2024083267A1 - 半导体结构的制备方法、半导体结构及电子设备 - Google Patents

半导体结构的制备方法、半导体结构及电子设备 Download PDF

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Publication number
WO2024083267A1
WO2024083267A1 PCT/CN2023/136920 CN2023136920W WO2024083267A1 WO 2024083267 A1 WO2024083267 A1 WO 2024083267A1 CN 2023136920 W CN2023136920 W CN 2023136920W WO 2024083267 A1 WO2024083267 A1 WO 2024083267A1
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silicon layer
single crystal
layer
doped single
crystal silicon
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PCT/CN2023/136920
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English (en)
French (fr)
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庞慰
杨清瑞
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广州乐仪投资有限公司
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Publication of WO2024083267A1 publication Critical patent/WO2024083267A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details

Definitions

  • the present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure and an electronic device.
  • silicon-based piezoelectric resonators are mostly made of Cavity Silicon-on-Insulator (CSOI) substrates with pre-set cavities.
  • CSOI Cavity Silicon-on-Insulator
  • the preparation method of CSOI substrate is: after the silicon wafer or SOI silicon wafer used as the device layer is thermally oxidized, it is bonded to the silicon substrate in which the cavity has been etched, or the thermal oxidation layer can also be grown on the substrate on one side of the cavity, and then bonded to the silicon wafer or SOI silicon wafer used as the device layer, and then the silicon wafer or SOI is thinned by mechanical grinding, chemical mechanical polishing technology, wet etching, dry etching and other methods, and finally a thinner silicon device layer is left, thereby making a CSOI silicon wafer.
  • the initial characteristics of the device silicon layer (device layer) in the silicon wafer or SOI silicon wafer determine the characteristics of the CSOI device layer, especially its doping concentration will determine the final frequency-temperature characteristics of the silicon-based piezoelectric resonator.
  • the silicon layer of the device in the silicon wafer or SOI silicon wafer is mostly manufactured by the direct pull method, and the precision of the doping concentration and the uniformity between wafers and batches are poor, especially when the doping concentration is close to or greater than 10 19 cm -3 , the precision and uniformity will be worse, and at this time the temperature coefficient is more sensitive to the doping concentration.
  • the piezoelectric silicon-based resonator manufactured by the above CSOI has poor consistency in the frequency temperature coefficient within the wafer, between wafers, within batches, and between batches, resulting in low device yield and high cost.
  • the doping concentration of the silicon wafer manufactured by this direct pull method is usually difficult to reach more than 10 20 cm -3 , which limits the available range of the frequency temperature coefficient of silicon. For some modes of piezoelectric driven silicon-based resonators, it is not easy to achieve their zero temperature drift characteristics.
  • the embodiments of the present application provide a method for preparing a semiconductor structure, a semiconductor structure and an electronic device to solve the technical problems of poor performance consistency (especially poor consistency of frequency-temperature characteristics) and low yield of the semiconductor structure.
  • the performance consistency of the semiconductor structure can be improved, thereby improving the yield of the semiconductor structure and reducing the cost of the device.
  • the available doping concentration range of the silicon layer in the semiconductor structure and the corresponding obtainable frequency temperature coefficient range can be increased.
  • a first aspect of an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:
  • the doped single crystal silicon layer is bonded to the first bottom silicon layer;
  • At least a portion of the substrate is removed to form a thin film silicon layer on the first bottom silicon layer; wherein the thin film silicon layer includes at least a portion of the thickness of the doped single crystal silicon layer.
  • the step of forming a heavily doped single crystal silicon layer on the substrate by epitaxial growth specifically includes:
  • the doped single crystal silicon layer having a doping concentration varying with the growth thickness is formed on the substrate.
  • the doped single crystal silicon layer has at least two sub-doped single crystal silicon layers stacked along a growth thickness direction, and different sub-doped single crystal silicon layers have different doping concentrations and/or different dopants.
  • the doping concentration of each of the sub-doped single crystal silicon layers is arranged in sequence from large to small or from small to large along the growth thickness direction.
  • the doping concentration of the doped single crystal silicon layer varies continuously with the growth thickness.
  • the doping concentration of the doped single crystal silicon layer is greater than the doping concentration of the substrate, and the doped single crystal silicon layer is an N-type heavily doped single crystal silicon layer or a P-type heavily doped single crystal silicon layer; wherein the doping concentration of the doped single crystal silicon layer is greater than or equal to 10 19 cm -3 .
  • the doping concentration of the doped single crystal silicon layer is greater than or equal to 10 20 cm ⁇ 3 .
  • the process further includes:
  • a thermal oxide layer is formed on at least one of the doped single crystal silicon layer and the first bottom silicon layer.
  • the substrate includes a first top silicon layer, and the doped single crystal silicon layer is formed on a surface of the first top silicon layer.
  • removing at least a portion of the substrate specifically includes: thinning the thickness of the first top silicon layer; or removing the first top silicon layer.
  • the forming of a heavily doped single crystal silicon layer on a substrate by epitaxial growth specifically includes:
  • the heavily doped doped single crystal silicon layer is epitaxially grown on the second top silicon layer of the SOI substrate.
  • removing at least a portion of the substrate specifically includes:
  • the second bottom silicon layer and the buried oxide layer are removed in sequence; or, the second bottom silicon layer, the buried oxide layer and at least a portion of the second top silicon layer are removed in sequence.
  • removing at least a portion of the substrate specifically includes:
  • the entire substrate and a portion of the doped single crystal silicon layer are removed.
  • the method further includes:
  • the doped single crystal silicon layer or thin film silicon layer is doped by ion implantation or thermal diffusion; and/or,
  • the doped single crystal silicon layer or thin film silicon layer is subjected to high temperature annealing.
  • the doped single crystal silicon layer or the thin film silicon layer is doped by ion implantation or thermal diffusion, or the doped single crystal silicon layer or the thin film silicon layer is subjected to high-temperature annealing to increase the doping concentration of the doped single crystal silicon layer or the thin film silicon layer; if the doping concentration of the doped single crystal silicon layer or the thin film silicon layer is greater than the preset doping concentration, the doped single crystal silicon layer or the thin film silicon layer is subjected to high-temperature annealing to reduce the doping concentration of the doped single crystal silicon layer or the thin film silicon layer.
  • the method further includes:
  • a piezoelectric resonator layer is formed on a surface of the thin film silicon layer.
  • the method further includes:
  • An upper silicon cap is bonded to the piezoelectric resonator layer.
  • a second aspect of an embodiment of the present application provides a semiconductor structure, including:
  • a thin film silicon layer is formed on the surface of the first bottom silicon layer by bonding, and the thin film silicon layer at least includes a doped single crystal silicon layer partially formed by epitaxial growth, and the doped single crystal silicon layer is located in the thin film silicon layer close to the first bottom silicon layer, and the doped single crystal silicon layer is a heavily doped layer.
  • the doped single crystal silicon layer is an N-type heavily doped single crystal silicon layer or a P-type heavily doped single crystal silicon layer; and the doping concentration of the doped single crystal silicon layer is greater than or equal to 10 19 cm -3 .
  • the doping concentration of the doped single crystal silicon layer varies with the growth thickness.
  • the doped single crystal silicon layer has at least two sub-doped single crystal silicon layers stacked along a growth thickness direction, and different sub-doped single crystal silicon layers have different doping concentrations and/or different dopants.
  • the doping concentration of each of the sub-doped single crystal silicon layers is arranged in sequence from large to small or from small to large along the growth thickness direction.
  • the doping concentration of the doped single crystal silicon layer varies continuously with the growth thickness.
  • a thermal oxide layer is further included, and the thermal oxide layer is disposed between the first bottom silicon layer and the doped single crystal silicon layer.
  • the thermal oxide layer covers a cavity wall on one side of the cavity opposite to the doped single crystal silicon layer.
  • the thermal oxide layer covers a surface of one side of the doped single crystal silicon layer corresponding to the cavity.
  • the thermal oxide layer covers a cavity wall of the cavity and a surface of one side of the doped single crystal silicon layer corresponding to the cavity.
  • the method further comprises:
  • a piezoelectric resonator layer is formed on the surface of the thin film silicon layer
  • An upper silicon cap is bonded to the piezoelectric resonator layer.
  • the piezoelectric resonator layer includes a piezoelectric layer and a top electrode stacked in sequence on the surface of the thin film silicon layer.
  • the piezoelectric resonator further includes a bottom electrode.
  • the piezoelectric layer is disposed on a side away from the top electrode.
  • a dielectric layer is disposed between the bottom electrode and the thin film silicon layer, and the dielectric layer is at least one of silicon dioxide, silicon nitride, aluminum oxide, and aluminum nitride.
  • the piezoelectric layer is any one of single crystal aluminum nitride, polycrystalline aluminum nitride, and rare earth element doped aluminum nitride; wherein the rare earth element doped aluminum nitride includes at least one of scandium, yttrium, magnesium, titanium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.
  • a first bonding layer is provided between the upper silicon cap and the piezoelectric layer.
  • the upper silicon cap includes a substrate and a second bonding layer, and the second bonding layer is arranged on a side of the substrate facing the first bonding layer;
  • the substrate is also provided with a conductive through hole penetrating the substrate and the second bonding layer, a metal pin electrically connected to the conductive through hole is provided on the side of the upper silicon cap away from the second bonding layer, and a getter layer is also provided on the side of the substrate facing the piezoelectric resonator layer.
  • both the first bonding layer and the second bonding layer are metal layers.
  • a silicon dioxide layer is disposed between the metal pin, the conductive through hole, and the substrate.
  • a third aspect of the embodiments of the present application provides an electronic device, comprising the semiconductor structure provided by the above embodiments.
  • the method for preparing a semiconductor structure includes: forming a heavily doped doped single crystal silicon layer on a substrate by epitaxial growth; forming a cavity on a first bottom silicon layer; bonding the doped single crystal silicon layer to the first bottom silicon layer after flipping the substrate; removing at least part of the substrate to form a thin film silicon layer on the first bottom silicon layer; wherein the thin film silicon layer includes at least a part of the thickness of the doped single crystal silicon layer.
  • a heavily doped doped single crystal silicon layer is formed on a substrate by epitaxial growth, so that the doping concentration of the silicon layer in the semiconductor structure can be increased, and the doping concentration is adjustable and controllable, thereby improving the performance consistency and yield of the semiconductor structure.
  • FIG1 is a schematic diagram of a process for preparing a semiconductor structure according to an embodiment of the present application.
  • FIG2 is a cross-sectional schematic diagram of forming a doped single crystal silicon layer on a substrate in one embodiment of the present application
  • FIG3 is a cross-sectional schematic diagram of forming a cavity on the first bottom silicon layer in one embodiment of the present application
  • FIG4 is a cross-sectional schematic diagram of forming a thermal oxide layer on a doped single crystal silicon layer in one embodiment of the present application
  • FIG5 is a cross-sectional schematic diagram of forming a thermal oxide layer on the first bottom silicon layer in one embodiment of the present application
  • FIG6 is a cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG7 a is a cross-sectional schematic diagram of another structure of a semiconductor structure provided by an embodiment of the present application.
  • FIG7 b is a cross-sectional schematic diagram of another structure of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 8 is a cross-sectional schematic diagram of a doped single crystal silicon layer and a first bottom silicon layer having a thermal oxide layer formed thereon in one embodiment of the present application;
  • FIG9 is a cross-sectional schematic diagram of FIG1 after flipping and bonding with FIG5;
  • FIG10 is a cross-sectional schematic diagram of FIG9 after a portion of the substrate is removed;
  • FIG11 is a cross-sectional schematic diagram of FIG9 after all substrates are removed.
  • FIG12 is a cross-sectional schematic diagram of the doped single crystal silicon layer in FIG11 grown according to a gradient doping concentration
  • FIG13 is a cross-sectional schematic diagram of the doping concentration of the doped single crystal silicon layer in FIG11 being continuously varied and grown;
  • FIG14 is a cross-sectional view showing a piezoelectric resonator layer formed on FIG11;
  • FIG15a is a cross-sectional schematic diagram of a structure in which a silicon cap is packaged on FIG14;
  • FIG15 b is a cross-sectional schematic diagram of another structure in which a silicon cap is packaged on FIG14 ;
  • FIG16 is a schematic top view of a structure of a tuning fork in a vibration mode in a semiconductor device provided in an embodiment of the present application;
  • FIG17 is a schematic top view of another structure of a tuning fork in a vibration mode in a semiconductor device provided by an embodiment of the present application;
  • FIG18 is a cross-sectional schematic diagram of forming a doped single crystal silicon layer on an SOI substrate in another embodiment of the present application.
  • FIG19 is a schematic cross-sectional structure diagram of a thermal oxygen layer formed on the basis of FIG18;
  • FIG20 is a cross-sectional schematic diagram of forming a thermal oxide layer only on a doped single crystal silicon layer in another embodiment of the present application.
  • 21 is a cross-sectional schematic diagram of forming a thermal oxide layer on both the doped single crystal silicon layer and the first bottom silicon layer in another embodiment of the present application;
  • FIG22 is a cross-sectional schematic diagram of another embodiment of the present application in which a thermal oxide layer is formed only on the first bottom silicon layer;
  • FIG23 is a cross-sectional schematic diagram of another embodiment of the present application after the second top silicon layer in the SOI substrate is removed;
  • FIG24 is a cross-sectional schematic diagram of another embodiment of the present application after removing the buried oxide layer in the SOI substrate;
  • FIG. 25 is a schematic cross-sectional view of another embodiment of the present application after the second bottom silicon layer in the SOI substrate is removed.
  • 600-first bonding layer 700-upper silicon cap; 701-substrate;
  • 702-second bonding layer 703-metal pin; 704-conductive via;
  • the silicon wafer used as the device layer or the silicon layer of the SOI device is usually manufactured by the Czochralski method.
  • the doping concentration is close to 1x10 19 cm -3 , the control accuracy of the doping concentration is poor, which makes the performance consistency between silicon wafers and batches worse, and further leads to technical problems such as poor performance consistency of the manufactured devices (especially the consistency of frequency-temperature characteristics) and low yield.
  • the doping concentration of silicon wafers manufactured by this Czochralski method is usually difficult to control. Reaching above 10 20 cm -3 , thus limiting the frequency temperature coefficient range of silicon, it is not easy to achieve the zero temperature drift characteristic for some modes of piezoelectrically driven silicon-based resonators.
  • the embodiments of the present application provide a method for preparing a semiconductor structure, a semiconductor structure and an electronic device, wherein in the method for preparing a semiconductor structure, a heavily doped single crystal silicon layer is formed on a substrate by epitaxial growth, and its doping concentration is easily controlled to reach 10 19 cm -3 or even 10 20 cm -3 or more, and the precision of its doping concentration can be better controlled.
  • a device silicon layer with high-concentration doping and adjustable and controllable doping concentration can be achieved, thereby improving the final frequency-temperature characteristics of the semiconductor structure, as well as the consistency and yield of the frequency-temperature characteristics within a chip, between chips, within a batch, and between batches.
  • the semiconductor structure provided in the embodiments of the present application may be a resonator, a transducer, a driver, etc.
  • the semiconductor structure is introduced as a resonator (eg, a piezoelectrically driven silicon-based resonator) as an example.
  • FIG1 is a schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application.
  • an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:
  • Step S101 forming a heavily doped single crystal silicon layer on a substrate by epitaxial growth.
  • the substrate 101 before forming a heavily doped single crystal silicon layer 200 on the substrate 101 by epitaxial growth, it also includes: providing a substrate 101.
  • the substrate 101 can provide a supporting basis for the structural layer on the substrate 101.
  • the substrate 101 can be made of a crystalline semiconductor material, for example, the substrate 101 can be a silicon (Si) substrate, the substrate 101 can also be a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, etc., wherein the substrate 101 can be a single-layer structure or a multi-layer composite structure, and the specific adaptive design is carried out according to actual needs, and no specific limitation is made here.
  • the substrate 101 is taken as a single crystal silicon as an example for introduction.
  • the heavily doped single crystal silicon layer 200 is formed by epitaxial growth. On the substrate 101. It is understood that while the single crystal silicon layer is grown by epitaxial growth on the substrate 101, the silicon layer is doped into the epitaxially grown silicon layer.
  • the doping element of the doped single crystal silicon layer 200 may be B, As or P, etc.; the doping type formed may be N-type or P-type (the dopant of the P-type doping is generally boron, or may be a group III element such as aluminum, gallium, indium, etc.; the dopant of the N-type doping is generally a group V element such as phosphorus or arsenic).
  • an N-type (doping agent is phosphorus) heavily doped (doping concentration is greater than 10 19 cm -3 ) doped single crystal silicon layer 200 is grown on the surface of the substrate 101.
  • the doping concentration of the doped single crystal silicon layer is greater than the doping concentration of the substrate.
  • the doping concentration can be further increased by ion implantation or thermal diffusion, or the distribution characteristics of the dopant in the silicon layer can be changed by high temperature annealing (about 1000° C.).
  • Step S102 forming a cavity on the first bottom silicon layer.
  • the first bottom silicon layer 102 provides a supporting foundation for the structural layer on the first bottom silicon layer 102;
  • the first bottom silicon layer 102 can be made of crystalline semiconductor material, for example, the material of the first bottom silicon layer 102 can be silicon (Si), single crystal silicon, silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI for short), gallium arsenide, gallium nitride, etc.
  • the material of the first bottom silicon layer 102 is single crystal silicon.
  • a cavity is formed on the first bottom silicon layer 102, wherein the cavity may be a recessed structure with an opening formed on the surface of the first bottom silicon layer 102, as shown in FIG. 3, and the cavity on the first bottom silicon layer 102 may be formed by a process such as dry etching or wet etching.
  • the depth of the cavity etched on the surface of the first bottom silicon layer 102 may be between several micrometers and hundreds of micrometers, for example: 5 ⁇ m, 50 ⁇ m, 100 ⁇ m, etc., wherein the specific depth of the cavity may be adaptively designed according to the actual requirements of the semiconductor structure, and no specific limitation is made herein.
  • the method further includes:
  • a thermal oxide layer is formed on at least one of the doped single crystal silicon layer 200 and the first bottom silicon layer 102. It is understood that the thermal oxide layer 301 can be grown on the surface of the doped single crystal silicon layer 200 facing away from the substrate 101, as shown in FIG4. By growing the thermal oxide layer 301 on the surface of the doped single crystal silicon layer 200, the single crystal silicon of the doped single crystal silicon layer 200 can have a positive temperature coefficient, thereby having a temperature compensation effect on the doped single crystal silicon layer 200; of course, the thermal oxide layer 302 can also be grown on the side of the first bottom silicon layer 102 having a cavity, as shown in FIG5. In this way, the thermal oxide layer 302 can be As an adhesion layer, the first bottom silicon layer 102 and the substrate 101 have good adhesion in the subsequent bonding process.
  • the material of the thermal oxide layer can be silicon dioxide (SiO 2 ).
  • Step S103 after turning the substrate upside down, the doped single crystal silicon layer is bonded to the first bottom silicon layer.
  • the doped single crystal silicon layer 200 may be directly bonded to the first bottom silicon layer 102 ;
  • the substrate 101 is flipped onto the first bottom silicon layer 102 and bonded to the first bottom silicon layer 102 .
  • the thermal oxide layer 301 is grown only on the surface of the doped single crystal silicon layer 200, and no thermal oxide layer is formed on the surface of the first bottom silicon layer 102.
  • the substrate 101 is flipped on the first bottom silicon layer 102 and bonded to the first bottom silicon layer 102.
  • the thermal oxide layer 301 on the surface of the doped single crystal silicon layer 200 not only improves the adhesion between the doped single crystal silicon layer 200 and the first bottom silicon layer 102, but also has a temperature compensation effect on the doped single crystal silicon layer 200, so that the temperature coefficient of silicon in the doped single crystal silicon layer 200 is positive.
  • a silicon dioxide layer is grown on the surface of the doped single crystal silicon layer 200 and patterned so that its edge falls into the cavity of the first bottom silicon layer 102 . At this time, the bonding between the two prepared substrates is still achieved through silicon-silicon bonding.
  • a thermal oxide layer is grown on the surface of the doped single crystal silicon layer 200 and the first bottom silicon layer 102. After the thermal oxide layer is formed, the substrate 101 is flipped onto the first bottom silicon layer 102 and bonded to the first bottom silicon layer 102. In this way, the thermal oxide layer not only improves the adhesion between the doped single crystal silicon layer 200 and the first bottom silicon layer 102, but also has a temperature compensation effect on the doped single crystal silicon layer 200, so that the temperature coefficient of silicon in the doped single crystal silicon layer 200 is positive.
  • the thermal oxide layer 302 is only formed on the first bottom silicon layer 102, and no thermal oxide layer is formed on the doped single crystal silicon layer 200. Then, the substrate 101 is flipped on the first bottom silicon layer 102 and bonded to the first bottom silicon layer 102. In this way, the thermal oxide layer 302 can improve the adhesion between the first bottom silicon layer 102 and the doped single crystal silicon layer 200.
  • the cavity on the first bottom silicon layer 102 is an open cavity, and when the substrate 101 is flipped and bonded to the first bottom silicon layer 102, the substrate 101 blocks the opening of the cavity so that a closed cavity is formed between the substrate 101 and the first bottom silicon layer 102.
  • Step S104 removing at least a portion of the substrate to form a thin film silicon layer on the first bottom silicon layer;
  • the thin film silicon layer includes at least a portion of the thickness of the doped single crystal silicon layer.
  • part of the substrate 101 is removed, that is, the thickness of the substrate 101 is reduced; or, the entire substrate 101 and part of the doped single crystal silicon layer 200 are removed.
  • the substrate 101 includes a first top silicon layer, the doped single crystal silicon layer 200 is formed on the surface of the first top silicon layer, and at least a portion of the substrate 101 is removed, that is, the thickness of the first top silicon layer is thinned or the entire first top silicon layer is removed.
  • part of the first top silicon layer is removed.
  • mechanical grinding and/or chemical mechanical polishing (CMP) process can be used to thin the thickness of the first top silicon layer, but is not limited to the above process method, so that a thin first top silicon layer is retained on the surface of the doped single crystal silicon layer 200.
  • this thin first silicon layer and the doped single crystal silicon layer 200 constitute a thin film silicon layer used as a device layer.
  • the entire first top silicon layer is removed.
  • the chemical mechanical polishing process can be continued to be used on the basis of Figure 10 to remove the first top silicon layer to expose the doped single crystal silicon layer 200; or a dry etching or wet etching process can be used to remove the first top silicon layer to expose the doped single crystal silicon layer 200.
  • the remaining doped single crystal silicon layer 200 constitutes a thin film silicon layer used as a device layer.
  • the average doping concentration can be calculated by measuring the square resistance of the thin film silicon layer or other methods. If the doping concentration is lower than the preset doping concentration, the doping concentration can be increased by thermal diffusion, ion implantation, high temperature annealing and other methods. If the doping concentration is higher than the preset doping concentration, the number of effective doping ions can be changed by high temperature annealing and other methods to reduce the doping concentration. Note that the specific process parameters (such as heating rate, heating time, cooling rate, number of cycles, etc.) of the high temperature annealing process used to increase the doping concentration and reduce the doping concentration are set differently, and the specific process parameter settings of the annealing process are different for different preset doping concentrations.
  • the doping concentration of the heavily doped single crystal silicon layer 200 formed by epitaxial growth on the substrate 101 can vary with the growth thickness. In this way, the doping concentration of the doped single crystal silicon layer 200 can be adjusted and controlled according to the doping concentration requirements of a specific device.
  • the doped single crystal silicon layer 200 has at least two sub-doped single crystal silicon layers stacked along the growth thickness direction, and different sub-doped single crystal silicon layers have different doping concentrations.
  • the doped single crystal silicon layer 200 includes three sub-doped single crystal silicon layers stacked along the growth thickness direction, and the three sub-doped single crystal silicon layers can be respectively formed with a first sub-doped single crystal silicon layer and a second sub-doped single crystal silicon layer.
  • Layer 201, the second sub-doped single crystal silicon layer 202 and the third sub-doped single crystal silicon layer 203 represent that a thermal oxide layer 301 is grown on the surface of the first sub-doped single crystal silicon layer 201. It can be understood that the doping concentrations of the first sub-doped single crystal silicon layer 201, the second sub-doped single crystal silicon layer 202 and the third sub-doped single crystal silicon layer 203 are different.
  • the doping concentration of each sub-doped single crystal silicon layer is arranged in descending order along the growth thickness direction.
  • the doping concentration may be arranged in descending order from the first sub-doped single crystal silicon layer 201 to the third sub-doped single crystal silicon layer 203 .
  • the doping concentration may also be arranged from large to small from the third sub-doped single crystal silicon layer 203 to the first sub-doped single crystal silicon layer 201, and may be adaptively set according to the requirements of the doping concentration, and no specific limitation is made here.
  • the thickness and doping concentration of each sub-doped single crystal silicon layer can be regulated, so that the doping concentration of the doped single crystal silicon layer 200 can be flexibly and accurately controlled, so that the doping concentration of the doped single crystal silicon layer 200 can reach the target doping concentration.
  • the target doping concentration may range from greater than 1 ⁇ 10 18 cm -3 , and the preferred range may be from 1 ⁇ 10 19 to 10 21 cm -3 , but is not limited to this range, and may also be a higher doping concentration range, so that the semiconductor structure can achieve zero temperature drift characteristics, that is, the temperature coefficient can be close to zero, and the temperature performance is more stable, thereby improving the performance of the semiconductor structure, and further improving the yield of the semiconductor structure.
  • the doping concentration of the doped single crystal silicon layer 200 may vary continuously with the growth thickness, as shown in FIG13 . It can be understood that by making the doping concentration of the doped single crystal silicon layer 200 vary continuously with the growth thickness so that the doping concentration of the doped single crystal silicon layer 200 can reach the target doping concentration, the semiconductor structure can achieve a zero temperature drift characteristic, that is, the temperature coefficient can be close to zero, and the temperature performance is more stable, thereby enabling the performance of the semiconductor structure to be improved, thereby improving the yield of the semiconductor structure.
  • Step S105 forming a piezoelectric resonator layer on the surface of the doped single crystal silicon layer, and bonding an upper silicon cap to the piezoelectric resonator layer.
  • a first top silicon layer can be retained on the surface of the doped single crystal silicon layer 200, or the first top silicon layer, including the doped single crystal silicon layer 200, can be completely removed. In the embodiment of the present application, the entire first top silicon layer is removed as an example.
  • physical vapor deposition, chemical vapor deposition, epitaxial growth A piezoelectric resonator layer 500 is formed on the surface of the doped single crystal silicon layer 200 by processes such as.
  • a bottom electrode 503, a piezoelectric layer 502 and a top electrode 501 can be sequentially deposited on the surface of the doped single crystal silicon layer 200, that is, the bottom electrode 503, the piezoelectric layer 502 and the top electrode 501 are stacked along the thickness direction of the doped single crystal silicon layer 200, and the bottom electrode 503 is located on the doped single crystal silicon layer 200.
  • the bottom electrode 503, the piezoelectric layer 502 and the top electrode 501 together form a piezoelectric resonator 500 layer, which is then etched to form the final resonator structure.
  • the material of the bottom electrode 503 can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite of the above metals or their alloys;
  • the material of the piezoelectric layer 502 can be aluminum nitride (different from the single crystal aluminum nitride mentioned later, the aluminum nitride formed here by physical vapor deposition and other processes is polycrystalline aluminum nitride), zinc oxide, PZT and other materials and contain rare earth element doped materials with a certain atomic ratio of the above materials;
  • the material of the top electrode 501 can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite of the above metals or their alloys.
  • the bottom electrode 503 can be omitted, that is, the piezoelectric layer 502 and the top electrode 501 are directly formed on the surface of the doped single crystal silicon layer 200; in this case, the piezoelectric layer can be a single crystal AlN material and a single crystal doped AlN material (the doping element can be the above-mentioned rare earth element) formed by epitaxial growth.
  • the previously prepared upper silicon cap 700 is bonded to the piezoelectric resonator layer 500 to achieve packaging, as shown in FIG. 15a and FIG. 15b.
  • a first bonding layer 600 is provided between the upper silicon cap 700 and the piezoelectric resonator 500 layer, and the bonding packaging and electrical conduction between the upper silicon cap 700 and the piezoelectric resonator 500 layer are achieved through the first bonding layer 600.
  • the material of the first bonding layer 600 may be gold, aluminum, germanium, copper, tin, titanium, chromium or a composite layer of the above metals or an alloy thereof.
  • the first bonding layer may be located above the piezoelectric layer 502 and connected to the piezoelectric layer, or located above the top electrode 501 and connected to the top electrode, or the piezoelectric layer 502 at the corresponding position may be etched away and located on the surface of the doped single crystal silicon layer 200 or the surface of the bottom electrode 503.
  • a first dielectric layer 801 is formed between the doped single crystal silicon layer 200 and the bottom electrode 503 of the piezoelectric resonator layer 500 to pass through the first dielectric layer.
  • Layer 801 realizes electrical isolation between the bottom electrode 503 and the doped single crystal silicon layer 200 ;
  • a second dielectric layer 802 is formed on the surface of the top electrode 501 , and the second dielectric layer 802 can prevent the surface of the top electrode 501 from being passivated.
  • the materials of the first dielectric layer 801 and the second dielectric layer 802 may be insulating materials such as aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ) or silicon dioxide (SiO 2 ).
  • the structure of the piezoelectrically driven silicon-based resonator can be a cantilever beam, a simply supported beam, a tuning fork structure, or other forms of a combination of multiple beams, or other flat-plate structures, and its vibration mode can be a Lamé mode, a Lamb wave mode, a flexural mode, or the like.
  • the structures of the piezoelectrically driven silicon-based resonator are two different structures corresponding to the tuning forks in the out-of-plane flexural vibration mode (out-of-plane flexural mode) and the in-plane flexural vibration mode (in-plane flexural mode).
  • the substrate 101 is an SOI substrate.
  • an SOI substrate is provided, wherein the SOI substrate comprises a second bottom silicon layer 1011, a buried oxide layer 400 and a second top silicon layer 103 stacked in sequence, the second top silicon layer 103 and the second bottom silicon layer 1011 are made of single crystal silicon, and the buried oxide layer 400 can be made of SiO 2 .
  • Step S101 forming a heavily doped single crystal silicon layer on a substrate by epitaxial growth.
  • a doped single crystal silicon layer 200 is grown on the surface of the second top silicon layer 103 by epitaxial growth, as shown in FIG17 , wherein the doping elements and doping types of the doped single crystal silicon layer 200 are the same as those in the above-mentioned embodiment 1 and are not repeated here.
  • a thermal oxide layer is grown on the surface of the doped single crystal silicon layer 200 .
  • the SOI substrate with the thermal oxide layer formed on the surface of the doped single crystal silicon layer 200 is flipped and mounted on the first bottom silicon layer 102 having the cavity formed therein. Bonding is performed so that the first bottom silicon layer 102 is bonded to the SOI substrate to form an open and closed cavity. Note that it is also possible to directly use silicon-silicon bonding to bond the two prepared substrates without growing a thermal oxide layer, similar to FIG6; or after a silicon dioxide layer is patterned on the surface of the doped single crystal silicon layer 200, a silicon-silicon bonding process is still used outside the cavity, similar to the situation shown in FIG7b.
  • the SOI substrate is flipped and bonded to a first bottom silicon layer 102 without a thermal oxide layer grown on the surface.
  • the SOI substrate is flipped and bonded to a first bottom silicon layer 102 having a thermal oxide layer grown on the surface.
  • removing at least a portion of the substrate 101 specifically includes: removing the second bottom silicon layer 1011 and the buried oxide layer 400 in sequence.
  • removing at least a portion of the substrate 101 specifically includes: removing the second bottom silicon layer 1011 , the buried oxide layer 400 , and the second top silicon layer 103 in sequence.
  • the second bottom silicon layer 1011 , the buried oxide layer 400 and the second top silicon layer 103 in the SOI substrate are removed in sequence, specifically including: removing the second bottom silicon layer 1011 by chemical mechanical polishing and wet etching.
  • the second bottom silicon layer 1011 can be completely removed by chemical mechanical polishing and wet etching, and the buried oxide layer 400 can be exposed, as shown in FIG. 23 .
  • the buried oxide layer 400 is equivalent to an etching barrier layer. In this way, etching is stopped when the buried oxide layer 400 is etched, thereby avoiding etching damage to the second top silicon layer 103 under the buried oxide layer 400. Therefore, by setting the buried oxide layer 400 between the second bottom silicon layer 1011 and the second top silicon layer 103, the accuracy of the thickness of the substrate 101 can be better controlled.
  • the buried oxide layer 400 may be removed by a hydrofluoric acid (HF) solution, as shown in FIG. 24 , to expose the second top oxide layer.
  • HF hydrofluoric acid
  • a part or all of the second top silicon layer 103 may be removed by a chemical mechanical polishing (CMP) process; for example, in FIG. 25, the entire second top silicon layer 103 is removed by chemical mechanical polishing to expose the doped single crystal silicon layer 200, and then Further structures such as a piezoelectric resonator 500 layer are processed on the doped single crystal silicon layer 200 .
  • CMP chemical mechanical polishing
  • the thickness accuracy of the semiconductor structure can be better controlled.
  • an embodiment of the present application provides a semiconductor structure, including: a first bottom silicon layer 102 and a thin film silicon layer, which is formed on the surface of the first bottom silicon layer 102 by bonding, and the thin film silicon layer at least includes a doped single crystal silicon layer 200 formed in part by epitaxial growth, and the doped single crystal silicon layer 200 is located in the thin film silicon layer near the first bottom silicon layer 102, and the doped single crystal silicon layer 200 is a heavily doped layer.
  • the semiconductor structure further includes a piezoelectric resonator 500 layer and an upper silicon cap 700, wherein the doped single crystal silicon layer 200, the piezoelectric resonator 500 layer and the upper silicon cap 700 layer are sequentially stacked on the first bottom silicon layer 102 along the thickness direction of the first bottom silicon layer 102, and the doped single crystal silicon layer 200 is arranged on a side close to the first bottom silicon layer 102.
  • the material of the first bottom silicon layer 102 may be single crystal silicon, and a cavity is disposed on a side of the first bottom silicon layer 102 facing the doped single crystal silicon layer 200 .
  • the piezoelectric resonator 500 is formed on the surface of the doped single crystal silicon layer 200, and the upper silicon cap 700 is bonded to the piezoelectric resonator 500 to form a semiconductor structure such as a piezoelectric driven silicon-based resonator.
  • the doped single crystal silicon layer 200 is an N-type heavily doped single crystal silicon layer 200 or a P-type heavily doped single crystal silicon layer 200, wherein the doped single crystal silicon layer 200 is doped while the silicon layer is grown, for example, by epitaxial growth, and the doped ion elements of the doped single crystal silicon layer 200 may be B, As, P, or the like.
  • the doping concentration of the doped single crystal silicon layer 200 can be changed with the growth thickness. In this way, the doping concentration of the doped single crystal silicon layer 200 can be flexibly and accurately controlled so that the doping concentration of the doped single crystal silicon layer 200 can reach the target doping concentration. For example, the range of the target doping concentration can be large.
  • the doping concentration of the semiconductor structure is preferably in the range of 1 ⁇ 10 18 cm -3 , and preferably in the range of 1 ⁇ 10 19 to 10 21 cm -3 , but is not limited to this range, and may also be in a higher doping concentration range, so that the semiconductor structure can achieve zero temperature drift characteristics, that is, the temperature coefficient can be close to zero, and the temperature performance is more stable, thereby improving the performance of the semiconductor structure and thus improving the yield of the semiconductor structure.
  • the doped single crystal silicon layer 200 has at least two sub-doped single crystal silicon layers stacked along the growth thickness direction, and different sub-doped single crystal silicon layers have different doping concentrations.
  • the doped single crystal silicon layer 200 includes a first sub-doped single crystal silicon layer 201, a second sub-doped single crystal silicon layer 202 and a third sub-doped single crystal silicon layer 203, wherein the surface growth of the first sub-doped single crystal silicon layer 201 is formed on the thermal oxide layer. It can be understood that the doping concentrations of the first sub-doped single crystal silicon layer 201, the second sub-doped single crystal silicon layer 202 and the third sub-doped single crystal silicon layer 203 are different.
  • the doping concentration of each sub-doped single crystal silicon layer is arranged in descending order along the growth thickness direction.
  • the doping concentration may be arranged in descending order from the first sub-doped single crystal silicon layer 201 to the third sub-doped single crystal silicon layer 203 .
  • the doping concentration may also be arranged from large to small from the third sub-doped single crystal silicon layer 203 to the first sub-doped single crystal silicon layer 201, and may be adaptively set according to the requirements of the doping concentration, and no specific limitation is made here.
  • the doping concentration of each sub-doped single crystal silicon layer is made to vary in a gradient, so that the thickness and doping concentration of each sub-doped single crystal silicon layer can be regulated, so that the doping concentration of the doped single crystal silicon layer 200 can be flexibly and accurately controlled, so that the semiconductor structure can achieve zero temperature drift characteristics, that is, the temperature coefficient can be close to zero, and the temperature performance is more stable, thereby improving the performance of the semiconductor structure and further improving the yield of the semiconductor structure.
  • the doping concentration of the doped single crystal silicon layer 200 may vary continuously with the growth thickness, as shown in FIG13 . It can be understood that by making the doping concentration of the doped single crystal silicon layer 200 vary continuously with the growth thickness so that the doping concentration of the doped single crystal silicon layer 200 can reach the target doping concentration, the semiconductor structure can achieve a zero temperature drift characteristic, that is, the temperature coefficient can be close to zero, and the temperature performance is more stable, thereby enabling the performance of the semiconductor structure to be improved, thereby improving the yield of the semiconductor structure.
  • the doped single crystal silicon layer 200 and the first bottom silicon layer 102 can be formed by bonding.
  • a thermal oxide layer 301 that is, the thermal oxide layer 301 is disposed on the first bottom silicon layer.
  • the thermal oxide layer may cover a cavity wall on one side of the cavity opposite to the doped single crystal silicon layer 200 , as shown in FIG. 9 .
  • the thermal oxide layer covers one side surface of the doped single crystal silicon layer 200 corresponding to the cavity, as shown in FIG. 7 a .
  • the thermal oxide layer covers the cavity wall and a surface of the doped single crystal silicon layer 200 corresponding to the cavity, as shown in FIG. 8 .
  • the piezoelectric resonator 500 includes a bottom electrode 503 , a piezoelectric layer 502 , and a top electrode 501 sequentially stacked on the surface of the doped single crystal silicon layer 200 .
  • the material of the piezoelectric layer 502 can be any one of aluminum nitride, polycrystalline aluminum nitride, and rare earth element doped aluminum nitride.
  • the material of the piezoelectric layer 502 is rare earth element doped aluminum nitride; wherein the rare earth element doped aluminum nitride includes at least one of scandium (Sc), yttrium (Y), magnesium (Mg), titanium (Ti), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).
  • Sc scandium
  • Y yttrium
  • Mg magnesium
  • Ti titanium
  • La lanthanum
  • Ce cerium
  • Pr praseodymium
  • Nd neodymium
  • promethium Pm
  • a dielectric layer may be disposed between the bottom electrode 503 and the thin film silicon layer.
  • the material of the dielectric layer may be any one of silicon dioxide, silicon nitride, aluminum oxide, and aluminum nitride.
  • the upper silicon cap 700 can be set on the top electrode 501 of the piezoelectric resonator 500 by bonding.
  • a first bonding layer 600 is provided between the upper silicon cap 700 and the top electrode 501. The bonding between the upper silicon cap 700 and the top electrode 501 is achieved through the first bonding layer 600, thereby improving its bonding reliability.
  • the upper silicon cap 700 includes a substrate 701 and a second bonding layer 702, the second bonding layer 702 is arranged on the side of the substrate 701 facing the first bonding layer 600; the substrate 701 is also provided with a conductive through hole 704 penetrating the substrate 701 and the second bonding layer 702, and the side of the upper silicon cap 700 away from the second bonding layer 702 is provided with a metal pin 703 electrically connected to the conductive through hole 704, and the side of the substrate 701 facing the top electrode 501 is also provided with a getter layer 705, the material of which can be titanium (Ti) and titanium alloys, zirconium (Zr) and zirconium alloys, etc.
  • the substrate 701 is provided with a metal pin 703 electrically connected to the conductive through hole 704, and the substrate 701 is provided with a metal pin 703 electrically connected to the conductive through hole 704.
  • the material of the base 701 may be single crystal silicon or the like.
  • the surface where the second bonding layer 702 and the conductive layer of the conductive via 704 contact the base 701 is also provided with a SiO2 layer generated by thermal oxidation or chemical vapor deposition as an insulating layer, so that the second bonding layer 702 and the conductive layer of the conductive via 704 do not directly contact the base 701, thereby improving the isolation characteristics between the device input, output and ground ports.
  • the second bonding layer 702 By arranging the second bonding layer 702 on the side of the substrate 701 facing the first bonding layer 600, the upper silicon cap 700 and the top electrode 501 are bonded through the first bonding layer 600 and the second bonding layer 702, so that the bonding reliability between the upper silicon cap 700 and the top electrode 501 can be further improved.
  • the material of the second bonding layer 702 can be gold, aluminum, germanium, copper, tin, titanium or a composite layer of the above metals or an alloy thereof, and specifically, a material matching the material of the first bonding layer 600 can be selected, that is, the first bonding layer 600 and the second bonding layer 702 can be hot-pressed bonded, for example, the bonding material matching the first bonding layer 600 and the second bonding layer 702 can be: gold-gold bonding, aluminum-germanium bonding, copper-copper bonding, copper-gold-copper bonding, copper-tin bonding, copper-tin-gold bonding, etc.
  • the upper silicon cap 700 is also provided with a through hole penetrating the substrate 701 and the second bonding layer 702, and a conductive layer is attached to the hole wall of the through hole, and the through hole and the conductive layer on the surface form a conductive through hole 704, wherein the material of the conductive layer in the conductive through hole 704 can be copper, gold, aluminum, aluminum-silicon-copper alloy or other materials or their composite layers.
  • the metal pin 703 is made of gold, aluminum, copper, titanium, iridium, osmium, chromium, or a composite of the above metals or an alloy thereof.
  • the semiconductor structure formed in the above solution can be electrically connected to other devices through the metal pins 703.
  • the upper silicon cap 700 has an etched protrusion structure and an upper cavity structure for accommodating the device, wherein the second bonding layer 702 is located on the protrusion structure, and the getter layer 705 is located inside the cavity.
  • the upper silicon cap may also not have an etched cavity structure and/or protrusion structure, so that the side of the upper silicon cap 700 facing the device is a flat surface, and in this case, only the upper cavity structure for accommodating the device is formed by the bonding layer.
  • An embodiment of the present application also provides an electronic device, comprising the semiconductor structure provided in the above embodiment.
  • the method for preparing a semiconductor structure comprises: forming a heavily doped single crystal silicon layer on a substrate by epitaxial growth; forming a cavity on a first bottom silicon layer; After assembly, the doped single crystal silicon layer is bonded to the first bottom silicon layer; at least a portion of the substrate is removed to form a thin film silicon layer on the first bottom silicon layer; wherein the thin film silicon layer includes at least a portion of the thickness of the doped single crystal silicon layer.
  • a heavily doped doped single crystal silicon layer is formed on the substrate by epitaxial growth, so that the doping concentration of the silicon layer of the semiconductor structure can be increased, and the doping concentration is adjustable and controllable, thereby improving the performance consistency and yield of the semiconductor structure.

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Abstract

本申请提供一种半导体结构的制备方法、半导体结构及电子设备，涉及半导体制造技术领域，用于解决半导体结构的性能均匀性差、良率低的技术问题，该半导体结构的制备方法包括：在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层；在第一底硅层上形成空腔；将衬底倒装后，使掺杂单晶硅层与第一底硅层键合；去除至少部分衬底，以在第一底硅层上形成薄膜硅层；其中，薄膜硅层至少包含部分厚度的掺杂单晶硅层。本申请能够提高半导体结构中硅层掺杂浓度的可控性及精确性，从而能够提升半导体结构的性能一致性和良率，特别是频率温度特性的片内、片间、批次内、批次间一致性。

Description

半导体结构的制备方法、半导体结构及电子设备
本申请要求于2022年10月21日提交中国专利局、申请号为202211296651.0、申请名称为“半导体结构的制备方法、半导体结构及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构的制备方法、半导体结构及电子设备。
背景技术
目前，硅基压电谐振器大多采用带预置空腔的绝缘层上硅(Cavity Silicon-on-Insulator，简称CSOI)衬底制作。
通常，CSOI衬底的制备方法为：将用作器件层的硅片或SOI硅片长热氧后与已经刻蚀出空腔的硅基底进行键合，或者，热氧层也可以是长在空腔一侧的基底上，然后与用作器件层的硅片或SOI硅片进行键合，再通过机械研磨、化学机械抛光技术、湿法刻蚀、干法刻蚀等方法对硅片或SOI进行减薄，最终留下较薄的硅器件层，从而制作成CSOI硅片。在上述方法中，硅片或SOI硅片中器件硅层(device layer)的初始特性决定了CSOI器件层特性，特别是其掺杂浓度会决定硅基压电谐振器最终的频率温度特性。而硅片或者SOI硅片中器件硅层多采用直拉法制造，其掺杂浓度的精度及片间及批次间均一性较差，特别对于掺杂浓度接近或大于1019cm-3的情况，其精度和均一性会更差，而此时温度系数对掺杂浓度的敏感性更强，因此，采用上述CSOI制造的压电硅基谐振器其频率温度系数的片内、片间、批次内、批次间一致性较差，从而导致器件良率低，成本高。另一方面，这种直拉法制造的硅片其掺杂浓度通常难以达到1020cm-3以上，从而限制了硅的频率温度系数可用范围，对于某些模式的压电驱动硅基谐振器，不易实现其零温漂特性。
发明内容
鉴于上述问题，本申请实施例提供一种半导体结构的制备方法、半导体结构及电子设备，以解决半导体结构的性能一致性差(特别是频率温度特性一致性差)、良率低的技术问题，能够提高半导体结构的性能一致性，从而提高半导体结构的良率，降低器件成本，同时，提高半导体结构中硅层可用的掺杂浓度范围及相应的可获得的频率温度系数范围。
为了实现上述目的，本申请实施例提供如下技术方案：
本申请实施例的第一方面提供一种半导体结构的制备方法，其包括：
在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层；
在第一底硅层上形成空腔；
将所述衬底倒置后，使所述掺杂单晶硅层与所述第一底硅层键合；
去除至少部分所述衬底，以在第一底硅层上形成薄膜硅层；其中，所述薄膜硅层至少包含部分厚度的所述掺杂单晶硅层。
在一些可选的实施方式中，所述在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层的步骤中，具体包括：
在所述衬底上形成掺杂浓度随生长厚度而变化的所述掺杂单晶硅层。
在一些可选的实施方式中，所述掺杂单晶硅层具有至少两个沿生长厚度方向层叠设置的子掺杂单晶硅层，不同所述子掺杂单晶硅层具有不同的掺杂浓度和/或不同的掺杂剂。
在一些可选的实施方式中，各所述子掺杂单晶硅层的掺杂浓度随所述生长厚度方向由大到小或由小到大依次排列。
在一些可选的实施方式中，所述掺杂单晶硅层的掺杂浓度随生长厚度而连续变化。
在一些可选的实施方式中，所述掺杂单晶硅层的掺杂浓度大于所述衬底掺杂浓度，所述掺杂单晶硅层为N型重掺杂单晶硅层或P型重掺杂单晶硅层；其中，所述掺杂单晶硅层的掺杂浓度大于或等于1019cm-3。
在一些可选的实施方式中，所述掺杂单晶硅层的掺杂浓度大于或等于1020cm-3。
在一些可选的实施方式中，所述将所述衬底倒置后和所述第一底硅层键合之前，还包括：
在所述掺杂单晶硅层和所述第一底硅层的至少一者上形成热氧层。
在一些可选的实施方式中，所述衬底包括第一顶硅层，所述掺杂单晶硅层形成于所述第一顶硅层表面。
在一些可选的实施方式中，所述去除至少部分所述衬底，具体包括：减薄所述第一顶硅层的厚度；或者，去除所述第一顶硅层。
在一些可选的实施方式中，所述在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层，具体包括：
对于包括依次层叠设置的第二顶硅层、埋氧层和第二底硅层的SOI衬底，在所述SOI衬底的第二顶硅层上外延生长重掺杂的所述掺杂单晶硅层。
在一些可选的实施方式中，所述去除至少部分所述衬底，具体包括：
依次去除所述第二底硅层和所述埋氧层；或者，依次去除所述第二底硅层、所述埋氧层和至少部分所述第二顶硅层。
在一些可选的实施方式中，所述去除至少部分所述衬底，具体包括：
去除全部所述衬底和部分所述掺杂单晶硅层。
在一些可选的实施方式中，在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层后，或在第一底硅层上形成薄膜硅层后，还包括：
通过离子注入或热扩散方式对所述掺杂单晶硅层或薄膜硅层进行掺杂；和/或者，
对所述掺杂单晶硅层或薄膜硅层进行高温退火。
在一些可选的实施方式中，若所述掺杂单晶硅层或薄膜硅层的掺杂浓度小于预设掺杂浓度，则通过离子注入或热扩散方式对所述掺杂单晶硅层或所述薄膜硅层进行硅层掺杂，或者对所述掺杂单晶硅层或薄膜硅层进行高温退火，以提高掺杂单晶硅层或薄膜硅层的掺杂浓度；若所述掺杂单晶硅层或薄膜硅层的掺杂浓度大于预设掺杂浓度，对所述掺杂单晶硅层或薄膜硅层进行高温退火，以减小所述掺杂单晶硅层或薄膜硅层的掺杂浓度。
在一些可选的实施方式中，所述去除至少部分所述衬底，以在第一底硅层上形成薄膜硅层之后，还包括：
在所述薄膜硅层的表面形成压电谐振器层。
在一些可选的实施方式中，所述在所述薄膜硅层的表面形成压电谐振器层之后，还包括：
将上硅帽键合至所述压电谐振器层。
本申请实施例的第二方面提供一种半导体结构，包括：
第一底硅层，具有空腔；
薄膜硅层，通过键合形成于所述第一底硅层表面，所述薄膜硅层，至少包含部分通过外延生长方式形成的掺杂单晶硅层，所述掺杂单晶硅层位于薄膜硅层中靠近第一底硅层的位置，且所述掺杂单晶硅层为重掺杂层。
在一些可选的实施方式中，所述掺杂单晶硅层为N型重掺杂单晶硅层或P型重掺杂单晶硅层；且所述掺杂单晶硅层的掺杂浓度大于或等于1019cm-3。
在一些可选的实施方式中，所述掺杂单晶硅层的掺杂浓度随生长厚度而变化。
在一些可选的实施方式中，所述掺杂单晶硅层具有至少两个沿生长厚度方向层叠设置的子掺杂单晶硅层，不同所述子掺杂单晶硅层具有不同的掺杂浓度和/或不同的掺杂剂。
在一些可选的实施方式中，各所述子掺杂单晶硅层的掺杂浓度随所述生长厚度方向由大到小或由小到大依次排列。
在一些可选的实施方式中，所述掺杂单晶硅层的掺杂浓度随生长厚度而连续变化。
在一些可选的实施方式中，还包括热氧层，所述热氧层设置于所述第一底硅层和所述掺杂单晶硅层之间。
在一些可选的实施方式中，所述热氧层覆盖所述空腔的与所述掺杂单晶硅层相对的一侧腔壁。
在一些可选的实施方式中，所述热氧层覆盖所述掺杂单晶硅层的与所述空腔对应的一侧表面。
在一些可选的实施方式中，所述热氧层覆盖所述空腔的腔壁以及所述掺杂单晶硅层的与所述空腔对应的一侧表面。
在一些可选的实施方式中，还包括：
压电谐振器层，形成于所述薄膜硅层表面；
上硅帽，键合于所述压电谐振器层上。
在一些可选的实施方式中，所述压电谐振器层包括在所述薄膜硅层表面依次层叠设置的压电层和顶电极。
在一些可选的实施方式中，所述压电谐振器还包括底电极，所述底电极 设置于所述压电层背离所述顶电极的一侧。
在一些可选的实施方式中，所述底电极与所述薄膜硅层之间设置有介质层，所述介质层为二氧化硅、氮化硅、氧化铝、氮化铝中的至少一种。
在一些可选的实施方式中，所述压电层为单晶氮化铝、多晶氮化铝、稀土元素掺杂氮化铝中的任一种；其中，所述稀土元素掺杂氮化铝包括钪、钇、镁、钛、镧、铈、镨、钕、钷、钐、铕、钆、铽、镝、钬、铒、铥、镱、镥中的至少一种。
在一些可选的实施方式中，所述上硅帽和所述压电层之间设置有第一键合层。
在一些可选的实施方式中，所述上硅帽包括基底和第二键合层，所述第二键合层设置在所述基底面向所述第一键合层的一侧；
所述基底上还设置有贯穿所述基底和所述第二键合层的导电通孔，上硅帽背离所述第二键合层的一侧设置有与所述导电通孔电连接的金属引脚，所述基底面向所述压电谐振器层的一侧还设置有吸气剂层。
在一些可选的实施方式中，所述第一键合层和所述第二键合层均为金属层。
在一些可选的实施方式中，所述金属引脚和所述导电通孔与所述基底之间均设置有二氧化硅层。
本申请实施例的第三方面提供一种电子设备，包括上述实施例提供的半导体结构。
本申请实施例提供的半导体结构的制备方法，包括：在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层；在第一底硅层上形成空腔；将衬底倒装后，使掺杂单晶硅层与第一底硅层键合；去除至少部分衬底，以在第一底硅层上形成薄膜硅层；其中，薄膜硅层至少包含部分厚度的掺杂单晶硅层。上述方案中，在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层，这样，可以提高半导体结构中硅层掺杂浓度，且掺杂浓度可调可控性好，从而能够提升半导体结构的性能一致性和良率。
本申请的构造以及它的其他发明目的及有益效果将会通过结合附图而对优选实施例的描述而更加明显易懂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的半导体结构的制备方法的流程示意图；
图2为本申请一实施例中在衬底上形成掺杂单晶硅层的剖面示意图；
图3为本申请一实施例中在第一底硅层上形成空腔的剖面示意图；
图4为本申请一实施例中在掺杂单晶硅层上形成热氧层的剖面示意图；
图5为本申请一实施例中在第一底硅层上形成热氧层的剖面示意图；
图6为本申请一实施例提供的半导体结构的一种结构的剖面示意图；
图7a为本申请一实施例提供的半导体结构的另一种结构的剖面示意图；
图7b为本申请一实施例提供的半导体结构的另一种结构的剖面示意图；
图8为本申请一实施例中掺杂单晶硅层和第一底硅层上均形成有热氧层的剖面示意图；
图9为图1倒装后与图5键合后的剖面示意图；
图10为图9中去除部分衬底后的剖面示意图；
图11为图9中去除全部衬底后的剖面示意图；
图12为图11中掺杂单晶硅层按梯度掺杂浓度生长的剖面示意图；
图13为图11中掺杂单晶硅层的掺杂浓度连续变化生长的剖面示意图；
图14为在图11上形成压电谐振器层后的剖面示意图；
图15a为在图14上封装上硅帽的一种结构的剖面示意图；
图15b为在图14上封装上硅帽的另一种结构的剖面示意图；
图16为本申请实施例提供的半导体器件中振动模式的音叉的一种结构的俯视示意图；
图17为本申请实施例提供的半导体器件中振动模式的音叉的另一种结构的俯视示意图；
图18为本申请另一实施例中在SOI衬底上形成掺杂单晶硅层的剖面示意图；
图19为在图18的基础上形成热氧层的剖面结构示意图；
图20为本申请另一实施例中只在掺杂单晶硅层上形成热氧层的剖面示意图；
图21为本申请另一实施例中在掺杂单晶硅层和第一底硅层上均形成热氧层的剖面示意图；
图22为本申请另一实施例中只在第一底硅层上形成热氧层的剖面示意图；
图23为本申请另一实施例中去除SOI衬底中第二顶硅层后的剖面示意图；
图24为本申请另一实施例中去除SOI衬底中埋氧层后的剖面示意图；
图25为本申请另一实施例中去除SOI衬底中第二底硅层后的剖面示意图。
附图标记：
101-衬底；         1011-第二底硅层；  103-第二顶硅层；
102-第一底硅层；   200-掺杂单晶硅层； 201-第一子掺杂单晶硅层；
202-第二子掺杂单晶硅层；              203-第三子掺杂单晶硅层；
301、302-热氧层；  400-埋氧层；       500-压电谐振器层；
501-顶电极；       502-压电层；       503-底电极；
600-第一键合层；   700-上硅帽；       701-基底；
702-第二键合层；   703-金属引脚；     704-导电通孔；
705-吸气剂层；     801-第一介质层；   802-第二介质层。
具体实施方式
正如背景技术所述，在传统CSOI制作流程中用作器件层的硅片或SOI的器件硅层，通常采用直拉法制造，在其掺杂浓度接近1x1019cm-3时其掺杂浓度的控制精度较差，从而使得硅片间以及批次件性能一致性变差，进而导致制造出的器件性能一致性差(特别是频率温度特性的一致性)、良率低的技术问题。另一方面，这种直拉法制造的硅片其掺杂浓度通常难以 达到1020cm-3以上，从而限制了硅的频率温度系数范围，对于某些模式的压电驱动硅基谐振器，不易实现其零温漂特性。
为了解决上述问题，本申请实施例提供一种半导体结构的制备方法、半导体结构及电子设备，其中，在半导体结构的制备方法中，通过在衬底上以外延生长的方式形成重掺杂的掺杂单晶硅层，容易控制其掺杂浓度使其达到1019cm-3甚至1020cm-3以上，同时其掺杂浓度的精度可以控制得更好。这样，可以实现高浓度掺杂且掺杂浓度可调可控性好的器件硅层，从而能够提升半导体结构的最终频率温度特性，以及频率温度特性在片内、片间、批次内、批次间的一致性和良率。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
本申请实施例提供的半导体结构可以是谐振器、换能器、驱动器等，在本申请中，以半导体结构为谐振器(例如压电驱动硅基谐振器)为例进行介绍。
实施例一
图1为本申请一实施例提供的半导体结构的制备方法的流程示意图。请参照图1所示，本申请实施例提供一种半导体结构的制备方法，包括：
步骤S101：在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层。
可以理解的是，如图2所示，在衬底101上通过外延生长方式形成重掺杂的掺杂单晶硅层200之前，还包括：提供衬底101。其中，衬底101可以为衬底101上的结构层提供支撑基础。该衬底101可以为晶体半导体材料制成，例如，衬底101可以为硅(Si)衬底，衬底101还可以为锗化硅(SiGe)衬底、碳化硅(SiC)衬底、绝缘体上硅(silicon-on-insulator，简称SOI)衬底等，其中，衬底101可以为单层结构，也可以为多层复合结构，具体根据实际需求进行适应性设计，在此不做具体限制，在本实施例中，以衬底101为单晶硅为例进行介绍。
在一些实施例中，通过外延生长方式形成重掺杂的掺杂单晶硅层200 于衬底101上。可以理解的是，在衬底101上通过外延生长单晶硅层的同时，向外延生长的硅层做硅层掺杂，掺杂单晶硅层200的掺杂元素可以为B、As或者P等；形成的掺杂类型可以为N型或P型(P型掺杂的掺杂剂一般为硼元素，也可以是铝、镓、铟等三族元素；N型掺杂的掺杂剂一般为磷元素或砷等五族元素)，例如，在图2中，在衬底101的表面生长形成N型(掺杂剂为磷)重掺杂(掺杂浓度大于1019cm-3)的掺杂单晶硅层200。通常，掺杂单晶硅层的掺杂浓度大于衬底的掺杂浓度。
进一步的，在外延形成的掺杂单晶硅层中，可以进一步通过离子注入或热扩散方法提高掺杂浓度，或通过高温退火(1000℃左右)改变掺杂剂在硅层中的分布特性。
步骤S102：在第一底硅层上形成空腔。
其中，第一底硅层102为第一底硅层102上的结构层提供支撑基础；第一底硅层102可以为晶体半导体材料制成，例如，第一底硅层102的材料可以为硅(Si)、单晶硅、锗化硅(SiGe)、碳化硅(SiC)、绝缘体上硅(silicon-on-insulator，简称SOI)、砷化镓、氮化镓等，在本申请实施例中，第一底硅层102的材料为单晶硅。
在一些实施例中，在第一底硅层102上形成空腔，其中，空腔可以是在第一底硅层102的表面上形成开口的凹陷结构，如图3中所示，且第一底硅层102上的空腔可通过干法刻蚀或者湿法刻蚀等工艺形成，示例性的，在第一底硅层102的表面上刻蚀形成的空腔的深度可以在几微米到百微米之间，例如：5μm、50μm、100μm等，其中，空腔的具体深度可根据半导体结构结构的实际需求进行适应性设计，在此不做具体限制。
在一些实施例中，在衬底101上通过外延生长方式形成重掺杂的掺杂单晶硅层200以及在第一底硅层102上形成空腔之后，还包括：
在掺杂单晶硅层200和第一底硅层102的至少一者上形成热氧层。可以理解的是，可以在掺杂单晶硅层200背离衬底101的一侧表面上生长形成热氧层301，如图4中所示，通过在掺杂单晶硅层200的表面生长形成热氧层301，可以使得掺杂单晶硅层200的单晶硅为正的温度系数，因此对掺杂单晶硅层200具有温补的效果；当然，也可以在第一底硅层102具有空腔的一侧生长形成热氧层302，如图5中所示，这样，热氧层302可 以作为粘附层，以使得第一底硅层102与衬底101在后续键合过程中具有良好的粘接性。其中，热氧层的材料可以为二氧化硅(SiO2)。
步骤S103：将衬底倒置后，使掺杂单晶硅层与第一底硅层键合。
如图6所示，可以将掺杂单晶硅层200与第一底硅层102直接键合；
或者，如图7a至图9所示，在掺杂单晶硅层200和第一底硅层102的至少一者上形成热氧层之后，将衬底101倒装在第一底硅层102上，并与第一底硅层102键合。
在图7a中，只在掺杂单晶硅层200的表面生长形成热氧层301，在第一底硅层102的表面未形成热氧层，在掺杂单晶硅层200上形成热氧层301之后，将衬底101倒装在第一底硅层102上并与第一底硅层102键合，这样，掺杂单晶硅层200表面的热氧层301在提升掺杂单晶硅层200与第一底硅层102之间的粘接性的同时，还具有对掺杂单晶硅层200的温补效果，使得掺杂单晶硅层200的硅的温度系数为正。
在如图7b中，在掺杂单晶硅层200表面生长一层二氧化硅层并做图形化，使其边缘落入第一底硅层102的空腔内侧，此时仍然是通过硅-硅键合实现两个制备好的衬底间键合。
在图8中，在掺杂单晶硅层200的表面和第一底硅层102上均生长形成有热氧层，形成热氧层之后，将衬底101倒装在第一底硅层102上并与第一底硅层102键合。这样，热氧层在提升掺杂单晶硅层200与第一底硅层102之间的粘接性的同时，还具有对掺杂单晶硅层200的温补效果，使得掺杂单晶硅层200的硅的温度系数为正。
在图9中，只在第一底硅层102上形成热氧层302，掺杂单晶硅层200上未形成热氧层，之后将衬底101倒装在第一底硅层102上并与第一底硅层102键合，这样，热氧层302可以提高第一底硅层102与掺杂单晶硅层200之间的粘接性。
可以理解的是，当第一底硅层102上形成空腔后与衬底101未键合时，此时，第一底硅层102上的空腔为开口的空腔，而当衬底101倒装后与第一底硅层102键合后，衬底101封堵空腔的开口，以使得衬底101与第一底硅层102之间形成封闭的空腔。
步骤S104：去除至少部分衬底，以在第一底硅层上形成薄膜硅层；其 中，薄膜硅层至少包含部分厚度的掺杂单晶硅层。
可以理解的是，当衬底101倒装后与第一底硅层102键合后，去除部分衬底101，即减薄衬底101的厚度；或者，去除全部衬底101和部分掺杂单晶硅层200。
在一些实施例中，衬底101包括第一顶硅层，掺杂单晶硅层200形成于第一顶硅层表面，去除至少部分衬底101，即减薄第一顶硅层的厚度或者去除全部第一顶硅层。
在图10中，去除部分第一顶硅层，具体的，可采用机械研磨和/或化学机械抛光(Chemical Mechanical Polishing，简称，CMP)工艺减薄第一顶硅层的厚度，但不限于上述工艺方法，使得在掺杂单晶硅层200的表面保留有一层厚度较薄的第一顶硅层，此时，这一薄层第一等硅层和掺杂单晶硅层200构成了用作器件层的薄膜硅层。
在图11中，去除全部第一顶硅层，例如，可以在图10的基础上继续采用化学机械抛光的工艺去除第一顶硅层，暴露出掺杂单晶硅层200；也可以采用干法刻蚀或湿法刻蚀工艺去除第一顶层硅，暴露出掺杂单晶硅层200，此时，剩余的掺杂单晶硅层200构成了用作器件层的薄膜硅层。
在形成的新衬底上，可以通过测量薄膜硅层的方块电阻或其他方法，计算出其平均掺杂浓度，若掺杂浓度低于预设掺杂浓度，则可以通过热扩散、离子注入、高温退火等方法提高掺杂浓度，若掺杂浓度高于预设掺杂浓度，则可以通过高温退火等方法改变有效掺杂离子数目进而减小掺杂浓度。注意提高掺杂浓度和减小掺杂浓度中所用到的高温退火工艺的具体工艺参数(如：升温速率、加热时间、降温速率、循环次数等)设置不同，以及针对不同预设掺杂浓度，其退火工艺的具体工艺参数设置有所不同。
另外，在衬底101上通过外延生长方式形成重掺杂的掺杂单晶硅层200的掺杂浓度可以随生长厚度而变化，这样，可以根据具体器件对掺杂浓度的需求，对掺杂单晶硅层200的掺杂浓度进行调整控制。
在一些实施例中，掺杂单晶硅层200具有至少两个沿生长厚度方向层叠设置的子掺杂单晶硅层，不同子掺杂单晶硅层具有不同的掺杂浓度。示例性的，如图12所示，掺杂单晶硅层200包括三个沿生长厚度方向层叠设置的子掺杂单晶硅层，三个子掺杂单晶硅层可分别用第一子掺杂单晶硅 层201、第二子掺杂单晶硅层202和第三子掺杂单晶硅层203表示，其中，第一子掺杂单晶硅层201的表面生长形成有热氧层301，可以理解的是，第一子掺杂单晶硅层201、第二子掺杂单晶硅层202和第三子掺杂单晶硅层203的掺杂浓度不同。
在一些实施例中，各子掺杂单晶硅层的掺杂浓度随生长厚度方向由大到小依次排列。例如，掺杂浓度可以是由第一子掺杂单晶硅层201到第三子掺杂单晶硅层203依次由大到小排列。
或者，掺杂浓度也可以是由第三子掺杂单晶硅层203到第一子掺杂单晶硅层201依次由大到小排列，具体根据掺杂浓度的需求进行适应性设置，在此不做具体限制。
可以理解的是，上述方案中，通过使各子掺杂单晶硅层的掺杂浓度呈梯度变化，这样，各子掺杂单晶硅层的厚度和掺杂浓度可以进行调控，以使得掺杂单晶硅层200的掺杂浓度能够进行灵活且精确的控制，使得掺杂单晶硅层200的掺杂浓度能够达到目标掺杂浓度，例如，目标掺杂浓度的范围可以为大于1×1018cm-3，优选范围可以为1×1019到1021cm-3，但不限于该范围，也可以为更高掺杂浓度范围，以使得半导体结构能够实现零温漂特性，即温度系数能够接近零，温度性能更稳定，从而能够使半导体结构的性能得到提升，进而提升半导体结构的良率。
在另一些实施例中，掺杂单晶硅层200的掺杂浓度可随生长厚度而连续变化，如图13中所示，可以理解的是，通过使掺杂单晶硅层200的掺杂浓度随生长厚度而连续变化，以使得掺杂单晶硅层200的掺杂浓度能够达到目标掺杂浓度，使得半导体结构能够实现零温漂特性，即温度系数能够接近零，温度性能更稳定，从而能够使半导体结构的性能得到提升，从而提升半导体结构的良率。
步骤S105：在掺杂单晶硅层的表面形成压电谐振器层，并将上硅帽键合至压电谐振器层。
可以理解的是，衬底101倒装后与第一底硅层102键合后，掺杂单晶硅层200的表面上可以保留一层第一顶硅层，或者完全去除第一顶硅层，包括掺杂单晶硅层200，在本申请实施例中，以去除全部第一顶硅层为例进行介绍，如图14所示，可通过物理气相沉积、化学气相沉积、外延生长 等工艺在掺杂单晶硅层200的表面上形成压电谐振器500层。
在一些实施例中，可以在掺杂单晶硅层200的表面依次沉积形成底电极503、压电层502和顶电极501，即底电极503、压电层502和顶电极501沿掺杂单晶硅层200的厚度方向层叠设置，且底电极503位于掺杂单晶硅层200上，这样，底电极503、压电层502和顶电极501共同形成压电谐振器500层，再经过刻蚀形成最终的谐振器结构。
其中，底电极503的材料可以为钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等；压电层502的材料可以为氮化铝(与后文中提到的单晶氮化铝不同，此处通过物理气相沉积等工艺形成的氮化铝为多晶氮化铝)，氧化锌，PZT等材料并包含上述材料的一定原子比的稀土元素掺杂材料；顶电极501的材料可以为钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金。
在另一些实施例中(未在图中示出)，底电极503可以省略，即直接在掺杂单晶硅层200表面形成压电层502和顶电极501；此时，压电层可以是通过外延生长方式形成的单晶AlN材料及单晶掺杂AlN材料(掺杂元素可以是上述稀土元素)。
在掺杂单晶硅层200的表面沉积形成压电谐振器之后，将之前制备好的上硅帽700键合至压电谐振器500层实现封装，如图15a和图15b所示。
在一些实施例中，如图15a和图15b所示，上硅帽700与压电谐振器500层进行键合封装时，上硅帽700与压电谐振器500层之间设置有第一键合层600，通过第一键合层600实现上硅帽700与压电谐振器500层之间的键合封装并实现电导通。
其中，第一键合层600的材料可以为金、铝、锗、铜、锡、钛、铬或以上金属的复合层或其合金。第一键合层可以位于压电层502上方与压电层相接，也可以位于顶电极501上方与顶电极相接，也可以将对应位置的压电层502刻蚀开，位于掺杂单晶硅层200的表面或底电极503表面。
在一些实施例中，如图15b所示，在掺杂单晶硅层200和压电谐振器500层的底电极503之间还形成有一层第一介质层801，以通过第一介质 层801实现底电极503与掺杂单晶硅层200之间的电性隔离；另外，在顶电极501的表面形成有一层第二介质层802，通过第二介质层802可以防止顶电极501的表面发生钝化。
其中，第一介质层801和第二介质层802的材料可以为氧化铝(Al2O3)、氮化铝(AlN)、氮化硅(Si3N4)或二氧化硅(SiO2)等绝缘材料。
在一些实施例中，压电驱动硅基谐振器的结构可以为悬臂梁、简支梁、音叉结构等具有多个梁组合结构的形式，也可以为其他平板型结构，其振动模式可以为Lamé(拉梅)模式、Lamb(兰姆波)模式、flexural(弯曲)模式等。
如图16和图17中所示，压电驱动硅基谐振器的结构为面外弯曲振动模式(out-of-plane flexural mode)和面内弯曲振动模式(in-plane flexural mode)的音叉对应的两种不同结构。
实施例二
本申请实施例中提供的半导体结构的制备方法中，仅在于提供的衬底结构不同于上述实施一中的衬底结构，在本申请实施例中，衬底101为SOI衬底。
具体的，在制备步骤S101之间，提供SOI衬底，其中，SOI衬底包括依次层叠设置的第二底硅层1011、埋氧层400和第二顶硅层103，第二顶硅层103和第二底硅层1011的材料为单晶硅，埋氧层400的材料可以为SiO2。
步骤S101：在衬底上通过外延生长方式形成重掺杂单晶硅层。
具体的，当提供SOI衬底后，在第二顶硅层103的表面通过外延生长的方式生长形成掺杂单晶硅层200，如图17中所示，其中，掺杂单晶硅层200的掺杂元素、掺杂类型与上述实施例一中的相同，在此不再赘述。
在一些实施例中，如图18和图19所示，在第二顶硅层103的表面通过外延生长的方式生长形成掺杂单晶硅层200后，在掺杂单晶硅层200的表面上生长形成热氧层。
在掺杂单晶硅层200的表面上生长形成热氧层后，将在掺杂单晶硅层200表面形成热氧层后的SOI衬底倒装并与形成有空腔的第一底硅层102 键合，使得第一底硅层102与SOI衬底键合后形成开口封闭的空腔。注意，也可以不生长热氧层，而直接采用硅-硅键合使准备好的两块衬底相键合，类似图6；或在掺杂单晶硅层200表面图形化一层二氧化硅层后，在空腔外部仍采用硅-硅键合工艺，类似图7b所示情况。
在图20中，SOI衬底倒装并与表面上没有生长热氧层的第一底硅层102键合。
在图21中，SOI衬底倒装并与表面上生长形成有热氧层的第一底硅层102键合。
图22中，在第二顶硅层103的表面上没有生长热氧层，只在第一底硅层102的表面生长形成热氧层，这样，SOI衬底倒装后与表面上生长形成有热氧层的第一底硅层102键合。
在一些实施例中，去除至少部分衬底101，具体包括：依次去除第二底硅层1011和埋氧层400。
在另一些实施例中，去除至少部分衬底101，具体包括：依次去除第二底硅层1011、埋氧层400和第二顶硅层103。
在一些实施例中，依次去除所述SOI衬底中的所述第二底硅层1011、所述埋氧层400和所述第二顶硅层103，具体包括：通过化学机械抛光和湿法刻蚀的方式去除第二底硅层1011。
也就是说，可以通过化学机械抛光和湿法刻蚀的方式将第二底硅层1011全部去除，并暴露埋氧层400，如图23中所示。
可以理解的是，在通过化学机械抛光和湿法刻蚀的方式去除第二底硅层1011时，埋氧层400相当于刻蚀阻挡层，这样，当刻蚀到埋氧层400时便停止刻蚀，从而可以避免对埋氧层400下面的第二顶硅层103造成刻蚀损伤，因此，通过在第二底硅层1011和第二顶硅层103之间设置埋氧层400，可以更好的控制衬底101厚度的精确度。
在一些实施例中，去除第二底硅层1011之后，可以通过氢氟酸(HF)溶液去除所述埋氧层400，如图24中所示，以暴露第二顶氧层。
在一些实施例中，去除埋氧层400之后，还可以通过化学机械抛光(CMP)工艺去除部分或者全部第二顶硅层103；例如，在图25中，通过化学机械抛光去除全部第二顶硅层103，以暴露掺杂单晶硅层200，之后 在掺杂单晶硅层200上进一步加工例如压电谐振器500层等结构。
通过化学机械抛光的方式去除第二顶硅层103，可以保证掺杂单晶硅层200表面的粗糙度的精度较高。
上述方案中，通过将衬底101的结构设置为SOI衬底，可以更好的控制半导体结构的厚度的精确度。
另外，半导体结构的其他制备工艺与上述实施例一中的制备工艺相同，在此不再赘述。
实施例三
如图15a和图15b所示，本申请实施例提供一种半导体结构，包括：第一底硅层102、薄膜硅层，通过键合形成于第一底硅层102表面，薄膜硅层至少包含部分通过外延生长方式形成的掺杂单晶硅层200，掺杂单晶硅层200位于薄膜硅层中靠近第一底硅层102的位置，且掺杂单晶硅层200为重掺杂层。
在一些实施例中，半导体结构还包括压电谐振器500层和上硅帽700，其中，掺杂单晶硅层200、压电谐振器500层和上硅帽700层沿第一底硅层102的厚度方向依次层叠设置在第一底硅层102上，掺杂单晶硅层200设置在靠近第一底硅层102的一侧。
在一些实施例中，第一底硅层102的材料可以为单晶硅，且第一底硅层102面向掺杂单晶硅层200的一侧设置有空腔。
压电谐振器500形成于掺杂单晶硅层200的表面，上硅帽700键合于压电谐振器500上，以形成例如压电驱动硅基谐振器的半导体结构。
在一些实施例中，掺杂单晶硅层200为N型重掺杂单晶硅层200或P型重掺杂单晶硅层200，其中，掺杂单晶硅层200是在通过例如外延生长的同时进行硅层掺杂，掺杂单晶硅层200的掺杂离子的元素可以为B、As或者P等。
为了能够使压电谐振器500的性能得到提升，在本申请实施例中，可以使掺杂单晶硅层200的掺杂浓度随生长厚度而变化，这样，可以对掺杂单晶硅层200的掺杂浓度进行灵活且精确的调控，使得掺杂单晶硅层200的掺杂浓度能够达到目标掺杂浓度，例如，目标掺杂浓度的范围可以为大 于1×1018cm-3，优选范围可以为1×1019到1021cm-3，但不限于该范围，也可以为更高掺杂浓度范围，以使得半导体结构能够实现零温漂特性，即温度系数能够接近零，温度性能更稳定，从而能够使半导体结构的性能得到提升，从而提升半导体结构的良率。
在一些实施例中，掺杂单晶硅层200具有至少两个沿生长厚度方向层叠设置的子掺杂单晶硅层，不同子掺杂单晶硅层具有不同的掺杂浓度，如图12中所示，掺杂单晶硅层200包括第一子掺杂单晶硅层201、第二子掺杂单晶硅层202和第三子掺杂单晶硅层203，其中，第一子掺杂单晶硅层201的表面生长形成于热氧层上，可以理解的是，第一子掺杂单晶硅层201、第二子掺杂单晶硅层202和第三子掺杂单晶硅层203的掺杂浓度不同。
在一些实施例中，各子掺杂单晶硅层的掺杂浓度随生长厚度方向由大到小依次排列。例如，掺杂浓度可以是由第一子掺杂单晶硅层201到第三子掺杂单晶硅层203依次由大到小排列。
或者，掺杂浓度也可以是由第三子掺杂单晶硅层203到第一子掺杂单晶硅层201依次由大到小排列，具体根据掺杂浓度的需求进行适应性设置，在此不做具体限制。
上述方案中，通过使各子掺杂单晶硅层的掺杂浓度呈梯度变化，这样，各子掺杂单晶硅层的厚度和掺杂浓度可以进行调控，以使得掺杂单晶硅层200的掺杂浓度能够进行灵活且精确的控制，使得半导体结构能够实现零温漂特性，即温度系数能够接近零，温度性能更稳定，从而能够使半导体结构的性能得到提升，进而提升半导体结构的良率。
在另一些实施例中，掺杂单晶硅层200的掺杂浓度可随生长厚度而连续变化，如图13中所示，可以理解的是，通过使掺杂单晶硅层200的掺杂浓度随生长厚度而连续变化，以使得掺杂单晶硅层200的掺杂浓度能够达到目标掺杂浓度，使得半导体结构能够实现零温漂特性，即温度系数能够接近零，温度性能更稳定，从而能够使半导体结构的性能得到提升，从而提升半导体结构的良率。
在一些实施例中，掺杂单晶硅层200和第一底硅层102之间可以通过键合的方式形成，为了提高掺杂单晶硅层200与第一底硅层102之间的键合可靠性，请继续参照图14，还包括热氧层301，即热氧层301设置于第一底硅 层102和掺杂单晶硅层200之间，这样，热氧层301可以作为粘接层设置在第一底硅层102与掺杂单晶硅层200之间，从而能够提高第一底硅层102和掺杂单晶硅层200之间的粘接性。
在一些实施例中，热氧层可以覆盖空腔的和掺杂单晶硅层200相对的一侧腔壁，如图9中所示。
在另一些实施例中，热氧层覆盖掺杂单晶硅层200的与空腔对应的一侧表面，如图7a中所示。
在又一些实施例中，热氧层覆盖空腔的腔壁以及掺杂单晶硅层200的与空腔对应的一侧表面，如图8中所示。
在一些实施例中，压电谐振器500层包括在掺杂单晶硅层200表面依次层叠设置的底电极503、压电层502和顶电极501。
在一些实施例中，压电层502的材质可以为氮化铝、多晶氮化铝、稀土元素掺杂氮化铝中的任一种。
示例性的，压电层502的材质为稀土元素掺杂氮化铝；其中，稀土元素掺杂氮化铝包括钪(Sc)、钇(Y)、镁(Mg)、钛(Ti)、镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)、镥(Lu)中的至少一种。
在一些实施例中，底电极503与薄膜硅层之间还可以设置有介质层，介质层的材质可以二氧化硅、氮化硅、氧化铝、氮化铝中的任一种。
在一些实施例中，上硅帽700可通过键合的方式设置在压电谐振器500的顶电极501上，为了提升上硅帽700与顶电极501之间的键合可靠性，在本申请实施例中，上硅帽700和顶电极501之间设置有第一键合层600，通过第一键合层600实现上硅帽700与顶电极501之间的键合，从而提高其键合可靠性。
在一些实施例中，请继续参照图15a和图15b所示，上硅帽700包括基底701和第二键合层702，第二键合层702设置在基底701面向所述第一键合层600的一侧；基底701上还设置有贯穿基底701和第二键合层702的导电通孔704，上硅帽700背离第二键合层702的一侧设置有与导电通孔704电连接的金属引脚703，基底701面向顶电极501的一侧还设置有吸气剂层705，其材料可以为钛(Ti)以及钛合金，锆(Zr)以及锆合金等。其中，基 底701的材料可以为单晶硅等。在另一些实施例中(未在图中示出)，第二键合层702以及导电通孔704的导电层与基底701接触的表面还设置有通过热氧或化学气相沉积生成的SiO2层作为绝缘层，使得第二键合层702以及导电通孔704的导电层不直接与基底701接触，从而提高器件输入、输出以及接地端口间隔离特性
通过在基底701面向第一键合层600的一侧设置第二键合层702，以使得上硅帽700与顶电极501之间通过第一键合层600和第二键合层702实现键合，从而能够进一步提高上硅帽700与顶电极501之间的键合可靠性。其中，第二键合层702的材料可以为金、铝、锗、铜、锡、钛或以上金属的复合层或其合金等，具体可选择与第一键合层600的材料相匹配的材料，即第一键合层600和第二键合层702可以进行热压键合，例如，第一键合层600和第二键合层702相匹配的键合材料可以为：金-金键合、铝-锗键合、铜-铜键合、铜-金-铜键合、铜-锡键合、铜-锡-金键合等。
在一些实施例中，上硅帽700上还设置有贯穿基底701和第二键合层702的通孔，通孔的孔壁上附着有一层导电层，通孔与表面的导电层形成导电通孔704，其中，导电通孔704中导电层的材料可以为铜、金、铝、铝硅铜合金等材料或其复合层。
另外，金属引脚703的材料金、铝、铜、钛、铱、锇、铬或以上金属的复合或其合金。
可以理解的是，上述方案中形成的半导体结构可以通过金属引脚703与其他器件实现电连接。
在一些实施例中，请继续参照图15a和图15b所示，上硅帽700上具有刻蚀出的凸起结构和容纳器件的上空腔结构，其中，第二键合层702位于凸起结构上，而吸气剂层705位于空腔内部。在另一些未示出的实施例中，上硅帽中也可以没有刻蚀出的空腔结构和/或凸起结构，而使得上硅帽700面向器件一侧为平整表面，此时仅通过键合层形成容纳器件的上空腔结构。
本申请实施例还提供一种电子设备，包括上述实施例中提供的半导体结构。
本申请实施例提供的半导体结构的制备方法，包括：在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层；在第一底硅层上形成空腔；将衬底倒 装后，使掺杂单晶硅层与第一底硅层键合；去除至少部分衬底，以在第一底硅层上形成薄膜硅层；其中，薄膜硅层至少包含部分厚度的掺杂单晶硅层。上述方案中，在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层，这样，可以提高半导体结构的硅层掺杂浓度，且掺杂浓度可调可控性好，从而能够提升半导体结构的性能一致性和良率。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (37)

  1. 一种半导体结构的制备方法，其特征在于，包括：
    在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层；
    在第一底硅层上形成空腔；
    将所述衬底倒置后，使所述掺杂单晶硅层与所述第一底硅层键合；
    去除至少部分所述衬底，以在第一底硅层上形成薄膜硅层；其中，所述薄膜硅层至少包含部分厚度的所述掺杂单晶硅层。
  2. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层的步骤中，具体包括：
    在所述衬底上形成掺杂浓度随生长厚度而变化的所述掺杂单晶硅层。
  3. 根据权利要求2所述的半导体结构的制备方法，其特征在于，所述掺杂单晶硅层具有至少两个沿生长厚度方向层叠设置的子掺杂单晶硅层，不同所述子掺杂单晶硅层具有不同的掺杂浓度和/或不同的掺杂剂。
  4. 根据权利要求3所述的半导体结构的制备方法，其特征在于，各所述子掺杂单晶硅层的掺杂浓度随所述生长厚度方向由大到小或由小到大依次排列。
  5. 根据权利要求2所述的半导体结构的制备方法，其特征在于，所述掺杂单晶硅层的掺杂浓度随生长厚度而连续变化。
  6. 根据权利要求1-5中任一项所述的半导体结构的制备方法，其特征在于，所述掺杂单晶硅层的掺杂浓度大于所述衬底掺杂浓度，所述掺杂单晶硅层为N型重掺杂单晶硅层或P型重掺杂单晶硅层；其中，所述掺杂单晶硅层的掺杂浓度大于或等于1019cm-3。
  7. 根据权利要求6所述的半导体结构的制备方法，其特征在于，所述掺杂单晶硅层的掺杂浓度大于或等于1020cm-3。
  8. 根据权利要求1-5中任一项所述的半导体结构的制备方法，其特征在于，所述将所述衬底倒置后和所述第一底硅层键合之前，还包括：
    在所述掺杂单晶硅层和所述第一底硅层的至少一者上形成热氧层。
  9. 根据权利要求1-5中任一项所述的半导体结构的制备方法，其特征在于，所述衬底包括第一顶硅层，所述掺杂单晶硅层形成于所述第一顶硅层表面。
  10. 根据权利要求9所述的半导体结构的制备方法，其特征在于，所述去除至少部分所述衬底，具体包括：减薄所述第一顶硅层的厚度；或者，去除所述第一顶硅层。
  11. 根据权利要求1-5中任一项所述的半导体结构的制备方法，其特征在于，所述在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层，具体包括：
    对于包括依次层叠设置的第二顶硅层、埋氧层和第二底硅层的SOI衬底，在所述SOI衬底的第二顶硅层上外延生长重掺杂的所述掺杂单晶硅层。
  12. 根据权利要求11所述的半导体结构的制备方法，其特征在于，所述去除至少部分所述衬底，具体包括：
    依次去除所述第二底硅层和所述埋氧层；或者，依次去除所述第二底硅层、所述埋氧层和至少部分所述第二顶硅层。
  13. 根据权利要求1-5中任一项所述的半导体结构的制备方法，其特征在于，所述去除至少部分所述衬底，具体包括：
    去除全部所述衬底和部分所述掺杂单晶硅层。
  14. 根据权利要求1-5中任一项所述的半导体结构的制备方法，其特征在于，在衬底上通过外延生长方式形成重掺杂的掺杂单晶硅层后，或在第一底硅层上形成薄膜硅层后，还包括：
    通过离子注入或热扩散方式对所述掺杂单晶硅层或薄膜硅层进行掺杂；和/或者，
    对所述掺杂单晶硅层或薄膜硅层进行高温退火。
  15. 根据权利要求14所述的半导体结构的制备方法，其特征在于，若所述掺杂单晶硅层或薄膜硅层的掺杂浓度小于预设掺杂浓度，则通过离子注入或热扩散方式对所述掺杂单晶硅层或所述薄膜硅层进行硅层掺杂，或者对所述掺杂单晶硅层或薄膜硅层进行高温退火，以提高掺杂单晶硅层或薄膜硅层的掺杂浓度；若所述掺杂单晶硅层或薄膜硅层的掺杂浓度大于预设掺杂浓度，对所述掺杂单晶硅层或薄膜硅层进行高温退火，以减小所述掺杂单晶硅层或薄膜硅层的掺杂浓度。
  16. 根据权利要求1-5中任一项所述的半导体结构的制备方法，其特征在于，所述去除至少部分所述衬底，以在第一底硅层上形成薄膜硅层之后， 还包括：
    在所述薄膜硅层的表面形成压电谐振器层。
  17. 根据权利要求16所述的半导体结构的制备方法，其特征在于，所述在所述薄膜硅层的表面形成压电谐振器层之后，还包括：
    将上硅帽键合至所述压电谐振器层。
  18. 一种半导体结构，其特征在于，包括：
    第一底硅层，具有空腔；
    薄膜硅层，通过键合形成于所述第一底硅层表面，所述薄膜硅层至少包含部分通过外延生长方式形成的掺杂单晶硅层，所述掺杂单晶硅层位于薄膜硅层中靠近第一底硅层的位置，且所述掺杂单晶硅层为重掺杂层。
  19. 根据权利要求18所述的半导体结构，其特征在于，所述掺杂单晶硅层为N型重掺杂单晶硅层或P型重掺杂单晶硅层，且所述掺杂单晶硅层的掺杂浓度大于或等于1019cm-3。
  20. 根据权利要求19所述的半导体结构，其特征在于，所述掺杂单晶硅层的掺杂浓度随生长厚度而变化。
  21. 根据权利要求20所述的半导体结构，其特征在于，所述掺杂单晶硅层具有至少两个沿生长厚度方向层叠设置的子掺杂单晶硅层，不同所述子掺杂单晶硅层具有不同的掺杂浓度和/或不同的掺杂剂。
  22. 根据权利要求21所述的半导体结构，其特征在于，各所述子掺杂单晶硅层的掺杂浓度随所述生长厚度方向由大到小或由小到大依次排列。
  23. 根据权利要求20所述的半导体结构，其特征在于，所述掺杂单晶硅层的掺杂浓度随生长厚度而连续变化。
  24. 根据权利要求18所述的半导体结构，其特征在于，还包括热氧层，所述热氧层设置于所述第一底硅层和所述掺杂单晶硅层之间。
  25. 根据权利要求24所述的半导体结构，其特征在于，所述热氧层覆盖所述空腔的与所述掺杂单晶硅层相对的一侧腔壁。
  26. 根据权利要求24所述的半导体结构，其特征在于，所述热氧层覆盖所述掺杂单晶硅层的与所述空腔对应的一侧表面。
  27. 根据权利要求24所述的半导体结构，其特征在于，所述热氧层覆盖所述空腔的腔壁以及所述掺杂单晶硅层的与所述空腔对应的一侧表面。
  28. 根据权利要求18所述的半导体结构，其特征在于，还包括：
    压电谐振器层，形成于所述薄膜硅层表面；
    上硅帽，键合于所述压电谐振器层上。
  29. 根据权利要求28所述的半导体结构，其特征在于，所述压电谐振器层包括在所述薄膜硅层表面依次层叠设置的压电层和顶电极。
  30. 根据权利要求29所述的半导体结构，其特征在于，所述压电谐振器还包括底电极，所述底电极设置于所述压电层背离所述顶电极的一侧。
  31. 根据权利要求30所述的半导体结构，其特征在于，所述底电极与所述薄膜硅层之间设置有介质层，所述介质层为二氧化硅、氮化硅、氧化铝、氮化铝中的至少一种。
  32. 根据权利要求29所述的半导体结构，其特征在于，所述压电层包括单晶氮化铝、多晶氮化铝、稀土元素掺杂氮化铝中的任一种；其中，所述稀土元素掺杂氮化铝包括钪、钇、镁、钛、镧、铈、镨、钕、钷、钐、铕、钆、铽、镝、钬、铒、铥、镱、镥中的至少一种。
  33. 根据权利要求29所述的半导体结构，其特征在于，所述上硅帽和所述压电层之间设置有第一键合层。
  34. 根据权利要求33所述的半导体结构，其特征在于，所述上硅帽包括基底和第二键合层，所述第二键合层设置在所述基底面向所述第一键合层的一侧；
    所述基底上还设置有贯穿所述基底和所述第二键合层的导电通孔，上硅帽背离所述第二键合层的一侧设置有与所述导电通孔电连接的金属引脚，所述基底面向所述压电谐振器层的一侧还设置有吸气剂层。
  35. 根据权利要求34所述的半导体结构，其特征在于，所述第一键合层和所述第二键合层均为金属层。
  36. 根据权利要求35所述的半导体结构，其特征在于，所述金属引脚和所述导电通孔与所述基底之间均设置有二氧化硅层。
  37. 一种电子设备，其特征在于，包括权利要求18-36中任一项所述的半导体结构。
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