CN105990312A - 半导体器件及其晶圆级封装 - Google Patents

半导体器件及其晶圆级封装 Download PDF

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Publication number
CN105990312A
CN105990312A CN201610099033.5A CN201610099033A CN105990312A CN 105990312 A CN105990312 A CN 105990312A CN 201610099033 A CN201610099033 A CN 201610099033A CN 105990312 A CN105990312 A CN 105990312A
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Prior art keywords
pad
metal gasket
wafer
semiconductor device
upper metal
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CN201610099033.5A
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CN105990312B (zh
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许仕逸
谢东宪
周哲雅
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供一种半导体器件，包括集成电路裸晶、钝化层和重布线层结构。集成电路裸晶具有主动表面，在主动表面上设有至少一第一片上金属垫和第二片上金属垫，第一片上金属垫邻近第二片上金属垫。钝化层位于主动表面上，且覆盖第一片上金属垫和第二片上金属垫。重布线层结构位于钝化层上。重布线层结构包括第一着垫，位于第一片上金属垫的上方；第一导孔，位于重布线层结构中，电连接第一着垫与第一片上金属垫；第二着垫，位于第二片上金属垫的上方；第二导孔，位于重布线层结构中，电连接第二着垫与第二片上金属垫；以及至少三条线路，设于重布线层结构上，并通过第一着垫与第二着垫之间的空间。本发明还提供一种晶圆级封装，可提高信号完整性。

Description

半导体器件及其晶圆级封装
技术领域
本发明有关于一种半导体器件及封装，具有微细的(fine)重布线层(redistribution layer,RDL)间距(pitch)以及较佳的信号完整性(signal integrity)。
背景技术
为了降低成本及封装尺寸，封装业界已发展出各种不同的技术及方法。晶圆级封装(Wafer Level Packaging，WLP)即是其中之一。所谓的晶圆级封装，是在整片晶圆生产完成后，直接在晶圆上进行封装测试，之后才切割制成单颗芯片。
例如，本领域公知的扇出型晶圆级封装(Fan-Out Wafer Level Packaging,FOWLP)，可以将并排组态的至少两个集成电路(integrated circuit,IC)裸晶(die)整合到一模封(molded)的半导体封装中，该半导体封装具有扇出式的重布线层(redistribution layer，RDL)和后钝化互连(post passivation interconnection，PPI)结构。两个集成电路裸晶可以通过重布线层(RDL)彼此互连。相较于现有的覆晶球栅数组(flip-chip ball grid array,FCBGA)封装，扇出型晶圆级封装能提供较优的外形尺寸、引脚数及散热性能。
然而，随着越来越多的功能被整合到单个的集体电路裸晶，裸晶至裸晶(die-to-die)信号数急剧增加。增加的裸晶至裸晶信号数导致重布线层(RDL)的绕线空间受到挤压。目前，由于每个着垫(landing pad)具有相对较大的尺寸，因此，在两个相邻的着垫之间最多仅能容纳三到四条信号线路(signal trace)。如此一来，就没有足够的空间用于布设屏蔽线路(shielding trace)。由于信号间的串扰，这对高速应用的信号完整性有不利地影响。
因此，本技术领域需要一种改良的晶圆级封装，以具有微细的重布线层间距和较佳的信号完整性。
发明内容
本发明的主要目的即在于提供一种改良的半导体器件及其封装，以解决上述问题。
本发明一方面提出一种半导体器件，该半导体器件包括集成电路裸晶、钝化层和重布线层结构。该集成电路裸晶具有主动表面，其中在该主动表面上设有至少一第一片上金属垫(on-chip metal pad)和第二片上金属垫，且该第一片上金属垫邻近该第二片上金属垫。该钝化层位于该主动表面上，且覆盖该第一片上金属垫以及该第二片上金属垫。该重布线层结构位于该钝化层上。该重布线层结构包括第一着垫，位于该第一片上金属垫的上方；第一导孔，位于该重布线层结构中，电连接该第一着垫与该第一片上金属垫；第二着垫，位于该第二片上金属垫的上方；第二导孔，位于该重布线层结构中，电连接该第二着垫与该第二片上金属垫；以及至少三条线路，设于该重布线层结构上，并通过该第一着垫与该第二着垫之间的空间(space)。
本发明另一方面提出一种晶圆级封装，其包括集成电路裸晶、钝化层、成型材料和重布线层结构。该集成电路裸晶具有主动表面，其中在该主动表面上设有至少一第一片上金属垫和第二片上金属垫，且该第一片上金属垫邻近该第二片上金属垫。该钝化层位于该主动表面上，且覆盖该第一片上金属垫以及该第二片上金属垫。该成型材料包覆除该主动表面外的该集成电路裸晶。该重布线层结构位于该钝化层以及该成型材料上。该重布线层结构包括第一着垫，位于该第一片上金属垫的上方；第一导孔，位于该重布线层结构中，电连接该第一着垫与该第一片上金属垫；第二着垫，位于该第二片上金属垫的上方；第二导孔，位于该重布线层结构中，电连接该第二着垫与该第二片上金属垫；以及至少三条线路，位于该重布线层结构上，并通过该第一着垫与该第二着垫之间的空间。
本发明提供了一种半导体器件及其晶圆级封装，可用于提高信号完整性。
为让本发明之上述目的、特征及优点能更明显易懂，下文特举较佳实施方式，并配合所附图式，作详细说明如下。然而如下之较佳实施方式与图式仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
附图系提供本发明更进一步的了解，并构成本说明书的一部分。附图与说明书内容一同阐述之本发明实施例系有助于解释本发明的原理原则。在附图中：
图1为依据本发明一实施例示出的一种扇出型晶圆级封装的剖面示意图；
图2为根据本发明一实施例所绘示的重布线层结构中的部分铝垫、铜导孔、线路及着垫的透视平面图；
图3是沿图2中I-I’线截取的示意剖面图；
图4为根据本发明另一实施例所绘示的重布线层中的部分铝垫、铜导孔、线路及着垫的透视平面图。
具体实施方式
在以下详细描述中，请参考附图，这些附图构成本揭露书的一部分，其用来辅助说明并例示本发明的具体实施方案。这些实施方案被详细地描述以使本领域的技术人员能够实践本发明。当然，其他实施例也可以被利用，且在不脱离本发明的范围下，可以做出结构上的变化。
因此，以下的详细描述，不应被视为具有限制意义，并且本发明的范围应由所附权利要求书所定义，其发明内容应同时考虑等效物的全部范围。
本发明的一个或多个实施方案将参照附图描述，其中以相同标号来表示相同元件，且其中例示的结构不一定按比例绘制。以下，术语“裸晶”、“芯片”、“晶粒”、“晶片”、“半导体芯片”和“半导体裸晶”在整个说明书中均可互换使用。
图1为依据本发明一实施例示出的一种示例性的半导体器件封装的剖面示意图。半导体器件封装1可以是扇出型晶圆级封装(FOWLP)，具有被模封的多个集成电路(IC)裸晶，该多个集体电路裸晶以并排组态排列，但不限于此。虽然图中示出的是多个裸晶(multi-die)的晶圆级封装，但本领域技术人员应理解本发明亦可应用于单个裸晶(single-die)的封装。可以理解的是，半导体器件封装1也可被理解为一种半导体器件，但应当说明的是，对于半导体器件的情形，可以不包括成型材料20，其中，成型材料20用于封装半导体器件中所包括的集体电路裸晶。在一些实施例中，集体电路裸晶的主动表面未被成型材料20包覆(encapsulate)。
如图1所示，该示例性的半导体器件封装1包括以并排组态排列的两个集成电路裸晶102及104，且集成电路裸晶102及104被成型材料(molding material)20模封。例如，成型材料20可以是环氧树脂(epoxy)、树脂(resin)或其他合适的成型材料。集成电路裸晶102及104分别具有主动表面(active surface)102a及104a。在此示例图中，主动表面102a及104a均朝下。在主动表面102a及104a上分别设有片上金属垫(on-chip metal pad)122及142，例如铝垫，如片上金属垫122和/或142可以为铝垫。这些片上金属垫122及142分别被钝化层120及140所覆盖。根据所示出的实施例，钝化层120及140可以包括有氧化硅、氮化硅、氮氧化硅、未掺杂硅玻璃，或其组合。
可选地，可分别在钝化层120及140上直接形成介电覆盖层(dielectriccapping layer)124及144，从而提供平坦的主表面，该主表面与围绕在这两个集成电路裸晶102及104附近的成型材料20的一表面齐平。根据所示出的实施例，介电覆盖层124及144分别直接接触到钝化层120及140。根据所示出的实施例，介电覆盖层124及144可以包括高分子材料，例如聚酰亚胺(polyimide)、层叠胶带(laminating tape)、晶背研磨胶带(backside grinding tape)、黏着剂(adhesive)、紫外线胶带(UV tap)等等。
虽然在图中没有示出，但可以理解的是，集成电路裸晶102和104还可以分别包括在钝化层120及140下方的金属互连结构。例如，前述金属互连结构可以包括，但不限于，分布或镶嵌在介电覆盖层内的超低k介电层(ultra-low-kdielectric layer)、层间介质(inter-layer dielectric,ILD)层，以及多层铜金属层。所述金属互连结构可以形成在半导体基板上(如，硅基板)，多个半导体电路组件(如，晶体管)可位于该半导体基板中及其上方。为简化说明，此处省略钝化层120和140下方的内部结构细节。
在介电覆盖层124、144以及钝化层120、140中，可以形成开孔(opening)。各开孔使相应的片上金属垫122及142的上表面(top surface)的一部分显露出来。在这些开孔内，可以形成导电柱凸块(Conductive pillar bump)126及146，例如铜柱凸块或铜接触栓(copper contact plug)，以及，导电柱凸块126及146分别填补(fill up)片上金属垫122及142上的开孔，从而，导电柱凸块126及146分别与片上金属垫122及142相接触。需理解的是，在其它实施例中，可以省略介电覆盖层124、144以及导电柱凸柱块126、146。
在介电覆盖层124、144与围绕两个集成电路裸晶102、104的成型材料20上，形成有重布线层(RDL)结构200，通常用做信号扇出目的。根据所示出的实施例，举例来说，重布线层结构200可以包括多个绝缘层(insulating layer)201、203、205、207以及设于多个绝缘层201、203、205、207中及其上的多个金属层202、204、206。绝缘层201、203、205及207可以包含有机材料或高分子材料，包括，但不限于，聚酰亚胺(polyimide)、苯环丁烯(benzocyclobutene,BCB)、聚苯恶唑(polybenzoxazole，PBO)等等。在其它实施例中，绝缘层201、203、205及207可以包含无机材料。在一些实施例中，重布线层结构200的底面上可设有多个锡球250，用于进一步与外部连接。在本发明实施例中，至少三条线路(trace)位于重布线层结构上，这些线路通过第一着垫与第二着垫之间的空间。为方便理解，例如，在图3所示的示例中，五条线路位于重布线层结构400上。
举例来说，金属层202可包括电路特征(circuit feature)，如设在每个导电柱凸块126和146上方的导孔202a、着垫202b以及细(fine)线路202c，在绝缘层201上的细线路202c延伸并连通于导孔与着垫之间，或着垫与着垫之间。在图1中，由虚线310所指出的示例性区域可表示裸晶至裸晶(或，芯片至芯片)信号发送路径，其包括但不限于裸晶至裸晶金属垫122a和142a、导孔202a、位于金属垫及导孔上的着垫202b，以及着垫202b之间的细线路202c。在一些实施例中，着垫以及导孔可以由铜组成。
如前文所述，随着越来越多的功能被合并到一个单一的集成电路裸晶中，裸晶至裸晶信号数急剧增加，导致重布线层的绕线空间受到挤压。目前，在两个相邻着垫之间最多仅能容纳三到四条信号线路，这是由于各着垫具有相对较大的尺寸。如此一来，就没有足够的空间用于布设屏蔽线路。这对于高速应用的信号完整性有不利地影响，因为会有信号间的串扰。本发明解决了这个问题。
请参考图2及图3。图2为根据本发明一实施例所绘示的扇出型晶圆级封装(FOWLP)的部分重布线层结构的透视平面图。图3是沿图2中I-I’线截取的示意剖面图。为方便理解，上述实施例中的片上金属垫以铝垫(AP)为例，导孔以铜导孔为例，但应当说明的是，本发明并不限于此。如图2及图3所示，制作在集成电路裸晶100上的重布线层结构400可以包括两个相邻的片上(on-chip)铝垫(aluminum pad，AP)，以虚线301表示。铝垫(AP)可以被钝化层410覆盖。根据所示出的实施例，钝化层410可以包括氧化硅、氮化硅、氮氧化硅、未掺杂的硅玻璃，或它们的任意组合。在其它实施例中，钝化层410可以包括有机材料，例如聚酰亚胺等。但是应该理解的是，为进一步连接，如图1中所示，可以在钝化层410上形成更多的电介质层(dielectric layer)和金属层。
在钝化层410中可以形成开孔。每一个开孔可以暴露相应铝垫(AP)的顶面的(约略)中央部分。铜导孔(V)，以虚线302表示，可直接形成在每个铝垫(AP)上。在每个铜导孔(Ⅴ)上可以直接形成着垫(LP)。在图3所示出的实施例中，至少五条细线路S、G、S、G、S可通过两个相邻着垫(LP)之间的空间。五条细线路S、G、S、G、S可以包括铜线路，但并不限于此。类似地，从该晶圆级封装的上面(或顶部)看(或在俯视图中)，铜导孔(V)可具有矩形或卵形轮廓。此外，每个铜导孔(V)的长宽比可介于1～3之间，更特别地，介于2～3之间。
根据所示出的实施例，从该晶圆级封装的上面(或顶部)看时，每个铝垫(AP)或其中至少一个铝垫可呈矩形或呈卵形(为方便说明，以每个铝垫呈矩形或呈卵形为例)。每个铝垫(AP)可具有纵向长度L1和宽度W1。根据所示出的实施例，每个铝垫(AP)的纵向方向是平形于参考y轴，其可以是如图1中的两个集成电路裸晶102和104之间的信号传输方向(裸晶至裸晶方向)。每个铝垫(AP)的长宽比(aspect ratio)被定义为L1/W1，其可介于1～3之间，更特别地，介于2～3之间。举例来说，宽度W1可以是二分之一的纵向长度L1，但不限于此。在一些实施例中，宽度W1可以小于二分之一的纵向长度L1，但并不限于此。举例来说，纵向长度L1的范围可以在35～55微米，例如45微米，宽度W1的范围可以在15～30微米，例如20微米。
根据所示出的实施例，从该晶圆级封装的上面(或顶部)看时，每个着垫(LP)或其中至少一个着垫呈矩形或卵形(为方便说明，以每个着垫呈矩形或呈卵形为例)。每个着垫(LP)的纵向方向是平形于参考y轴，其可以是如图1中的两个集成电路裸晶102和104之间的信号传输方向(裸晶至裸晶方向)。每个着垫(LP)的长宽比被定义为L2/W2，其可介于1～3之间，更特别地，介于2～3之间。宽度W2可以是二分之一的纵向长度L2，但不限于此。在一些实施例中，宽度W2可以小于二分之一的纵向长度L2，但并不限于此。举例来说，纵向长度L2的范围可以在30～50微米，例如40微米，宽度W2的范围可以在10～25微米，例如18微米。
根据所示出的实施例，两个相邻着垫(LP)之间的五条细线路S、G、S、G、S是沿参考y轴(或裸晶至裸晶方向)延伸的，用来传送裸晶至裸晶信号。根据所示出的实施例，两条细线路G可以传输接地信号，且可以用作两条相邻高速信号线路(例如，图中标示为S的细线路)之间的屏蔽线路。术语“SGS”可以指一电路布局结构，其包括中介参考(例如接地)线路G，线路G被一对高速或高频信号线路S(例如，操作在大于1Gb/s的速度上)夹着(sandwiched)。术语“SGSGS”可以指两条中介参考线路G介于三条高速或高频信号线路S之间，换言之，中介参考线路G设置在相邻的高频信号线路S之间。通过提供这样的结构，可以进一步显著地改善(提高)信号完整性。
根据所示出的实施例，钝化层410下的重布线层还可以设在两个铝垫(AP)之间。举例来说，在图3中，可以提供至少四条铝线路(AT)，沿参考y轴(或裸晶至裸晶方向)延伸。本发明的优点在于，因为着垫(LP)和/或铝垫(AP)，特别是位于图1中的虚线310所示的区域内者，从封装的上面(或顶部)看时(或在俯视图中)呈矩形或卵形，因此它们之间的空间被加宽，从而可容纳更多的重布线层线路。在图2、图3中所示的SGSGS线路组态能提高在重布线层层级的信号完整性。
图4为根据本发明另一实施例所绘示的重布线层中的部分铝垫、铜导孔、线路及着垫的透视平面图。如图4所示，相对于图2中的着垫，图4中的着垫(LP)具有更纤细的形状，它具有纵向长度L3，其大于L2；以及宽度W3，其比W2小。由于图4中的着垫(LP)具有更纤细的形状，两个相邻的着垫(LP)之间的空间被进一步拓宽。因此，更多的重布线层线路可以布置在该空间，提高信号完整性。例如，图4中例示七条线路，标记为SGSGSGS，包括四条高速信号线路和三条参考或接地线路。根据所示出的实施例，图4中的着垫(LP)与图2中所示的着垫(LP)基本上具有相同的表面积。在一些情况下，铜导孔(V)的部分边界，其以虚线302标示，可与着垫(LP)的周缘或边界部分重叠。
以上所述仅为本发明之较佳实施例，凡依本发明权利要求所做之均等变化与修饰，皆应属本发明之涵盖范围。

Claims (28)

1.一种半导体器件，其特征在于，包括：
集成电路裸晶，具有主动表面，在该主动表面上设有至少一第一片上金属垫和第二片上金属垫，且该第一片上金属垫邻近该第二片上金属垫；
钝化层，位于该主动表面上，且覆盖该第一片上金属垫以及该第二片上金属垫；以及
重布线层结构，位于该钝化层上，该重布线层结构包括：
第一着垫，位于该第一片上金属垫的上方；
第一导孔，位于该重布线层结构中，电连接该第一着垫与该第一片上金属垫；
第二着垫，位于该第二片上金属垫的上方；
第二导孔，位于该重布线层结构中，电连接该第二着垫与该第二片上金属垫；以及
至少三条线路，位于该重布线层结构上，并通过该第一着垫与该第二着垫之间的空间。
2.如权利要求1所述的半导体器件，其特征在于，该第一片上金属垫和该第二片上金属垫中的至少一个为铝垫。
3.如权利要求1所述的半导体器件，其特征在于，该钝化层包含氧化硅、氮化硅、氮氧化硅、未掺杂硅玻璃，或其任意组合。
4.如权利要求1所述的半导体器件，其特征在于，该第一着垫以及该第一导孔由铜组成；和/或，该第二着垫以及该第二导孔由铜组成。
5.如权利要求1所述的半导体器件，其特征在于，该至少三条线路包括两条中介参考线路G以及三条高速信号线路S，其中，该两条中介参考线路G介于该三条高速信号线路S之间，从而构成一SGSGS重布线层线路组态。
6.如权利要求5所述的半导体器件，其特征在于，该高速信号线路S在大于1Gb/s的速度下操作。
7.如权利要求5所述的半导体器件，其特征在于，该两条中介参考线路G传输接地信号。
8.如权利要求1所述的半导体器件，其特征在于，从该半导体器件的顶部看时，该第一着垫以及该第二着垫中的至少一个具有矩形或卵形轮廓。
9.如权利要求8所述的半导体器件，其特征在于，该第一着垫以及该第二着垫的长宽比均介于1至3之间。
10.如权利要求1所述的半导体器件，其特征在于，从该半导体器件的顶部看时，该第一片上金属垫以及该第二片上金属垫中的至少一个具有矩形或卵形轮廓。
11.如权利要求10所述的半导体器件，其特征在于，该第一片上金属垫以及该第二片上金属垫的长宽比均介于1至3之间。
12.如权利要求10所述的半导体器件，其特征在于，该第一片上金属垫以及该第二片上金属垫之间具有至少四条沿着裸晶至裸晶方向布设的铝线路。
13.如权利要求1所述的半导体器件，其特征在于，该钝化层在该第一片上金属垫以及该第二片上金属垫的对应位置上分别设有开孔，以使该第一片上金属垫以及该第二片上金属垫的一部分从该钝化层显露出来。
14.如权利要求13所述的半导体器件，其特征在于，该开孔内形成有导电柱凸块，以电连接相应的片上金属垫和导孔。
15.一种晶圆级封装，其特征在于，包括：
集成电路裸晶，具有主动表面，其中，在该主动表面上设有至少一第一片上金属垫和第二片上金属垫，且该第一片上金属垫邻近该第二片上金属垫；
钝化层，位于该主动表面上，且覆盖该第一片上金属垫以及该第二片上金属垫；
成型材料，包覆除该主动表面外的该集成电路裸晶；以及
重布线层结构，位于该钝化层以及该成型材料上，该重布线层结构包括：
第一着垫，位于该第一片上金属垫的上方；
第一导孔，位于该重布线层结构中，电连接该第一着垫与该第一片上金属垫；
第二着垫，位于该第二片上金属垫的上方；
第二导孔，位于该重布线层结构中，电连接该第二着垫与该第二片上金属垫；以及
至少三条线路，位于该重布线层结构上，并通过该第一着垫与该第二着垫之间的空间。
16.如权利要求15所述的晶圆级封装，其特征在于，该第一片上金属垫和该第二片上金属垫中的至少一个为铝垫。
17.如权利要求15所述的晶圆级封装，其特征在于，该钝化层包含氧化硅、氮化硅、氮氧化硅、未掺杂硅玻璃，或其任意组合。
18.如权利要求15所述的晶圆级封装，其特征在于，该第一着垫以及该第一导孔由铜组成；和/或，该第二着垫以及该第二导孔由铜组成。
19.如权利要求15所述的晶圆级封装，其特征在于，该至少三条线路包含两条中介参考线路G以及三条高速信号线路S，其中该两条中介参考线路G介于该三条高速信号线路S之间，如此构成SGSGS重布线层线路组态。
20.如权利要求19所述的晶圆级封装，其特征在于，该高速信号线路S在大于1Gb/s的速度下操作。
21.如权利要求19所述的晶圆级封装，其特征在于，该两条中介参考线路G传输接地信号。
22.如权利要求15所述的晶圆级封装，其特征在于，从该晶圆级封装的顶部看时，该第一着垫以及该第二着垫中的至少一个具有矩形或卵形轮廓。
23.如权利要求22所述的晶圆级封装，其特征在于，该第一着垫以及该第二着垫的长宽比均介于1至3之间。
24.如权利要求15所述的晶圆级封装，其特征在于，从该晶圆级封装的顶部看时，该第一片上金属垫以及该第二片上金属垫中的至少一个具有矩形或卵形轮廓。
25.如权利要求24所述的晶圆级封装，其特征在于，该第一片上金属垫以及该第二片上金属垫的长宽比均介于1至3之间。
26.如权利要求24所述的晶圆级封装，其特征在于，该第一片上金属垫以及该第二片上金属垫之间具有至少四条沿着裸晶至裸晶方向布设的铝线路。
27.如权利要求15所述的晶圆级封装，其特征在于，该钝化层在该第一片上金属垫以及该第二片上金属垫的对应位置上分别设有一开孔，以使该第一片上金属垫以及该第二片上金属垫的一部分从该钝化层显露出来。
28.如权利要求27所述的晶圆级封装，其特征在于，该开孔内形成有导电柱凸块，以电连接相应的片上金属垫和导孔。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107919330A (zh) * 2016-10-07 2018-04-17 联发科技股份有限公司 半导体芯片封装
CN115360170A (zh) * 2022-10-19 2022-11-18 睿力集成电路有限公司 一种半导体结构及其形成方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9431600B2 (en) * 2014-10-06 2016-08-30 International Business Machines Corporation Magnetic domain wall shift register memory devices with high magnetoresistance ratio structures
CN105514071B (zh) * 2016-01-22 2019-01-25 中芯长电半导体（江阴）有限公司 一种扇出型芯片的封装方法及封装结构
TWI649856B (zh) * 2016-05-13 2019-02-01 精材科技股份有限公司 晶片封裝體與其製造方法
US9842810B1 (en) * 2016-06-08 2017-12-12 Globalfoundries Inc. Tiled-stress-alleviating pad structure
US10276382B2 (en) 2016-08-11 2019-04-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and stacked package assemblies including high density interconnections
TWI623049B (zh) * 2016-11-04 2018-05-01 英屬開曼群島商鳳凰先驅股份有限公司 封裝基板及其製作方法
US10181449B1 (en) 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
US10504865B2 (en) * 2017-09-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法
JP2021002581A (ja) * 2019-06-21 2021-01-07 株式会社村田製作所 半導体装置
US10833053B1 (en) * 2019-07-17 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US11716117B2 (en) * 2020-02-14 2023-08-01 Texas Instruments Incorporated Circuit support structure with integrated isolation circuitry
KR20220026809A (ko) 2020-08-26 2022-03-07 삼성전자주식회사 반도체 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237506A1 (en) * 2009-03-20 2010-09-23 Infineon Technologies Ag Semiconductor device and manufacturing method thereof
US20120299192A1 (en) * 2011-05-23 2012-11-29 Via Technologies, Inc. Pad structure, circuit carrier and integrated circuit chip
CN102956634A (zh) * 2011-08-09 2013-03-06 联发科技股份有限公司 集成电路芯片
US20140191390A1 (en) * 2013-01-04 2014-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Routing Architecture for Integrated Circuits

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8622578B2 (en) * 2005-03-30 2014-01-07 Koninklijke Philips N.V. Flexible LED array
US10074553B2 (en) 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US8900931B2 (en) * 2007-12-26 2014-12-02 Skyworks Solutions, Inc. In-situ cavity integrated circuit package
US9484319B2 (en) 2011-12-23 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate
TW201347140A (zh) 2012-05-07 2013-11-16 Richtek Technology Corp 多晶片覆晶封裝模組及相關的製造方法
US9543259B2 (en) * 2014-10-01 2017-01-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure with oval shaped conductor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237506A1 (en) * 2009-03-20 2010-09-23 Infineon Technologies Ag Semiconductor device and manufacturing method thereof
US20120299192A1 (en) * 2011-05-23 2012-11-29 Via Technologies, Inc. Pad structure, circuit carrier and integrated circuit chip
CN102956634A (zh) * 2011-08-09 2013-03-06 联发科技股份有限公司 集成电路芯片
US20140191390A1 (en) * 2013-01-04 2014-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Routing Architecture for Integrated Circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107919330A (zh) * 2016-10-07 2018-04-17 联发科技股份有限公司 半导体芯片封装
CN115360170A (zh) * 2022-10-19 2022-11-18 睿力集成电路有限公司 一种半导体结构及其形成方法
CN115360170B (zh) * 2022-10-19 2023-01-31 睿力集成电路有限公司 一种半导体结构及其形成方法

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