US10224287B2 - Semiconductor device and wafer level package including such semiconductor device - Google Patents

Semiconductor device and wafer level package including such semiconductor device Download PDF

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US10224287B2
US10224287B2 US15/613,144 US201715613144A US10224287B2 US 10224287 B2 US10224287 B2 US 10224287B2 US 201715613144 A US201715613144 A US 201715613144A US 10224287 B2 US10224287 B2 US 10224287B2
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pad
chip metal
metal pad
landing pad
semiconductor device
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US20170271265A1 (en
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Shih-Yi Syu
Tung-Hsien Hsieh
Che-Ya Chou
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MediaTek Inc
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MediaTek Inc
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Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSIEH, TUNG-HSIEN, CHOU, CHE-YA, SYU, SHIH-YI
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Definitions

  • the present invention relates to a semiconductor device and package having fine RDL pitch and improved signal integrity.
  • Wafer level packaging is one approach, which the packaging industry is looking into for size and cost reduction.
  • Fan-Out Wafer Level Packaging which is known in the art, integrates at least two individual integrated circuit (IC) dies in a side-by-side configuration into one molded semiconductor package having fan-out redistribution layer (RDL) and post passivation interconnection (PPI).
  • RDL redistribution layer
  • PPI post passivation interconnection
  • the two IC dies are interconnected to each other through the RDL.
  • FOWLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FCBGA) packages.
  • the die-to-die signal points have dramatically increased.
  • the increased die-to-die signal points results in considerable loss of routing space in the redistribution layer (RDL).
  • RDL redistribution layer
  • a semiconductor device includes an integrated circuit (IC) die having an active surface.
  • IC integrated circuit
  • a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface.
  • a passivation layer is disposed on the active surface and covers the first on-chip metal pad and the second on-chip metal pad.
  • a redistribution layer (RDL) structure is disposed on the passivation layer.
  • the RDL structure includes a first landing pad disposed directly above the first on-chip metal pad, a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad, a second landing pad disposed directly above the second on-chip metal pad; a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad, and at least three traces being disposed on the RDL structure and passing through a space between the first landing pad and the second landing pad.
  • Each of the first landing pad, the second landing pad, the first via and the second via has a rectangular shape or an oval shape when viewed from the above.
  • a semiconductor package includes an integrated circuit (IC) die having an active surface.
  • IC integrated circuit
  • a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface.
  • a passivation layer is disposed on the active surface and covers the first on-chip metal pad and the second on-chip metal pad.
  • a molding compound encapsulates the IC die except for the active surface.
  • a redistribution layer (RDL) structure is disposed on the passivation layer and on the molding compound.
  • the RDL structure includes a first landing pad disposed directly above the first on-chip metal pad, a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad being disposed directly above the second on-chip metal pad, a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad; and at least three traces being disposed on the RDL structure and passing through a space between the landing pad and the second landing pad.
  • the first landing pad and the second landing pad have a longitudinal length L1 and a width W1, and an aspect ratio defined as L1/W1 ranges between 1 ⁇ 3.
  • a semiconductor package includes at least two integrated circuit (IC) dies each having an active surface. At least a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on respective active surfaces of the integrated circuit (IC) dies.
  • a passivation layer is disposed on the respective active surfaces and covering the first on-chip metal pad and the second on-chip metal pad.
  • a redistribution layer (RDL) structure is disposed on the passivation layer.
  • the RDL structure includes a first landing pad disposed directly above the first on-chip metal pad, a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad, a second landing pad disposed directly above the second on-chip metal pad, a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad, and at least three traces being disposed on the RDL structure and passing through a space between the first landing pad and the second landing pad.
  • Each of the first landing pad, the second landing pad, the first via and the second via has a rectangular shape or an oval shape when viewed from the above.
  • FIG. 1 is a schematic, cross-sectional diagram showing an exemplary fan-out wafer level package (FOWLP) according to one embodiment of the invention
  • FIG. 2 is a perspective plan view showing a portion of aluminum pads, copper vias, traces, and landing pads in the redistribution layer according to one embodiment of the invention
  • FIG. 3 is a schematic, cross-sectional diagram taken along line I-I′ in FIG. 2 ;
  • FIG. 4 is a perspective plan view showing a portion of aluminum pads, copper vias, traces, and landing pads in the redistribution layer according to another embodiment of the invention.
  • FIG. 1 is a schematic, cross-sectional diagram showing an exemplary semiconductor device package according to one embodiment of the invention.
  • the semiconductor device package 1 may be a Fan-Out Wafer Level Packaging (FOWLP) having molded integrated circuit (IC) dies arranged in a side-by-side configuration, but not limited thereto.
  • FOWLP Fan-Out Wafer Level Packaging
  • IC integrated circuit
  • the exemplary semiconductor device package 1 comprises two IC dies 102 and 104 arranged in a side-by-side configuration and molded by using a molding material 20 such as epoxy, resin, or other suitable molding compounds.
  • the IC dies 102 and 104 have active surfaces 102 a and 104 a , respectively (in this figure both facing downward).
  • On the active surfaces 102 a and 104 a on-chip metal pads 122 and 142 such as aluminum (Al) pads are provided.
  • Al aluminum
  • passivation layers 120 and 140 may comprise silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof.
  • dielectric capping layers 124 and 144 may be disposed directly on the passivation layers 120 and 140 respectively, thereby providing a planar major surface that is substantially flush with a surface of the molding material 20 surrounding the two IC dies 102 and 104 .
  • the dielectric capping layers 124 and 144 are in direct contact with the passivation layers 120 and 140 , respectively.
  • the dielectric capping layers 124 and 144 may comprise a polymeric material such as polyimide, a laminating tape, a backside grinding tape, an adhesive, an UV tap, or the like.
  • the IC dies 102 and 104 may further comprise metal interconnection schemes underneath the passivation layers 120 and 140 , respectively.
  • the aforesaid metal interconnection schemes may include but not limited to ultra-low-k dielectric layers, inter-layer dielectric (ILD) layers, and multi-layer copper metal layers distributed or damascened in the dielectric capping layers.
  • the metal interconnection schemes may be constructed on a semiconductor substrate such as a silicon substrate in and on which a plurality of semiconductor circuit elements such as transistors may be located. The details of the inner structures under the passivation layers 120 and 140 are omitted for the sake of simplicity.
  • Openings may be formed in the dielectric capping layer 124 and the passivation layers 120 and 140 . Each of the openings may expose a portion of the top surface of each of the metal pads 122 and 142 .
  • Conductive pillar bumps 126 and 146 such as copper pillar bumps or copper contact plugs may be formed within the openings and fill up the openings on the metal pads 122 and 142 , respectively. It is to be understood that in other embodiments the dielectric capping layer 124 and the conductive pillar bumps 126 may be omitted.
  • a redistribution layer (RDL) structure 200 is formed directly on the dielectric capping layer 124 and on the molding material 20 surrounding the two IC dies 102 and 104 generally for signal fan-out purposes.
  • the RDL structure 200 may comprise a plurality of insulating layers 201 , 203 , 205 , and 207 , for example, and a plurality of metal layers 202 , 204 , and 206 in and on the plurality of insulating layers 201 , 203 , 205 , and 207 .
  • the insulating layers 201 , 203 , 205 , and 207 may comprise organic materials or polymeric materials including but not limited to polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. In other embodiments, the insulating layers 201 , 203 , 205 , and 207 may comprise inorganic materials.
  • the metal layer 202 may comprise circuit features such as via 202 a disposed directly above each of the conductive pillar bumps 126 and 146 , a landing pad 202 b , and a fine trace 202 c extending and communicating between via and landing pad, or between landing pad and landing pad on the insulating layer 201 .
  • an exemplary region indicated by the dashed lines 310 shows the route for die-to-die signal transmitting, which includes but not limited to die-to-die metal pads 122 a and 142 a , vias 202 a , landing pads 202 b on the metal pads and vias, and fine trace 202 c between the landing pads 202 b.
  • the die-to-die signal points have dramatically increased.
  • the increased die-to-die signal points results in considerable loss of routing space in the RDL.
  • FIG. 2 is a perspective plan view showing a portion of the RDL structure of a fan-out wafer level package (FOWLP) according to one embodiment of the invention.
  • FIG. 3 is a schematic, cross-sectional diagram taken along line I-I′ in FIG. 2 .
  • the RDL structure 400 fabricated on an IC die 100 may comprise two adjacent on-chip aluminum (Al) pads (AP), which are indicated by the dashed line 301 .
  • the Al pads (AP) may be covered with a passivation layer 410 .
  • the passivation layer 410 may comprise silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof.
  • the passivation layer 410 may comprise organic materials such as polyimide or the like. It is to be understood that more dielectric layers and metal layers may be formed on the passivation layer 410 for further connection as set forth in FIG. 1 .
  • Openings may be formed in the passivation layer 410 . Each of the openings may expose a central portion of the top surface of each of the Al pads (AP).
  • a copper via (V), which is indicated by the dashed line 302 is formed directly on each of the Al pads (AP).
  • a landing pad (LP) is formed directly on each of the copper vias (V).
  • at least five fine traces S, G, S, G, S may pass through the space between the two adjacent landing pads (LP).
  • the five fine traces S, G, S, G, S may comprise copper, but not limited thereto.
  • each of the Al pads (AP) may have a rectangular shape or oval shape when viewed from the above.
  • Each of the Al pads (AP) may have a longitudinal length L1 and a width W1.
  • the longitudinal direction of each of the Al pads (AP) is in parallel with a reference y-axis, which may be the signal transmitting direction (die-to-die direction) between two IC dies 102 and 104 as set forth in FIG. 1 .
  • An aspect ratio of the each of the Al pads (AP) is defined as L1/W1, which may range between 2 ⁇ 3, especially range between 1 ⁇ 3, for example.
  • the width W1 may be one-half the longitudinal length L1, but not limited thereto.
  • the width W1 may be smaller than one-half the longitudinal length L1, but not limited thereto.
  • longitudinal length L1 may range between 35 ⁇ 55 micrometers, for example, 45 micrometers
  • width W1 may range between 15 ⁇ 30 micrometers, for example, 20 micrometers.
  • each of the landing pads (LP) may have a rectangular shape or oval shape when viewed from the above.
  • Each of the landing pads (LP) may have a longitudinal length L2 and a width W2.
  • the longitudinal direction of each of the landing pads (LP) is in parallel with the reference y-axis, which may be the signal transmitting direction (die-to-die direction) between two IC dies 102 and 104 as set forth in FIG. 1 .
  • An aspect ratio of the each of the landing pads (LP) is defined as L2/W2, which may range between 2 ⁇ 3, especially range between 1 ⁇ 3, for example.
  • the width W2 may be one-half the longitudinal length L2, but not limited thereto.
  • the width W2 may be smaller than one-half the longitudinal length L2, but not limited thereto.
  • longitudinal length L2 may range between 30 ⁇ 50 micrometers, for example, 40 micrometers
  • width W2 may range between 10 ⁇ 25 micrometers, for example, 18 micrometers.
  • the five fine traces S, G, S, G, S extending along the reference y-axis (or die-to-die direction) between the two adjacent landing pads (LP) may transmit die-to-die signals.
  • the two fine traces G may transmit ground signal and may function as shielding traces interposed between two high-speed signal traces, i.e. fine traces denoted with S.
  • the term “SGS” may refer to a circuit layout structure comprising an intervening reference (e.g. grounded) trace sandwiched by a pair of high-speed or high-frequency signal traces, for example, operated greater than 1 Gb/s.
  • the term “SGSGS” may refer to two intervening reference traces between three high-speed or high-frequency signal traces.
  • redistribution layer under the passivation layer 410 may be provided between the two Al pads (AP).
  • AP Al pads
  • FIG. 3 at least four aluminum traces (AT), which also extend along the reference y-axis (or die-to-die direction), are provided.
  • the landing pads (LP) and/or the Al pads (AP), especially those located within the region indicated by the dashed lines 310 in FIG. 1 have rectangular shape or oval shape when viewed from the above and therefore the space therebetween is widened to thereby accommodating more RDL traces.
  • the SGSGS trace configuration depicted in FIG. 2 and FIG. 3 improves the signal integrity in the RDL level.
  • FIG. 4 is a perspective plan view showing a portion of aluminum pads, copper vias, traces, and landing pads in the redistribution layer according to another embodiment of the invention.
  • the landing pads (LP) in FIG. 4 has a more slender shape, which has a longitudinal length L3 that is greater than L2 and a width W3 that is smaller than W2. Due to the more slender shape of the landing pads (LP) in FIG. 4 , the space between the two adjacent landing pads (LP) is further widened. Therefore, more RDL traces may be arranged in the space.
  • the landing pads (LP) in FIG. 4 have substantially the same surface area as that of the landing pads (LP) shown in FIG. 2 .
  • part of the boundary of the copper via (V) as indicated by the dashed line 302 may partially overlaps with part of the boundary or peripheral edge of the landing pad (LP).

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Abstract

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Description

CROSS REFERENCE TO RELATED APPLICATION
This application is a continuation of U.S. application Ser. No. 15/006,082 filed Jan. 25, 2016, which itself claims the benefit of U.S. provisional application No. 62/135,935 filed Mar. 20, 2015.
BACKGROUND
The present invention relates to a semiconductor device and package having fine RDL pitch and improved signal integrity.
Cost and size reduction is driving packaging industry to new measures and approaches. Wafer level packaging is one approach, which the packaging industry is looking into for size and cost reduction.
For example, Fan-Out Wafer Level Packaging (FOWLP), which is known in the art, integrates at least two individual integrated circuit (IC) dies in a side-by-side configuration into one molded semiconductor package having fan-out redistribution layer (RDL) and post passivation interconnection (PPI). The two IC dies are interconnected to each other through the RDL. FOWLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FCBGA) packages.
However, as more and more functions are incorporated into one single IC die, the die-to-die signal points have dramatically increased. The increased die-to-die signal points results in considerable loss of routing space in the redistribution layer (RDL). Currently, at most three to four signal traces can be arranged between two adjacent landing pads due to the relatively large size of each landing pad. There is no enough room for disposing the shielding traces. This adversely influences the signal integrity in high-speed applications because of crosstalk between signals.
Accordingly, there is a need in this industry to provide an improved wafer level package with fine RDL pitch and improved signal integrity.
SUMMARY
It is an objective of the claimed invention to provide an improved semiconductor device and package having fine RDL pitch and improved signal integrity.
According to one aspect of the invention, a semiconductor device includes an integrated circuit (IC) die having an active surface. A first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface. A passivation layer is disposed on the active surface and covers the first on-chip metal pad and the second on-chip metal pad. A redistribution layer (RDL) structure is disposed on the passivation layer.
The RDL structure includes a first landing pad disposed directly above the first on-chip metal pad, a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad, a second landing pad disposed directly above the second on-chip metal pad; a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad, and at least three traces being disposed on the RDL structure and passing through a space between the first landing pad and the second landing pad. Each of the first landing pad, the second landing pad, the first via and the second via has a rectangular shape or an oval shape when viewed from the above.
According to another aspect of the invention, a semiconductor package includes an integrated circuit (IC) die having an active surface. A first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface. A passivation layer is disposed on the active surface and covers the first on-chip metal pad and the second on-chip metal pad. A molding compound encapsulates the IC die except for the active surface. A redistribution layer (RDL) structure is disposed on the passivation layer and on the molding compound.
The RDL structure includes a first landing pad disposed directly above the first on-chip metal pad, a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad being disposed directly above the second on-chip metal pad, a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad; and at least three traces being disposed on the RDL structure and passing through a space between the landing pad and the second landing pad. The first landing pad and the second landing pad have a longitudinal length L1 and a width W1, and an aspect ratio defined as L1/W1 ranges between 1˜3.
According to still another aspect of the invention, a semiconductor package includes at least two integrated circuit (IC) dies each having an active surface. At least a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on respective active surfaces of the integrated circuit (IC) dies. A passivation layer is disposed on the respective active surfaces and covering the first on-chip metal pad and the second on-chip metal pad. A redistribution layer (RDL) structure is disposed on the passivation layer.
The RDL structure includes a first landing pad disposed directly above the first on-chip metal pad, a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad, a second landing pad disposed directly above the second on-chip metal pad, a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad, and at least three traces being disposed on the RDL structure and passing through a space between the first landing pad and the second landing pad. Each of the first landing pad, the second landing pad, the first via and the second via has a rectangular shape or an oval shape when viewed from the above.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic, cross-sectional diagram showing an exemplary fan-out wafer level package (FOWLP) according to one embodiment of the invention;
FIG. 2 is a perspective plan view showing a portion of aluminum pads, copper vias, traces, and landing pads in the redistribution layer according to one embodiment of the invention;
FIG. 3 is a schematic, cross-sectional diagram taken along line I-I′ in FIG. 2; and
FIG. 4 is a perspective plan view showing a portion of aluminum pads, copper vias, traces, and landing pads in the redistribution layer according to another embodiment of the invention.
 DETAILED DESCRIPTION
In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.
These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.
FIG. 1 is a schematic, cross-sectional diagram showing an exemplary semiconductor device package according to one embodiment of the invention. The semiconductor device package 1 may be a Fan-Out Wafer Level Packaging (FOWLP) having molded integrated circuit (IC) dies arranged in a side-by-side configuration, but not limited thereto. Although a multi-die WLP package is illustrated, it is understood that the present invention may be applicable to single-die packages.
As shown in FIG. 1, the exemplary semiconductor device package 1 comprises two IC dies 102 and 104 arranged in a side-by-side configuration and molded by using a molding material 20 such as epoxy, resin, or other suitable molding compounds. The IC dies 102 and 104 have active surfaces 102 a and 104 a, respectively (in this figure both facing downward). On the active surfaces 102 a and 104 a, on- chip metal pads 122 and 142 such as aluminum (Al) pads are provided. These on- chip metal pads 122 and 142 are covered with passivation layers 120 and 140, respectively. According to the illustrated embodiment, the passivation layers 120 and 140 may comprise silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof.
Optionally, dielectric capping layers 124 and 144 may be disposed directly on the passivation layers 120 and 140 respectively, thereby providing a planar major surface that is substantially flush with a surface of the molding material 20 surrounding the two IC dies 102 and 104. According to the illustrated embodiment, the dielectric capping layers 124 and 144 are in direct contact with the passivation layers 120 and 140, respectively. According to the illustrated embodiment, the dielectric capping layers 124 and 144 may comprise a polymeric material such as polyimide, a laminating tape, a backside grinding tape, an adhesive, an UV tap, or the like.
Although not shown in this figure, it is understood that the IC dies 102 and 104 may further comprise metal interconnection schemes underneath the passivation layers 120 and 140, respectively. For example, the aforesaid metal interconnection schemes may include but not limited to ultra-low-k dielectric layers, inter-layer dielectric (ILD) layers, and multi-layer copper metal layers distributed or damascened in the dielectric capping layers. The metal interconnection schemes may be constructed on a semiconductor substrate such as a silicon substrate in and on which a plurality of semiconductor circuit elements such as transistors may be located. The details of the inner structures under the passivation layers 120 and 140 are omitted for the sake of simplicity.
Openings may be formed in the dielectric capping layer 124 and the passivation layers 120 and 140. Each of the openings may expose a portion of the top surface of each of the metal pads 122 and 142. Conductive pillar bumps 126 and 146 such as copper pillar bumps or copper contact plugs may be formed within the openings and fill up the openings on the metal pads 122 and 142, respectively. It is to be understood that in other embodiments the dielectric capping layer 124 and the conductive pillar bumps 126 may be omitted.
A redistribution layer (RDL) structure 200 is formed directly on the dielectric capping layer 124 and on the molding material 20 surrounding the two IC dies 102 and 104 generally for signal fan-out purposes. According to the illustrated embodiment, the RDL structure 200 may comprise a plurality of insulating layers 201, 203, 205, and 207, for example, and a plurality of metal layers 202, 204, and 206 in and on the plurality of insulating layers 201, 203, 205, and 207. The insulating layers 201, 203, 205, and 207 may comprise organic materials or polymeric materials including but not limited to polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. In other embodiments, the insulating layers 201, 203, 205, and 207 may comprise inorganic materials.
For example, the metal layer 202 may comprise circuit features such as via 202 a disposed directly above each of the conductive pillar bumps 126 and 146, a landing pad 202 b, and a fine trace 202 c extending and communicating between via and landing pad, or between landing pad and landing pad on the insulating layer 201. In FIG. 1, an exemplary region indicated by the dashed lines 310 shows the route for die-to-die signal transmitting, which includes but not limited to die-to-die metal pads 122 a and 142 a, vias 202 a, landing pads 202 b on the metal pads and vias, and fine trace 202 c between the landing pads 202 b.
As alluded to hereinabove, as more and more functions are incorporated into one single IC die, the die-to-die signal points have dramatically increased. The increased die-to-die signal points results in considerable loss of routing space in the RDL. Conventionally, at most three to four signal traces can be arranged between two adjacent landing pads due to the relatively large size of each landing pad. There is no enough room for disposing the shielding traces. This adversely influences the signal integrity in high-speed applications because of crosstalk between signals. This invention addresses this problem.
Please refer to FIG. 2 and FIG. 3. FIG. 2 is a perspective plan view showing a portion of the RDL structure of a fan-out wafer level package (FOWLP) according to one embodiment of the invention. FIG. 3 is a schematic, cross-sectional diagram taken along line I-I′ in FIG. 2. As shown in FIG. 2 and FIG. 3, the RDL structure 400 fabricated on an IC die 100 may comprise two adjacent on-chip aluminum (Al) pads (AP), which are indicated by the dashed line 301. The Al pads (AP) may be covered with a passivation layer 410. According to the illustrated embodiment, the passivation layer 410 may comprise silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof. In other embodiments, the passivation layer 410 may comprise organic materials such as polyimide or the like. It is to be understood that more dielectric layers and metal layers may be formed on the passivation layer 410 for further connection as set forth in FIG. 1.
Openings may be formed in the passivation layer 410. Each of the openings may expose a central portion of the top surface of each of the Al pads (AP). A copper via (V), which is indicated by the dashed line 302, is formed directly on each of the Al pads (AP). A landing pad (LP) is formed directly on each of the copper vias (V). According to the illustrated embodiment, at least five fine traces S, G, S, G, S may pass through the space between the two adjacent landing pads (LP). The five fine traces S, G, S, G, S may comprise copper, but not limited thereto.
According to the illustrated embodiment, each of the Al pads (AP) may have a rectangular shape or oval shape when viewed from the above. Each of the Al pads (AP) may have a longitudinal length L1 and a width W1. According to the illustrated embodiment, the longitudinal direction of each of the Al pads (AP) is in parallel with a reference y-axis, which may be the signal transmitting direction (die-to-die direction) between two IC dies 102 and 104 as set forth in FIG. 1. An aspect ratio of the each of the Al pads (AP) is defined as L1/W1, which may range between 2˜3, especially range between 1˜3, for example. The width W1 may be one-half the longitudinal length L1, but not limited thereto. In some embodiments, the width W1 may be smaller than one-half the longitudinal length L1, but not limited thereto. For not limiting example, longitudinal length L1 may range between 35˜55 micrometers, for example, 45 micrometers, and the width W1 may range between 15˜30 micrometers, for example, 20 micrometers.
According to the illustrated embodiment, each of the landing pads (LP) may have a rectangular shape or oval shape when viewed from the above. Each of the landing pads (LP) may have a longitudinal length L2 and a width W2. According to the illustrated embodiment, the longitudinal direction of each of the landing pads (LP) is in parallel with the reference y-axis, which may be the signal transmitting direction (die-to-die direction) between two IC dies 102 and 104 as set forth in FIG. 1. An aspect ratio of the each of the landing pads (LP) is defined as L2/W2, which may range between 2˜3, especially range between 1˜3, for example. The width W2 may be one-half the longitudinal length L2, but not limited thereto. In some embodiments, the width W2 may be smaller than one-half the longitudinal length L2, but not limited thereto. For not limiting example, longitudinal length L2 may range between 30˜50 micrometers, for example, 40 micrometers, and the width W2 may range between 10˜25 micrometers, for example, 18 micrometers.
According to the illustrated embodiment, the five fine traces S, G, S, G, S extending along the reference y-axis (or die-to-die direction) between the two adjacent landing pads (LP) may transmit die-to-die signals. According to the illustrated embodiment, the two fine traces G may transmit ground signal and may function as shielding traces interposed between two high-speed signal traces, i.e. fine traces denoted with S. The term “SGS” may refer to a circuit layout structure comprising an intervening reference (e.g. grounded) trace sandwiched by a pair of high-speed or high-frequency signal traces, for example, operated greater than 1 Gb/s. The term “SGSGS” may refer to two intervening reference traces between three high-speed or high-frequency signal traces. By providing such configuration, the signal integrity can be significantly improved.
According to the illustrated embodiment, redistribution layer under the passivation layer 410 may be provided between the two Al pads (AP). For example, in FIG. 3, at least four aluminum traces (AT), which also extend along the reference y-axis (or die-to-die direction), are provided. It is advantageous to use the present invention because the landing pads (LP) and/or the Al pads (AP), especially those located within the region indicated by the dashed lines 310 in FIG. 1, have rectangular shape or oval shape when viewed from the above and therefore the space therebetween is widened to thereby accommodating more RDL traces. The SGSGS trace configuration depicted in FIG. 2 and FIG. 3 improves the signal integrity in the RDL level.
FIG. 4 is a perspective plan view showing a portion of aluminum pads, copper vias, traces, and landing pads in the redistribution layer according to another embodiment of the invention. As shown in FIG. 4, when compared to the landing pads in FIG. 2, the landing pads (LP) in FIG. 4 has a more slender shape, which has a longitudinal length L3 that is greater than L2 and a width W3 that is smaller than W2. Due to the more slender shape of the landing pads (LP) in FIG. 4, the space between the two adjacent landing pads (LP) is further widened. Therefore, more RDL traces may be arranged in the space. For example, seven traces denoted by SGSGSGS comprising four high-speed signal traces and three reference or grounded traces are shown in FIG. 4. According to the illustrated embodiment, the landing pads (LP) in FIG. 4 have substantially the same surface area as that of the landing pads (LP) shown in FIG. 2. In some cases, part of the boundary of the copper via (V) as indicated by the dashed line 302 may partially overlaps with part of the boundary or peripheral edge of the landing pad (LP).
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (17)

What is claimed is:
1. A semiconductor device, comprising:
an integrated circuit (IC) die having an active surface, wherein at least a first on-chip metal pad and a second on-chip metal pad are disposed on the active surface;
a passivation layer on the active surface and covering the first on-chip metal pad and the second on-chip metal pad;
and a redistribution layer (RDL) structure on the passivation layer, the RDL structure comprising:
a first conductive pillar bump disposed under the first on-chip metal pad;
a first landing pad disposed under the first conductive pillar bump;
a first via in the RDL structure to contact the first conductive pillar bump and electrically connect the first landing pad with the first on-chip metal pad;
a second conductive pillar bump disposed under the second on-chip metal pad;
a second landing pad disposed under the second conductive bump;
a second via in the RDL structure to contact the second conductive pillar bump and electrically connect the second landing pad with the second on-chip metal pad, wherein each of the first landing pad, the second landing pad, the first via and the second via has an oval shape when viewed from the above; and
at least three traces being disposed on the RDL structure and passing through a space between the first landing pad and the second landing pad, wherein the at least three traces comprise two intervening reference traces between three high-speed signal traces to thereby form a SGSGS RDL trace configuration.
2. The semiconductor device according to claim 1, wherein the first on-chip metal pad is an aluminum pad.
3. The semiconductor device according to claim 2, wherein the second on-chip metal pad is an aluminum pad.
4. The semiconductor device according to claim 1, wherein the passivation layer comprises silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof.
5. The semiconductor device according to claim 1, wherein the first landing pad and the first via are composed of copper.
6. The semiconductor device according to claim 5, wherein the second landing pad and the second via are composed of copper.
7. The semiconductor device according to claim 1, wherein the high-speed signal traces are operated greater than 1 Gb/s.
8. The semiconductor device according to claim 1, wherein the two intervening reference traces transmit a ground signal.
9. The semiconductor device according to claim 1, wherein the at least three traces comprise two intervening reference traces around one signal traces to thereby form a GSG RDL trace configuration.
10. The semiconductor device according to claim 1, wherein the first landing pad and the second landing pad both have an aspect ratio ranging between 1˜3.
11. The semiconductor device according to claim 1, wherein at least four aluminum traces extending along a die-to-die direction are disposed between the first on-chip metal pad and the second on-chip metal pad.
12. A semiconductor package, comprising:
an integrated circuit (IC) die having an active surface, wherein at least a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface;
a passivation layer on the active surface and covering the first on-chip metal pad and the second on-chip metal pad;
a molding compound encapsulating the IC die except for the active surface; and a redistribution layer (RDL) structure on the passivation layer and on the molding compound, the RDL structure comprising:
a first landing pad disposed directly above the first on-chip metal pad;
a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad;
a second landing pad being disposed directly above the second on-chip metal pad;
a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad; and
at least three traces being disposed on the RDL structure and passing through a space between the landing pad and the second landing pad, wherein the first landing pad and the second landing pad have a longitudinal length L1 and a width W1, and an aspect ratio defined as L1/W1 ranges between 1˜3.
13. The semiconductor package according to claim 12, wherein the first on-chip metal pad and on-chip metal pad are aluminum pads.
14. The semiconductor package according to claim 12, wherein the passivation layer comprises silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof.
15. The semiconductor package according to claim 12, wherein the first landing pad, the first via, the second landing pad and the second via are composed of copper.
16. The semiconductor package according to claim 12, wherein the at least three traces comprise two intervening reference traces around one signal traces to thereby form a GSG RDL trace configuration.
17. The semiconductor device according to claim 1, wherein the first conductive pillar bump and/or second conductive pillar bump are copper.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11735571B2 (en) 2020-08-26 2023-08-22 Samsung Electronics Co., Ltd. Semiconductor package including a redistribution structure

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9431600B2 (en) * 2014-10-06 2016-08-30 International Business Machines Corporation Magnetic domain wall shift register memory devices with high magnetoresistance ratio structures
CN105514071B (en) * 2016-01-22 2019-01-25 中芯长电半导体（江阴）有限公司 A kind of encapsulating method and structure being fanned out to cake core
TWI649856B (en) * 2016-05-13 2019-02-01 精材科技股份有限公司 Chip package and manufacturing method thereof
US9842810B1 (en) * 2016-06-08 2017-12-12 Globalfoundries Inc. Tiled-stress-alleviating pad structure
US10276382B2 (en) 2016-08-11 2019-04-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and stacked package assemblies including high density interconnections
US10217723B2 (en) 2016-10-07 2019-02-26 Mediatek Inc. Semiconductor package with improved bandwidth
TWI623049B (en) * 2016-11-04 2018-05-01 英屬開曼群島商鳳凰先驅股份有限公司 Package substrate and its fabrication method
US10504865B2 (en) * 2017-09-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10181449B1 (en) 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
CN111627867A (en) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 Chip packaging structure and manufacturing method thereof
JP2021002581A (en) * 2019-06-21 2021-01-07 株式会社村田製作所 Semiconductor device
US10833053B1 (en) * 2019-07-17 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US11716117B2 (en) * 2020-02-14 2023-08-01 Texas Instruments Incorporated Circuit support structure with integrated isolation circuitry
CN115360170B (en) * 2022-10-19 2023-01-31 睿力集成电路有限公司 Semiconductor structure and forming method thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080225523A1 (en) 2005-03-30 2008-09-18 Koninklijke Philips Electronics N.V. Flexible Led Array
TW200926312A (en) 2007-12-03 2009-06-16 Stats Chippac Ltd Wafer level package integration and method
US20100237506A1 (en) * 2009-03-20 2010-09-23 Infineon Technologies Ag Semiconductor device and manufacturing method thereof
US20120299192A1 (en) 2011-05-23 2012-11-29 Via Technologies, Inc. Pad structure, circuit carrier and integrated circuit chip
CN102956634A (en) 2011-08-09 2013-03-06 联发科技股份有限公司 Integrated circuit chip
TW201327744A (en) 2011-12-23 2013-07-01 Stats Chippac Ltd Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate
US20130292813A1 (en) 2012-05-07 2013-11-07 Richtek Technology Corporation Multi-chip flip chip package and manufacturing method thereof
US20140191390A1 (en) 2013-01-04 2014-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Routing Architecture for Integrated Circuits
US20170103955A1 (en) * 2014-10-01 2017-04-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8900931B2 (en) * 2007-12-26 2014-12-02 Skyworks Solutions, Inc. In-situ cavity integrated circuit package

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080225523A1 (en) 2005-03-30 2008-09-18 Koninklijke Philips Electronics N.V. Flexible Led Array
TW200926312A (en) 2007-12-03 2009-06-16 Stats Chippac Ltd Wafer level package integration and method
US20100237506A1 (en) * 2009-03-20 2010-09-23 Infineon Technologies Ag Semiconductor device and manufacturing method thereof
US20120299192A1 (en) 2011-05-23 2012-11-29 Via Technologies, Inc. Pad structure, circuit carrier and integrated circuit chip
CN102956634A (en) 2011-08-09 2013-03-06 联发科技股份有限公司 Integrated circuit chip
TW201327744A (en) 2011-12-23 2013-07-01 Stats Chippac Ltd Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate
US20130292813A1 (en) 2012-05-07 2013-11-07 Richtek Technology Corporation Multi-chip flip chip package and manufacturing method thereof
US20140191390A1 (en) 2013-01-04 2014-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Routing Architecture for Integrated Circuits
US20170103955A1 (en) * 2014-10-01 2017-04-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11735571B2 (en) 2020-08-26 2023-08-22 Samsung Electronics Co., Ltd. Semiconductor package including a redistribution structure

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