CN105914192A - 基于级联电路的半导体封装结构 - Google Patents

基于级联电路的半导体封装结构 Download PDF

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Publication number
CN105914192A
CN105914192A CN201510991622.XA CN201510991622A CN105914192A CN 105914192 A CN105914192 A CN 105914192A CN 201510991622 A CN201510991622 A CN 201510991622A CN 105914192 A CN105914192 A CN 105914192A
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Prior art keywords
semiconductor transistor
source electrode
transistor
semiconductor
low pressure
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CN201510991622.XA
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CN105914192B (zh
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赵树峰
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SUZHOU JIEXINWEI SEMICONDUCTOR TECHNOLOGY Co Ltd
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SUZHOU JIEXINWEI SEMICONDUCTOR TECHNOLOGY Co Ltd
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Priority to CN201510991622.XA priority Critical patent/CN105914192B/zh
Priority to US15/251,594 priority patent/US10163811B2/en
Priority to EP16186549.8A priority patent/EP3185295A1/en
Publication of CN105914192A publication Critical patent/CN105914192A/zh
Priority to JP2016190580A priority patent/JP6346643B2/ja
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Abstract

本发明公开了一种基于级联电路的半导体封装结构，包括：高压耗尽型半导体晶体管；低压增强型半导体晶体管；导电支撑片，高压耗尽型半导体晶体管和所述低压增强型半导体晶体管固定于导电支撑片上；管壳，管壳上设有高压端子、第一低压端子及第二低压端子；级联电路，高压耗尽型半导体晶体管、低压增强型半导体晶体管及管壳间通过级联电路电连接，其中，高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极直接固定于导电支撑片上并导电支撑片电连接。本发明的半导体封装结构中，高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极通过导电支撑片电连接，可有效减少引入的寄生电感和寄生电阻，提高器件的工作性能。

Description

基于级联电路的半导体封装结构
技术领域
本发明涉及半导体技术领域，特别是涉及一种基于级联电路的半导体封装结构。
背景技术
目前，功率电子器件应用中的晶体管主要还是传统的硅材料器件，例如SiCoolMOS、SiIGBT、SiMOSFET等。但随着功率器件技术的快速发展，基于传统的Si材料以及第二代半导体材料的功率器件已经无法满足实际应用中快速、低损耗等的迫切需求。SiC功率器件凭借材料的优势，已经受到了业界的高度重视。同时，作为第三代宽禁带半导体功率器件，特别是氮化镓功率器件近年来也逐渐成为研究的热点，已经被广泛的应用于射频和电力电子领域。一方面，是因为氮化镓是宽禁带半导体材料的，该材料具有比硅材料大10倍左右临界击穿电场以及相应的高耐压的特性，另一方面，是由于二维电子气沟道能够提供非常小的导通电阻，从而减少开关器件的功率损耗。因此，基于铝镓氮/氮化镓异质结构的平面型三极管逐渐成为业界的重要研究对象。
在高压功率器件的实际应用中，为了保证应用系统以及操作环境的安全性，一般采用常关型器件，也就是功率器件栅极施加零电压时，器件没有电流输出。但是，由于铝镓氮/氮化镓异质结材料的特点，更加容易实现耗尽型器件。当然，有很多报道中提到了通过能带工程实现增强器件，但从业界角度考虑，这样的技术还存在诸多不足。目前，为了制作常关型氮化镓器件，报道中涉及了一种将高压耗尽型器件与传统的低压增强型器件级联，即高压耗尽型器件的源极与增强型器件的漏极电连接，耗尽型器件的栅极与增强型器件的源极电连接，因此增强型器件的漏极电压就成了耗尽型器件的负栅极电压，从而自动提供必要的负偏压以实现耗尽型关断操作。但是级联电路中，寄生电感主要分布与源极、漏极、栅极以及器件间内部电连接的电感，由于电极之间互联引入的寄生电感和寄生电阻，将降低信号的切换速度，使得氮化镓功率器件高频快速特性受阻。因此，需要考虑将级联电路中引入的寄生电感最小化。
现在，也有很多的文献和专利中提出了不同结构级联形式，实现器件的增强型特性。例如：
专利号为US20140167822A1专利“Cascode Circuit”中，涉及到级联电路，参图1所示为耗尽型器件与增强型器件级联电连接的电路图，结合图3所示，该级联过程主要是将耗尽型器件的源极通过导线直接与增强型器件的漏极相连，耗尽型器件的栅极与增强型器件的源极通过导线电连接共同作为级联电路的源极。整合电路可以实现高压增强型器件的特性。
专利号为US2014/0042495A1专利“semiconductor electronic componentsand circuits”中提出的级联电路结构时，参图2a、2b所示，在耗尽型管子的栅极与增强型管子的源极之间分别加入了电阻和电容。结合图3所示，在级联电路中增加电阻和电容的目的是当给定输入电压后，增加的电阻或电容限制了信号转化速率，降低电噪声以及电磁干扰的产生，防止了栅极驱动发生故障。
文献“A New Package of High-Voltage Cascode Gallium Nitride Device forMegahertz Operation”中提到了一种在no-lead的PQFN管壳类型中，参图4所示，将低压增强型器件的漏电极叠放在高压耗尽型器件的源电极上，再将耗尽型器件的栅极通过导线引到增强器件的源极，共同作为整合器件的源极；同时将高压耗尽型器件的漏极通过金属带与管壳的漏极电连接。通过叠放形式，可以改善寄生电感，有效降低了硬开关和软开关过程损耗。
在上述解决方案中，都提到了采用低压增强型器件与高压耗尽型器件级联实现高压增强型特性，同时有的方案中也提到了通过二者电极叠放的方式减少寄生电感，得到了很好的效果。
发明内容
有鉴于此，本发明提出了一种基于级联电路的半导体封装结构，通过级联电路，高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极直接通过导电支撑片电连接，无需借助导线，可有效减少引入的寄生电感和寄生电阻，提高器件的工作性能。
为了实现上述目的，本发明实施例提供的技术方案如下：
一种基于级联电路的半导体封装结构，所述半导体封装结构包括：
高压耗尽型半导体晶体管，其包括源极、栅极及漏极；
低压增强型半导体晶体管，其包括源极、栅极及漏极；
导电支撑片，所述高压耗尽型半导体晶体管和所述低压增强型半导体晶体管固定于导电支撑片上；
管壳，所述管壳上设有高压端子、第一低压端子及第二低压端子；
级联电路，所述高压耗尽型半导体晶体管、低压增强型半导体晶体管及管壳间通过级联电路电连接，其中，所述高压耗尽型半导体晶体管的漏极电连接所述管壳的高压端子；所述高压耗尽型半导体晶体管的栅极和低压增强型半导体晶体管的源极分别与第一低压端子电连接；所述低压增强型半导体晶体管的栅极与所述管壳的第二低压端子电连接；所述高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极直接固定于导电支撑片上并导电支撑片电连接。
作为本发明的进一步改进，所述导电支撑片为金属陶瓷支撑片。
作为本发明的进一步改进，所述高压耗尽型半导体晶体管包括：
衬底；
位于衬底上的沟道层和势垒层，沟道层和势垒层在界面处形成二维电子气；
位于沟道层上的源极欧姆金属、漏极、以及位于势垒层上的栅极；
通孔，所述通孔位于所述高压耗尽型半导体晶体管的源极欧姆金属背面，且所述通孔的方向由所述衬底的背面指向所述源极欧姆金属方向；
通孔金属，所述通孔金属位于所述通孔内，且与所述的源极欧姆金属电连接；
背金属，所述背金属位于所述衬底背面，且与所述通孔金属电连接；
其中，所述高压耗尽型半导体晶体管的源极由源极欧姆金属、通孔金属以及背金属共同形成。
作为本发明的进一步改进，所述高压耗尽型半导体晶体管中的背金属固定于所述导电支撑片上，且与导电支撑片电连接。
作为本发明的进一步改进，所述高压耗尽型半导体晶体管还包括位于势垒层上的栅介质层和/或表面钝化介质层。
作为本发明的进一步改进，所述低压增强型半导体晶体管的源极和栅极位于同侧，漏极位于相对栅源极的另一侧。
作为本发明的进一步改进，所述高压耗尽型半导体晶体管为氮化镓半导体晶体管，所述低压增强型半导体晶体管为硅半导体场效应晶体管。
作为本发明的进一步改进，所述低压增强型半导体晶体管为垂直结构的增强型半导体晶体管。
作为本发明的进一步改进，所述半导体封装结构中：
所述高压耗尽型半导体晶体管的漏极与管壳的高压端子通过导线电连接；
所述低压增强型半导体晶体管的源极与所述高压耗尽型半导体晶体管的栅极通过导线电连接，所述低压增强型半导体晶体管的源极或所述高压耗尽型半导体晶体管的栅极与所述管壳的第一低压端子通过导线电连接；
所述低压增强型半导体晶体管的栅极与所述管壳的第二低压端子通过导线电连接。
作为本发明的进一步改进，所述半导体封装结构中，在所述低压增强型半导体晶体管的源极与所述高压耗尽型半导体晶体管的栅极之间串联有一个或多个电阻元件。
作为本发明的进一步改进，所述半导体封装结构中，在所述低压增强型半导体晶体管的源极与所述高压耗尽型半导体晶体管的栅极之间并联有一个或多个电容元件。
本发明的有益效果是：
新的级联结构方式，主要采用高压耗尽型半导体晶体管源极通孔技术，将源极引导在衬底背面，将高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极通过金属陶瓷支撑片进行电连接，具有降低寄生电感、提高器件工作性能、且节约封装空间的优点；
将管壳端子的导电板进行延伸，使得晶体管电极间与管壳端子间电连接的导线进一步缩短，减少封装过程引入的寄生电感和寄生电阻，提高了晶体管的工作性能；
在高压耗尽型半导体晶体管的栅极与低压增强型半导体晶体管源极间串联电阻元件或并联电容元件，降低了电噪声以及电磁干扰的产生，防止了栅极驱动发生故障，提高了晶体管工作的可靠性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中耗尽型器件与增强型器件级联电连接的电路图；
图2a、2b为另一现有技术中耗尽型器件与增强型器件级联电连接的电路图；
图3为现有技术中对应级联电路的电感分布图；
图4为再一现有技术中耗尽型器件与增强型器件级联电连接的电路图；
图5为本发明实施例一中高压耗尽型半导体晶体管结构示意图；
图6为本发明实施例一中半导体封装结构的示意图；
图7为本发明实施例一中半导体封装结构对应的电感分布图；
图8为本发明实施例二中半导体封装结构的示意图；
图9为本发明实施例三中半导体封装结构的示意图；
图10为本发明实施例四中半导体封装结构的示意图。
具体实施方式
本发明公开了一种基于级联电路的半导体封装结构，包括：
高压耗尽型半导体晶体管，其包括源极、栅极及漏极；
低压增强型半导体晶体管，其包括源极、栅极及漏极；
导电支撑片，所述高压耗尽型半导体晶体管和所述低压增强型半导体晶体管固定于导电支撑片上；
管壳，所述管壳上设有高压端子、第一低压端子及第二低压端子；
级联电路，所述高压耗尽型半导体晶体管、低压增强型半导体晶体管及管壳间通过级联电路电连接，其中，所述高压耗尽型半导体晶体管的漏极电连接所述管壳的高压端子；所述高压耗尽型半导体晶体管的栅极和低压增强型半导体晶体管的源极分别与第一低压端子电连接；所述低压增强型半导体晶体管的栅极与所述管壳的第二低压端子电连接；所述高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极直接固定于导电支撑片上并导电支撑片电连接。
本发明的级联电路中，高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极通过导电支撑片电连接，无需借助导线，可有效减少引入的寄生电感和寄生电阻，提高器件的工作性能。
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所作出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
此外，在不同的实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例或结构之间具有任何关联性。
实施例一：
图6给出了本发明实施例一提供的基于级联电路的半导体封装结构。如图6所示，该半导体封装结构300中包括高压耗尽型半导体晶体管、低压增强型半导体晶体管、管壳、以及级联电路，其中：
低压增强型半导体晶体管320，该低压增强型半导体晶体管320可以是硅半导体场效应晶体管，优选地，本实施例中为垂直结构的低压增强型半导体晶体管。
低压增强型半导体晶体管的源极308和栅极310位于同侧，漏极309位于相对栅源极另一侧。
高压耗尽型半导体晶体管，可以是氮化镓半导体晶体管，也可以是其它半导体材料形成的高压半导体晶体管。
图5给出了本发明实施例一中使用的高压耗尽型半导体晶体管304的结构示意图。如图5所示，高压耗尽型半导体晶体管304包括：
衬底401；
位于衬底上的沟道层402和势垒层405，沟道层402和势垒层405在界面处形成二维电子气403；
位于沟道层上的源极欧姆金属404-1、漏极404-2、以及位于势垒层上的栅极408；
通孔409，通孔409位于高压耗尽型半导体晶体管的源极欧姆金属404-1背面，且通孔409的方向由衬底401的背面指向源极欧姆金属404-1方向；
通孔金属410，通孔金属410位于通孔409内，且与源极欧姆金属404-1电连接；
背金属411，背金属411位于衬底401材料背面，且与通孔金属410电连接；
高压耗尽型半导体晶体管304的源极450是由源极欧姆金属404-1、通孔金属410以及背金属411共同形成。
优选地，参图5所示，本实施例中的高压耗尽型半导体晶体管304的势垒层上进一步还覆盖有栅介质层407和表面钝化介质层406，栅介质层407主要用于调节高压耗尽型半导体晶体管栅极下方沟道中二维电子气的控制电压，调节器件栅极阈值电压，同时用于改善栅极金属下方材料界面，减少栅极漏电；表面钝化介质层406可有效降低材料表面表面态浓度，抑制或减少晶体管发生电流崩塌效应。
在该级联电路中：
高压耗尽型半导体晶体管304和低压增强型半导体晶体管320固定于同一金属陶瓷支撑片302上，并组装于管壳301内；
高压耗尽型半导体晶体管304的源极306背金属一面以及低压增强型半导体晶体管320的漏极309一面与金属陶瓷支撑片302电连接，即高压耗尽型半导体晶体管304的源极电306与低压增强型半导体晶体管320的漏极309通过金属陶瓷支撑片302进行电连接；
高压耗尽型半导体晶体管304的漏极305通过导线311电连接到管壳301的高压端子303；
低压增强型半导体晶体管320的源极308与高压耗尽型半导体晶体管304的栅极307通过导线390电连接之后，再与管壳301的第一低压端子330通过导线390电连接；
低压增强型半导体晶体管320的栅极310通过导线380电连接到管壳301的第二低压端子331；
整个半导体组装器件的工作过程中，低压增强型半导体晶体管320的漏极电压VDS就成了高压耗尽型半导体晶体管304的负栅极电压VGS，从而自动提供必要的负偏压以实现高压耗尽型半导体晶体管304的关断操作。
同时，高压耗尽型半导体晶体管304的结构采用了通孔金属工艺、背金属工艺以及欧姆金属共同作为了源极306，通过金属陶瓷支撑片302与低压增强型半导体晶体管320的漏极309实现电连接，无需借助导线进行电连接，从而大大降低了导线电连接引入的寄生电感。
优选地，本实施例中以金属陶瓷支撑片为例进行说明，在其他实施例中也可以选用其他材质的导电支撑片电连接高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极。
另外，晶体管电极间的空间进一步缩小，部分实现电连接导线长度缩短，不但可以进一步减少寄生电感和电阻，也降低了加工的成本。
因此，本发明既可以实现高压增强型特性，又提高了晶体管的工作性能。
图7给出了图6所示的本发明实施例一的级联电路电感分布图。
该级联电路中，寄生电感以及寄生电阻主要是由于电连接过程引起的，寄生电感以及寄生电阻越大，对器件工作过程中信号的切换速率以及整个工作的效率都会受到影响。与图3给出的现有技术中级联电路电感分布相比，通过本发明中金属陶瓷支撑片302与低压增强型半导体晶体管320的漏极309实现电连接，无需借助导线进行电连接，可以抑制该电连接间引入的寄生电感Lint1和寄生电阻，同时由于上述技术的改进，有利于晶体管电极间的空间进一步缩小，部分实现电连接导线长度缩短，可以进一步减少寄生电感(Lint3’＜Lint3；Lint2’＜Lint2)和寄生电阻，而且降低了制造的成本。
实施例二：
图8给出了本发明实施例二提供的基于级联电路的半导体封装结构。
如图8所示，与实施例一不同的是，本实施例二提供的半导体封装结构500a是在实施例一的基础上，将管壳501的高压端子503、第一低压端子530和第二低压端子531的导电板进行延伸。高压耗尽型半导体晶体管504的漏极505通过导线511电连接与管壳501的高压端子503；高压耗尽型半导体晶体管504的栅极507与低压增强型半导体晶体管520的源极508通过导线590电连接后，再与管壳501的第一低压端子530电连接；高压耗尽型半导体晶体管504的源极506与低压增强型半导体晶体管520的漏极509通过金属陶瓷支撑片502电连接；低压增强型半导体晶体管520的栅极510通过导线580电连接至管壳501的第二低压端子531。
与本发明实施例一提供的级联电路相比，本发明实施例二提供的级联电路使得晶体管电极间与管壳端子间电连接的导线进一步缩短，因此可以进一步减少封装过程引入的寄生电感和寄生电阻，提高晶体管的工作性能。
实施例三：
图9给出了本发明实施例三提供的基于级联电路的半导体封装结构。
如图9所示，与实施例一不同的是，本实施例三提供的半导体封装结构500b是在实施例二的基础上将高压耗尽型半导体晶体管504的栅极507与低压增强型半导体晶体管520的源极508通过串联一个或多个电阻元件524进行电连接，且半导体晶体管520的源极508通过导线与管壳501的第一低压端子530电连接；
与本发明实施例一和实施例二提供的级联电路相比，本发明实施例三提供的级联电路中，在高压耗尽型半导体晶体管的栅极与低压增强型半导体晶体管源极通过电阻元件电连接，且低压增强型半导体晶体管源极通过导线与管壳的第一低压端子530电连接。引入电阻元件的目的是当给定输入电压后，增加的电阻限制了信号转化速率，降低电噪声以及电磁干扰的产生，防止了栅极驱动发生故障，提高了晶体管工作的可靠性能。
实施例四：
图10给出了本发明实施例四提供的基于级联电路的半导体封装结构。
如图10所示，与实施例一不同的是，本实施例三提供的半导体封装结构500c是在实施例二的基础上将高压耗尽型半导体晶体管504的栅极507与低压增强型半导体晶体管520的源极508通过导线与管壳501的第一低压端子530电连接，且在高压耗尽型半导体晶体管504的栅极507与低压增强型半导体晶体管520的源极508通过导线与管壳501的第一低压端子530电连接的基础上并联一个或多个电容元件525。
与本发明实施例一和实施例二提供的级联电路相比，本发明实施例三提供的级联电路中，在高压耗尽型半导体晶体管的栅极与低压增强型半导体晶体管源极间并联电容元件的目的是当给定输入电压后，增加的电容可有效降低电噪声以及电磁干扰的产生，防止了栅极驱动发生故障，提高了晶体管工作的可靠性能。
由以上技术方案可以看出，本发明具有以下有益效果：
新的级联结构方式，主要采用高压耗尽型半导体晶体管源极通孔技术，将源极引导在衬底背面，将高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极通过金属陶瓷支撑片进行电连接，具有降低寄生电感、提高器件工作性能、且节约封装空间的优点；
将管壳端子的导电板进行延伸，使得晶体管电极间与管壳端子间电连接的导线进一步缩短，减少封装过程引入的寄生电感和寄生电阻，提高了晶体管的工作性能；
在高压耗尽型半导体晶体管的栅极与低压增强型半导体晶体管源极间串联电阻元件或并联电容元件，降低了电噪声以及电磁干扰的产生，防止了栅极驱动发生故障，提高了晶体管工作的可靠性能。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (11)

1.一种基于级联电路的半导体封装结构，其特征在于，所述半导体封装结构包括：
高压耗尽型半导体晶体管，其包括源极、栅极及漏极；
低压增强型半导体晶体管，其包括源极、栅极及漏极；
导电支撑片，所述高压耗尽型半导体晶体管和所述低压增强型半导体晶体管固定于导电支撑片上；
管壳，所述管壳上设有高压端子、第一低压端子及第二低压端子；
级联电路，所述高压耗尽型半导体晶体管、低压增强型半导体晶体管及管壳间通过级联电路电连接，其中，所述高压耗尽型半导体晶体管的漏极电连接所述管壳的高压端子；所述高压耗尽型半导体晶体管的栅极和低压增强型半导体晶体管的源极分别与第一低压端子电连接；所述低压增强型半导体晶体管的栅极与所述管壳的第二低压端子电连接；所述高压耗尽型半导体晶体管的源极与低压增强型半导体晶体管的漏极直接固定于导电支撑片上并与导电支撑片电连接。
2.根据权利要求1所述的半导体封装结构，其特征在于，所述导电支撑片为金属陶瓷支撑片。
3.根据权利要求1所述的半导体封装结构，其特征在于，所述高压耗尽型半导体晶体管包括：
衬底；
位于衬底上的沟道层和势垒层，沟道层和势垒层在界面处形成二维电子气；
位于沟道层上的源极欧姆金属、漏极、以及位于势垒层上的栅极；
通孔，所述通孔位于所述高压耗尽型半导体晶体管的源极欧姆金属背面，且所述通孔的方向由所述衬底的背面指向所述源极欧姆金属方向；
通孔金属，所述通孔金属位于所述通孔内，且与所述的源极欧姆金属电连接；
背金属，所述背金属位于所述衬底背面，且与所述通孔金属电连接；
其中，所述高压耗尽型半导体晶体管的源极由源极欧姆金属、通孔金属以及背金属共同形成。
4.根据权利要求3所述的半导体封装结构，其特征在于，所述高压耗尽型半导体晶体管中的背金属固定于所述导电支撑片上，且与导电支撑片电连接。
5.根据权利要求3所述的半导体封装结构，其特征在于，所述高压耗尽型半导体晶体管还包括位于势垒层上的栅介质层和/或表面钝化介质层。
6.根据权利要求1所述的半导体封装结构，其特征在于，所述低压增强型半导体晶体管的源极和栅极位于同侧，漏极位于相对栅源极的另一侧。
7.根据权利要求1所述的半导体封装结构，其特征在于，所述高压耗尽型半导体晶体管为氮化镓半导体晶体管，所述低压增强型半导体晶体管为硅半导体场效应晶体管。
8.根据权利要求1所述的半导体封装结构，其特征在于，所述低压增强型半导体晶体管为垂直结构的增强型半导体晶体管。
9.根据权利要求1所述的半导体封装结构，其特征在于，所述半导体封装结构中：
所述高压耗尽型半导体晶体管的漏极与管壳的高压端子通过导线电连接；
所述低压增强型半导体晶体管的源极与所述高压耗尽型半导体晶体管的栅极通过导线电连接，所述低压增强型半导体晶体管的源极或所述高压耗尽型半导体晶体管的栅极与所述管壳的第一低压端子通过导线电连接；
所述低压增强型半导体晶体管的栅极与所述管壳的第二低压端子通过导线电连接。
10.根据权利要求1所述的半导体封装结构，其特征在于，所述半导体封装结构中，在所述低压增强型半导体晶体管的源极与所述高压耗尽型半导体晶体管的栅极之间串联有一个或多个电阻元件。
11.根据权利要求1所述的半导体封装结构，其特征在于，所述半导体封装结构中，在所述低压增强型半导体晶体管的源极与所述高压耗尽型半导体晶体管的栅极之间并联有一个或多个电容元件。
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